[binutils-gdb] aarch64: Add new test advsimd-modified-immediate.d
Alice Carlotti
acarlotti@sourceware.org
Fri May 9 19:38:14 GMT 2025
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=42ebdfe15d6935126d25a92a2b8aace6830e4d88
commit 42ebdfe15d6935126d25a92a2b8aace6830e4d88
Author: Alice Carlotti <alice.carlotti@arm.com>
Date: Sun Apr 20 23:00:36 2025 +0100
aarch64: Add new test advsimd-modified-immediate.d
All instructions (7 opcode table entries) were previously untested.
Diff:
---
.../gas/aarch64/advsimd-modified-immediate.d | 103 +++++++++++++++++++++
.../gas/aarch64/advsimd-modified-immediate.s | 98 ++++++++++++++++++++
2 files changed, 201 insertions(+)
diff --git a/gas/testsuite/gas/aarch64/advsimd-modified-immediate.d b/gas/testsuite/gas/aarch64/advsimd-modified-immediate.d
new file mode 100644
index 00000000000..ecfd3372f00
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/advsimd-modified-immediate.d
@@ -0,0 +1,103 @@
+#as: -march=armv8-a
+#objdump: -dr
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+
+0+ <\.text>:
+ *[0-9a-f]+: 0f009400 orr v0\.4h, #0x0
+ *[0-9a-f]+: 0f00941f orr v31\.4h, #0x0
+ *[0-9a-f]+: 0f0097e0 orr v0\.4h, #0x1f
+ *[0-9a-f]+: 0f0797e0 orr v0\.4h, #0xff
+ *[0-9a-f]+: 0f009400 orr v0\.4h, #0x0
+ *[0-9a-f]+: 0f00b400 orr v0\.4h, #0x0, lsl #8
+ *[0-9a-f]+: 4f009400 orr v0\.8h, #0x0
+ *[0-9a-f]+: 4f00941f orr v31\.8h, #0x0
+ *[0-9a-f]+: 4f0097e0 orr v0\.8h, #0x1f
+ *[0-9a-f]+: 4f0797e0 orr v0\.8h, #0xff
+ *[0-9a-f]+: 4f0797e0 orr v0\.8h, #0xff
+ *[0-9a-f]+: 4f07b7e0 orr v0\.8h, #0xff, lsl #8
+ *[0-9a-f]+: 0f001400 orr v0\.2s, #0x0
+ *[0-9a-f]+: 0f00141f orr v31\.2s, #0x0
+ *[0-9a-f]+: 0f0017e0 orr v0\.2s, #0x1f
+ *[0-9a-f]+: 0f0717e0 orr v0\.2s, #0xff
+ *[0-9a-f]+: 0f001400 orr v0\.2s, #0x0
+ *[0-9a-f]+: 0f003400 orr v0\.2s, #0x0, lsl #8
+ *[0-9a-f]+: 0f005400 orr v0\.2s, #0x0, lsl #16
+ *[0-9a-f]+: 0f007400 orr v0\.2s, #0x0, lsl #24
+ *[0-9a-f]+: 4f001400 orr v0\.4s, #0x0
+ *[0-9a-f]+: 4f00141f orr v31\.4s, #0x0
+ *[0-9a-f]+: 4f0017e0 orr v0\.4s, #0x1f
+ *[0-9a-f]+: 4f0717e0 orr v0\.4s, #0xff
+ *[0-9a-f]+: 4f0717e0 orr v0\.4s, #0xff
+ *[0-9a-f]+: 4f0737e0 orr v0\.4s, #0xff, lsl #8
+ *[0-9a-f]+: 4f0757e0 orr v0\.4s, #0xff, lsl #16
+ *[0-9a-f]+: 4f0777e0 orr v0\.4s, #0xff, lsl #24
+ *[0-9a-f]+: 2f008400 mvni v0\.4h, #0x0
+ *[0-9a-f]+: 2f00841f mvni v31\.4h, #0x0
+ *[0-9a-f]+: 2f0087e0 mvni v0\.4h, #0x1f
+ *[0-9a-f]+: 2f0787e0 mvni v0\.4h, #0xff
+ *[0-9a-f]+: 2f008400 mvni v0\.4h, #0x0
+ *[0-9a-f]+: 2f00a400 mvni v0\.4h, #0x0, lsl #8
+ *[0-9a-f]+: 6f008400 mvni v0\.8h, #0x0
+ *[0-9a-f]+: 6f00841f mvni v31\.8h, #0x0
+ *[0-9a-f]+: 6f0087e0 mvni v0\.8h, #0x1f
+ *[0-9a-f]+: 6f0787e0 mvni v0\.8h, #0xff
+ *[0-9a-f]+: 6f0787e0 mvni v0\.8h, #0xff
+ *[0-9a-f]+: 6f07a7e0 mvni v0\.8h, #0xff, lsl #8
+ *[0-9a-f]+: 2f000400 mvni v0\.2s, #0x0
+ *[0-9a-f]+: 2f00041f mvni v31\.2s, #0x0
+ *[0-9a-f]+: 2f0007e0 mvni v0\.2s, #0x1f
+ *[0-9a-f]+: 2f0707e0 mvni v0\.2s, #0xff
+ *[0-9a-f]+: 2f000400 mvni v0\.2s, #0x0
+ *[0-9a-f]+: 2f002400 mvni v0\.2s, #0x0, lsl #8
+ *[0-9a-f]+: 2f004400 mvni v0\.2s, #0x0, lsl #16
+ *[0-9a-f]+: 2f006400 mvni v0\.2s, #0x0, lsl #24
+ *[0-9a-f]+: 6f000400 mvni v0\.4s, #0x0
+ *[0-9a-f]+: 6f00041f mvni v31\.4s, #0x0
+ *[0-9a-f]+: 6f0007e0 mvni v0\.4s, #0x1f
+ *[0-9a-f]+: 6f0707e0 mvni v0\.4s, #0xff
+ *[0-9a-f]+: 6f0707e0 mvni v0\.4s, #0xff
+ *[0-9a-f]+: 6f0727e0 mvni v0\.4s, #0xff, lsl #8
+ *[0-9a-f]+: 6f0747e0 mvni v0\.4s, #0xff, lsl #16
+ *[0-9a-f]+: 6f0767e0 mvni v0\.4s, #0xff, lsl #24
+ *[0-9a-f]+: 2f00c400 mvni v0\.2s, #0x0, msl #8
+ *[0-9a-f]+: 2f00c41f mvni v31\.2s, #0x0, msl #8
+ *[0-9a-f]+: 2f00c7e0 mvni v0\.2s, #0x1f, msl #8
+ *[0-9a-f]+: 2f07c7e0 mvni v0\.2s, #0xff, msl #8
+ *[0-9a-f]+: 2f00d400 mvni v0\.2s, #0x0, msl #16
+ *[0-9a-f]+: 6f00c400 mvni v0\.4s, #0x0, msl #8
+ *[0-9a-f]+: 6f00c41f mvni v31\.4s, #0x0, msl #8
+ *[0-9a-f]+: 6f00c7e0 mvni v0\.4s, #0x1f, msl #8
+ *[0-9a-f]+: 6f07c7e0 mvni v0\.4s, #0xff, msl #8
+ *[0-9a-f]+: 6f07d7e0 mvni v0\.4s, #0xff, msl #16
+ *[0-9a-f]+: 2f009400 bic v0\.4h, #0x0
+ *[0-9a-f]+: 2f00941f bic v31\.4h, #0x0
+ *[0-9a-f]+: 2f0097e0 bic v0\.4h, #0x1f
+ *[0-9a-f]+: 2f0797e0 bic v0\.4h, #0xff
+ *[0-9a-f]+: 2f009400 bic v0\.4h, #0x0
+ *[0-9a-f]+: 2f00b400 bic v0\.4h, #0x0, lsl #8
+ *[0-9a-f]+: 6f009400 bic v0\.8h, #0x0
+ *[0-9a-f]+: 6f00941f bic v31\.8h, #0x0
+ *[0-9a-f]+: 6f0097e0 bic v0\.8h, #0x1f
+ *[0-9a-f]+: 6f0797e0 bic v0\.8h, #0xff
+ *[0-9a-f]+: 6f0797e0 bic v0\.8h, #0xff
+ *[0-9a-f]+: 6f07b7e0 bic v0\.8h, #0xff, lsl #8
+ *[0-9a-f]+: 2f001400 bic v0\.2s, #0x0
+ *[0-9a-f]+: 2f00141f bic v31\.2s, #0x0
+ *[0-9a-f]+: 2f0017e0 bic v0\.2s, #0x1f
+ *[0-9a-f]+: 2f0717e0 bic v0\.2s, #0xff
+ *[0-9a-f]+: 2f001400 bic v0\.2s, #0x0
+ *[0-9a-f]+: 2f003400 bic v0\.2s, #0x0, lsl #8
+ *[0-9a-f]+: 2f005400 bic v0\.2s, #0x0, lsl #16
+ *[0-9a-f]+: 2f007400 bic v0\.2s, #0x0, lsl #24
+ *[0-9a-f]+: 6f001400 bic v0\.4s, #0x0
+ *[0-9a-f]+: 6f00141f bic v31\.4s, #0x0
+ *[0-9a-f]+: 6f0017e0 bic v0\.4s, #0x1f
+ *[0-9a-f]+: 6f0717e0 bic v0\.4s, #0xff
+ *[0-9a-f]+: 6f0717e0 bic v0\.4s, #0xff
+ *[0-9a-f]+: 6f0737e0 bic v0\.4s, #0xff, lsl #8
+ *[0-9a-f]+: 6f0757e0 bic v0\.4s, #0xff, lsl #16
+ *[0-9a-f]+: 6f0777e0 bic v0\.4s, #0xff, lsl #24
diff --git a/gas/testsuite/gas/aarch64/advsimd-modified-immediate.s b/gas/testsuite/gas/aarch64/advsimd-modified-immediate.s
new file mode 100644
index 00000000000..af64f2e5d1f
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/advsimd-modified-immediate.s
@@ -0,0 +1,98 @@
+// movi and fmov are tested elsewhere, so skipped here.
+
+ orr v0.4h, #0
+ orr v31.4h, #0
+ orr v0.4h, #31
+ orr v0.4h, #255
+ orr v0.4h, #0, lsl #0
+ orr v0.4h, #0, lsl #8
+ orr v0.8h, #0
+ orr v31.8h, #0
+ orr v0.8h, #31
+ orr v0.8h, #255
+ orr v0.8h, #255, lsl #0
+ orr v0.8h, #255, lsl #8
+ orr v0.2s, #0
+ orr v31.2s, #0
+ orr v0.2s, #31
+ orr v0.2s, #255
+ orr v0.2s, #0, lsl #0
+ orr v0.2s, #0, lsl #8
+ orr v0.2s, #0, lsl #16
+ orr v0.2s, #0, lsl #24
+ orr v0.4s, #0
+ orr v31.4s, #0
+ orr v0.4s, #31
+ orr v0.4s, #255
+ orr v0.4s, #255, lsl #0
+ orr v0.4s, #255, lsl #8
+ orr v0.4s, #255, lsl #16
+ orr v0.4s, #255, lsl #24
+
+ mvni v0.4h, #0
+ mvni v31.4h, #0
+ mvni v0.4h, #31
+ mvni v0.4h, #255
+ mvni v0.4h, #0, lsl #0
+ mvni v0.4h, #0, lsl #8
+ mvni v0.8h, #0
+ mvni v31.8h, #0
+ mvni v0.8h, #31
+ mvni v0.8h, #255
+ mvni v0.8h, #255, lsl #0
+ mvni v0.8h, #255, lsl #8
+ mvni v0.2s, #0
+ mvni v31.2s, #0
+ mvni v0.2s, #31
+ mvni v0.2s, #255
+ mvni v0.2s, #0, lsl #0
+ mvni v0.2s, #0, lsl #8
+ mvni v0.2s, #0, lsl #16
+ mvni v0.2s, #0, lsl #24
+ mvni v0.4s, #0
+ mvni v31.4s, #0
+ mvni v0.4s, #31
+ mvni v0.4s, #255
+ mvni v0.4s, #255, lsl #0
+ mvni v0.4s, #255, lsl #8
+ mvni v0.4s, #255, lsl #16
+ mvni v0.4s, #255, lsl #24
+ mvni v0.2s, #0, msl #8
+ mvni v31.2s, #0, msl #8
+ mvni v0.2s, #31, msl #8
+ mvni v0.2s, #255, msl #8
+ mvni v0.2s, #0, msl #16
+ mvni v0.4s, #0, msl #8
+ mvni v31.4s, #0, msl #8
+ mvni v0.4s, #31, msl #8
+ mvni v0.4s, #255, msl #8
+ mvni v0.4s, #255, msl #16
+
+ bic v0.4h, #0
+ bic v31.4h, #0
+ bic v0.4h, #31
+ bic v0.4h, #255
+ bic v0.4h, #0, lsl #0
+ bic v0.4h, #0, lsl #8
+ bic v0.8h, #0
+ bic v31.8h, #0
+ bic v0.8h, #31
+ bic v0.8h, #255
+ bic v0.8h, #255, lsl #0
+ bic v0.8h, #255, lsl #8
+ bic v0.2s, #0
+ bic v31.2s, #0
+ bic v0.2s, #31
+ bic v0.2s, #255
+ bic v0.2s, #0, lsl #0
+ bic v0.2s, #0, lsl #8
+ bic v0.2s, #0, lsl #16
+ bic v0.2s, #0, lsl #24
+ bic v0.4s, #0
+ bic v31.4s, #0
+ bic v0.4s, #31
+ bic v0.4s, #255
+ bic v0.4s, #255, lsl #0
+ bic v0.4s, #255, lsl #8
+ bic v0.4s, #255, lsl #16
+ bic v0.4s, #255, lsl #24
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