[binutils-gdb] doc/riscv: Add description of disassembler options

[Nelson Chu]

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=b667765b2c3e098c5930c28c2f89584523bf99d6

commit b667765b2c3e098c5930c28c2f89584523bf99d6
Author: Marek Pikuła <m.pikula@partner.samsung.com>
Date:   Thu Mar 27 15:09:14 2025 +0100

    doc/riscv: Add description of disassembler options
    
    Up to this point, no mention of RISC-V-specific disassembler options was
    mentioned in binutils documentation. This patch includes description for
    all of the currently supported options.
    
    Signed-off-by: Marek Pikuła <m.pikula@partner.samsung.com>

Diff:
---
 binutils/doc/binutils.texi | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/binutils/doc/binutils.texi b/binutils/doc/binutils.texi
index 73848e3b390..5bf5d80b85b 100644
--- a/binutils/doc/binutils.texi
+++ b/binutils/doc/binutils.texi
@@ -2701,6 +2701,23 @@ If you disassemble without giving a CPU selection, a default will be
 chosen from information gleaned by BFD from the object files headers,
 but the result again may not be as you expect.
 
+For RISC-V, the following options are supported:
+
+@table @code
+@item numeric
+Print numeric register names, rather than ABI names (e.g., print @code{x2}
+instead of @code{sp}).
+
+@item no-aliases
+Disassemble only into canonical instructions. For example, compressed
+instructions will be represented as such (@code{addi sp,sp,-128} will be
+@code{c.addi16sp sp,-128}).
+
+@item priv-spec=@var{SPEC}
+Print the CSR according to the chosen privilege spec version (e.g.,
+@code{1.10}, @code{1.11}, @code{1.12}).
+@end table
+
 For MIPS, this option controls the printing of instruction mnemonic
 names and register names in disassembled instructions.  Multiple
 selections from the following may be specified as a comma separated