https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=3165109751f9478fdce8fee451a8842034b07762
commit 3165109751f9478fdce8fee451a8842034b07762
Author: Ezra Sitorus <ezra.sitorus@arm.com>
Date: Thu Jun 19 10:40:43 2025 +0100
aarch64: Support for FEAT_SVE_BFSCALE
FEAT_SVE_BFSCALE introduces the SVE BFSCALE instruction, when the PE is not in
Streaming SVE mode. If FEAT_SME2 is implemented, FEAT_SVE_BFSCALE also
introduces SME multi-vector Z-targeting BFloat16 scaling instructions, BFSCALE
and BFMUL.
Diff:
---
gas/config/tc-aarch64.c | 4 +
gas/doc/c-aarch64.texi | 2 +
gas/testsuite/gas/aarch64/sve-b16b16-sve2-bad-2.l | 4 +-
gas/testsuite/gas/aarch64/sve-bfscale-bad.d | 4 +
gas/testsuite/gas/aarch64/sve-bfscale-bad.l | 26 +
gas/testsuite/gas/aarch64/sve-bfscale-bad.s | 27 +
gas/testsuite/gas/aarch64/sve-bfscale-sme2-bad.d | 4 +
gas/testsuite/gas/aarch64/sve-bfscale-sme2-bad.l | 41 +
gas/testsuite/gas/aarch64/sve-bfscale-sme2.d | 66 +
gas/testsuite/gas/aarch64/sve-bfscale-sme2.s | 57 +
gas/testsuite/gas/aarch64/sve-bfscale-sve2.d | 18 +
gas/testsuite/gas/aarch64/sve-bfscale-sve2.s | 9 +
include/opcode/aarch64.h | 5 +
opcodes/aarch64-asm-2.c | 71 +-
opcodes/aarch64-dis-2.c | 1435 +++++++++++----------
opcodes/aarch64-opc-2.c | 1 +
opcodes/aarch64-opc.c | 2 +
opcodes/aarch64-tbl.h | 23 +
18 files changed, 1072 insertions(+), 727 deletions(-)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 0fd74aaa999..42a3115102d 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -6820,6 +6820,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
case AARCH64_OPND_SVE_Zn:
case AARCH64_OPND_SVE_Zt:
case AARCH64_OPND_SME_Zm:
+ case AARCH64_OPND_SME_Zm_17:
reg_type = REG_TYPE_Z;
goto vector_reg;
@@ -10726,6 +10727,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
{"ite", AARCH64_FEATURE (ITE), AARCH64_NO_FEATURES},
{"d128", AARCH64_FEATURE (D128), D128_FEATURE_DEPS},
{"sve-b16b16", AARCH64_FEATURE (SVE_B16B16), AARCH64_NO_FEATURES},
+ {"sve-bfscale", AARCH64_FEATURE (SVE_BFSCALE), AARCH64_NO_FEATURES},
{"sme2p1", AARCH64_FEATURE (SME2p1), AARCH64_FEATURE (SME2)},
{"sve2p1", AARCH64_FEATURE (SVE2p1), AARCH64_FEATURE (SVE2)},
{"rcpc3", AARCH64_FEATURE (RCPC3), AARCH64_FEATURE (RCPC2)},
@@ -10775,6 +10777,8 @@ static const struct aarch64_virtual_dependency_table aarch64_dependencies[] = {
SVE2p1_SME2p1)},
{AARCH64_FEATURE (SME), AARCH64_FEATURE (SVE2p1_SME)},
{AARCH64_FEATURE (SME2), AARCH64_FEATURE (SVE2p1_SME2)},
+ {AARCH64_FEATURE (SVE2), AARCH64_FEATURE (SVE2_SME2)},
+ {AARCH64_FEATURE (SME2), AARCH64_FEATURE (SVE2_SME2)},
{AARCH64_FEATURE (SME2p1), AARCH64_FEATURE (SVE2p1_SME2p1)},
};
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 74ce717a746..1d5fac1adcd 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -299,6 +299,8 @@ automatically cause those extensions to be disabled.
@tab Enable the Scalable Vector Extension.
@item @code{sve-b16b16} @tab
@tab Enable the SVE B16B16 extension. These instructions also require either @code{+sve2} or @code{+sme2}.
+@item @code{sve-bfscale} @tab
+@tab Enable the SVE BFSCALE extension. These instructions also require either @code{+sve2} or @code{+sme2}.
@item @code{sve2} @tab @code{sve}
@tab Enable SVE2.
@item @code{sve2-aes} @tab @code{sve2}, @code{aes}
diff --git a/gas/testsuite/gas/aarch64/sve-b16b16-sve2-bad-2.l b/gas/testsuite/gas/aarch64/sve-b16b16-sve2-bad-2.l
index 83f00f55bd0..2ede0c95de7 100644
--- a/gas/testsuite/gas/aarch64/sve-b16b16-sve2-bad-2.l
+++ b/gas/testsuite/gas/aarch64/sve-b16b16-sve2-bad-2.l
@@ -237,8 +237,8 @@
.*: Error: operand mismatch -- `bfmul z31.b,z31.s,z31.d\[8\]'
.*: Info: did you mean this\?
.*: Info: bfmul z31.h, z31.h, z31.h\[8\]
-.*: Error: expected an SVE vector register at operand 1 -- `bfmul { ?z0.h ?},z0.h,z0.h\[1\]'
-.*: Error: expected an SVE vector register at operand 1 -- `bfmul { ?z0.h-z0.h ?},z0.h\[2\]'
+.*: Error: missing braces at operand 2 -- `bfmul { ?z0.h ?},z0.h,z0.h\[1\]'
+.*: Error: invalid range in vector register list at operand 1 -- `bfmul { ?z0.h-z0.h ?},z0.h\[2\]'
.*: Error: expected an SVE predicate register at operand 2 -- `bfmul z0.h,z0.h\[3\]'
.*: Error: operand mismatch -- `bfsub z0.b,z0.h,z0.h'
.*: Info: did you mean this\?
diff --git a/gas/testsuite/gas/aarch64/sve-bfscale-bad.d b/gas/testsuite/gas/aarch64/sve-bfscale-bad.d
new file mode 100644
index 00000000000..297fb30ad71
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve-bfscale-bad.d
@@ -0,0 +1,4 @@
+#name: Invalid SVE_BFSCALE instructions
+#as: -march=armv8-a+sve-bfscale+sme2
+#source: sve-bfscale-bad.s
+#error_output: sve-bfscale-bad.l
diff --git a/gas/testsuite/gas/aarch64/sve-bfscale-bad.l b/gas/testsuite/gas/aarch64/sve-bfscale-bad.l
new file mode 100644
index 00000000000..7cddb25c1f7
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve-bfscale-bad.l
@@ -0,0 +1,26 @@
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `bfscale z0\.h,p0/m,z1\.h,z0\.h'
+[^ :]+:[0-9]+: Error: operand mismatch -- `bfscale z0\.h,p0/z,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: bfscale z0\.h, p0/m, z0\.h, z0\.h
+[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `bfscale { ?z0\.h-z1\.h ?},{ ?z0\.h-z2\.h ?},z0\.h'
+[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 1 -- `bfscale { ?z0\.h-z2\.h ?},{ ?z0\.h-z2\.h ?},z0\.h'
+[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 1 -- `bfscale { ?z0\.h-z4\.h ?},{ ?z0\.h-z4\.h ?},z0\.h'
+[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `bfscale { ?z0\.h-z1\.h ?},{ ?z0\.h-z2\.h ?},{ ?z0\.h-z1\.h ?}'
+[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 1 -- `bfscale { ?z0\.h-z2\.h ?},{ ?z0\.h-z2\.h ?},{ ?z0\.h-z1\.h ?}'
+[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 1 -- `bfscale { ?z0\.h-z4\.h ?},{ ?z0\.h-z4\.h ?},{ ?z0\.h-z1\.h ?}'
+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `bfscale { ?z0\.h-z1\.h ?},{ ?z0\.h-z1\.h ?},{ ?z0\.h-z2\.h ?}'
+[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 3 -- `bfscale { ?z0\.h-z3\.h ?},{ ?z0\.h-z3\.h ?},{ ?z0\.h-z1\.h ?}'
+[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 3 -- `bfscale { ?z0\.h-z3\.h ?},{ ?z0\.h-z3\.h ?},{ ?z0\.h-z4\.h ?}'
+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `bfmul { ?z0\.h-z1\.h ?},{ ?z0\.h-z2\.h ?},z0\.h'
+[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 1 -- `bfmul { ?z0\.h-z2\.h ?},{ ?z0\.h-z1\.h ?},z0\.h'
+[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `bfmul { ?z0\.h-z3\.h ?},{ ?z0\.h-z2\.h ?},z0\.h'
+[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `bfmul { ?z0\.h-z3\.h ?},{ ?z0\.h-z1\.h ?},z0\.h'
+[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `bfmul { ?z0\.h-z1\.h ?},{ ?z0\.h-z1\.h ?},z16\.h'
+[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `bfmul { ?z0\.h-z3\.h ?},{ ?z0\.h-z3\.h ?},z16\.h'
+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `bfmul { ?z0\.h-z1\.h ?},{ ?z0\.h-z2\.h ?},{ ?z0\.h-z1\.h ?}'
+[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 1 -- `bfmul { ?z0\.h-z2\.h ?},{ ?z0\.h-z1\.h ?},{ ?z0\.h-z1\.h ?}'
+[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `bfmul { ?z0\.h-z3\.h ?},{ ?z0\.h-z2\.h ?},{ ?z0\.h-z3\.h ?}'
+[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `bfmul { ?z0\.h-z3\.h ?},{ ?z0\.h-z1\.h ?},{ ?z0\.h-z3\.h ?}'
+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `bfmul { ?z0\.h-z1\.h ?},{ ?z0\.h-z1\.h ?},{ ?z0\.h-z2\.h ?}'
+[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 3 -- `bfmul { ?z0\.h-z3\.h ?},{ ?z0\.h-z3\.h ?},{ ?z0\.h-z2\.h ?}'
diff --git a/gas/testsuite/gas/aarch64/sve-bfscale-bad.s b/gas/testsuite/gas/aarch64/sve-bfscale-bad.s
new file mode 100644
index 00000000000..bcb8867aa66
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve-bfscale-bad.s
@@ -0,0 +1,27 @@
+bfscale:
+ bfscale z0.h, p0/m, z1.h, z0.h
+ bfscale z0.h, p0/z, z0.h, z0.h
+ bfscale {z0.h-z1.h}, {z0.h-z2.h}, z0.h
+ bfscale {z0.h-z2.h}, {z0.h-z2.h}, z0.h
+ bfscale {z0.h-z4.h}, {z0.h-z4.h}, z0.h
+ bfscale {z0.h-z1.h}, {z0.h-z2.h}, {z0.h-z1.h}
+ bfscale {z0.h-z2.h}, {z0.h-z2.h}, {z0.h-z1.h}
+ bfscale {z0.h-z4.h}, {z0.h-z4.h}, {z0.h-z1.h}
+ bfscale {z0.h-z1.h}, {z0.h-z1.h}, {z0.h-z2.h}
+ bfscale {z0.h-z3.h}, {z0.h-z3.h}, {z0.h-z1.h}
+ bfscale {z0.h-z3.h}, {z0.h-z3.h}, {z0.h-z4.h}
+
+bfmul:
+ bfmul {z0.h-z1.h}, {z0.h-z2.h}, z0.h
+ bfmul {z0.h-z2.h}, {z0.h-z1.h}, z0.h
+ bfmul {z0.h-z3.h}, {z0.h-z2.h}, z0.h
+ bfmul {z0.h-z3.h}, {z0.h-z1.h}, z0.h
+ bfmul {z0.h-z1.h}, {z0.h-z1.h}, z16.h
+ bfmul {z0.h-z3.h}, {z0.h-z3.h}, z16.h
+ bfmul {z0.h-z1.h}, {z0.h-z2.h}, {z0.h-z1.h}
+ bfmul {z0.h-z2.h}, {z0.h-z1.h}, {z0.h-z1.h}
+ bfmul {z0.h-z3.h}, {z0.h-z2.h}, {z0.h-z3.h}
+ bfmul {z0.h-z3.h}, {z0.h-z1.h}, {z0.h-z3.h}
+ bfmul {z0.h-z1.h}, {z0.h-z1.h}, {z0.h-z2.h}
+ bfmul {z0.h-z3.h}, {z0.h-z3.h}, {z0.h-z2.h}
+ bfmul {z0.h-z3.h}, {z0.h-z3.h}, {z0.h-z3.h}
diff --git a/gas/testsuite/gas/aarch64/sve-bfscale-sme2-bad.d b/gas/testsuite/gas/aarch64/sve-bfscale-sme2-bad.d
new file mode 100644
index 00000000000..ad6d365e288
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve-bfscale-sme2-bad.d
@@ -0,0 +1,4 @@
+#name: Negative SVE_BFSCALE test with missing +sme2 flag.
+#as: -march=armv8-a+sve-bfscale
+#source: sve-bfscale-sme2.s
+#error_output: sve-bfscale-sme2-bad.l
diff --git a/gas/testsuite/gas/aarch64/sve-bfscale-sme2-bad.l b/gas/testsuite/gas/aarch64/sve-bfscale-sme2-bad.l
new file mode 100644
index 00000000000..79ae8514744
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve-bfscale-sme2-bad.l
@@ -0,0 +1,41 @@
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: selected processor does not support `bfscale z0\.h,p0/m,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfscale z0\.h,p0/m,z0\.h,z31\.h'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfscale z0\.h,p7/m,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfscale z0\.h,p7/m,z0\.h,z31\.h'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfscale z31\.h,p0/m,z31\.h,z0\.h'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfscale z31\.h,p0/m,z31\.h,z31\.h'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfscale z31\.h,p7/m,z31\.h,z0\.h'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfscale z31\.h,p7/m,z31\.h,z31\.h'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfscale { ?z0\.h-z1\.h ?},{ ?z0\.h-z1\.h ?},z0\.h'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfscale { ?z0\.h-z1\.h ?},{ ?z0\.h-z1\.h ?},z15\.h'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfscale { ?z30\.h-z31\.h ?},{ ?z30\.h-z31\.h ?},z0\.h'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfscale { ?z30\.h-z31\.h ?},{ ?z30\.h-z31\.h ?},z15\.h'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfscale { ?z0\.h-z3\.h ?},{ ?z0\.h-z3\.h ?},z0\.h'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfscale { ?z0\.h-z3\.h ?},{ ?z0\.h-z3\.h ?},z15\.h'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfscale { ?z28\.h-z31\.h ?},{ ?z28\.h-z31\.h ?},z0\.h'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfscale { ?z28\.h-z31\.h ?},{ ?z28\.h-z31\.h ?},z15\.h'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfscale { ?z0\.h-z1\.h ?},{ ?z0\.h-z1\.h ?},{ ?z0\.h-z1\.h ?}'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfscale { ?z0\.h-z1\.h ?},{ ?z0\.h-z1\.h ?},{ ?z30\.h-z31\.h ?}'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfscale { ?z30\.h-z31\.h ?},{ ?z30\.h-z31\.h ?},{ ?z0\.h-z1\.h ?}'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfscale { ?z30\.h-z31\.h ?},{ ?z30\.h-z31\.h ?},{ ?z30\.h-z31\.h ?}'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfscale { ?z0\.h-z3\.h ?},{ ?z0\.h-z3\.h ?},{ ?z0\.h-z3\.h ?}'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfscale { ?z0\.h-z3\.h ?},{ ?z0\.h-z3\.h ?},{ ?z28\.h-z31\.h ?}'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfscale { ?z28\.h-z31\.h ?},{ ?z28\.h-z31\.h ?},{ ?z0\.h-z3\.h ?}'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfscale { ?z28\.h-z31\.h ?},{ ?z28\.h-z31\.h ?},{ ?z28\.h-z31\.h ?}'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfmul { ?z0\.h-z1\.h ?},{ ?z0\.h-z1\.h ?},z0\.h'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfmul { ?z0\.h-z1\.h ?},{ ?z0\.h-z1\.h ?},z15\.h'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfmul { ?z30\.h-z31\.h ?},{ ?z30\.h-z31\.h ?},z0\.h'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfmul { ?z30\.h-z31\.h ?},{ ?z30\.h-z31\.h ?},z15\.h'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfmul { ?z0\.h-z3\.h ?},{ ?z0\.h-z3\.h ?},z0\.h'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfmul { ?z0\.h-z3\.h ?},{ ?z0\.h-z3\.h ?},z15\.h'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfmul { ?z28\.h-z31\.h ?},{ ?z28\.h-z31\.h ?},z0\.h'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfmul { ?z28\.h-z31\.h ?},{ ?z28\.h-z31\.h ?},z15\.h'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfmul { ?z0\.h-z1\.h ?},{ ?z0\.h-z1\.h ?},{ ?z0\.h-z1\.h ?}'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfmul { ?z0\.h-z1\.h ?},{ ?z0\.h-z1\.h ?},{ ?z30\.h-z31\.h ?}'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfmul { ?z30\.h-z31\.h ?},{ ?z30\.h-z31\.h ?},{ ?z0\.h-z1\.h ?}'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfmul { ?z30\.h-z31\.h ?},{ ?z30\.h-z31\.h ?},{ ?z30\.h-z31\.h ?}'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfmul { ?z0\.h-z3\.h ?},{ ?z0\.h-z3\.h ?},{ ?z0\.h-z3\.h ?}'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfmul { ?z0\.h-z3\.h ?},{ ?z0\.h-z3\.h ?},{ ?z28\.h-z31\.h ?}'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfmul { ?z28\.h-z31\.h ?},{ ?z28\.h-z31\.h ?},{ ?z0\.h-z3\.h ?}'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfmul { ?z28\.h-z31\.h ?},{ ?z28\.h-z31\.h ?},{ ?z28\.h-z31\.h ?}'
diff --git a/gas/testsuite/gas/aarch64/sve-bfscale-sme2.d b/gas/testsuite/gas/aarch64/sve-bfscale-sme2.d
new file mode 100644
index 00000000000..84b76477ffd
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve-bfscale-sme2.d
@@ -0,0 +1,66 @@
+#name: SVE_BFSCALE + SME2 instructions test
+#as: -march=armv8-a+sve-bfscale+sme2
+#objdump: -dr
+
+.*: file format .*
+
+
+Disassembly of section .*:
+
+.* <bfscale>:
+.*: 65098000 bfscale z0.h, p0/m, z0.h, z0.h
+.*: 650983e0 bfscale z0.h, p0/m, z0.h, z31.h
+.*: 65099c00 bfscale z0.h, p7/m, z0.h, z0.h
+.*: 65099fe0 bfscale z0.h, p7/m, z0.h, z31.h
+.*: 6509801f bfscale z31.h, p0/m, z31.h, z0.h
+.*: 650983ff bfscale z31.h, p0/m, z31.h, z31.h
+.*: 65099c1f bfscale z31.h, p7/m, z31.h, z0.h
+.*: 65099fff bfscale z31.h, p7/m, z31.h, z31.h
+
+.* <bfscale_2x1>:
+.*: c120a180 bfscale {z0.h-z1.h}, {z0.h-z1.h}, z0.h
+.*: c12fa180 bfscale {z0.h-z1.h}, {z0.h-z1.h}, z15.h
+.*: c120a19e bfscale {z30.h-z31.h}, {z30.h-z31.h}, z0.h
+.*: c12fa19e bfscale {z30.h-z31.h}, {z30.h-z31.h}, z15.h
+
+.* <bfscale_4x1>:
+.*: c120a980 bfscale {z0.h-z3.h}, {z0.h-z3.h}, z0.h
+.*: c12fa980 bfscale {z0.h-z3.h}, {z0.h-z3.h}, z15.h
+.*: c120a99c bfscale {z28.h-z31.h}, {z28.h-z31.h}, z0.h
+.*: c12fa99c bfscale {z28.h-z31.h}, {z28.h-z31.h}, z15.h
+
+.* <bfscale_2x2>:
+.*: c120b180 bfscale {z0.h-z1.h}, {z0.h-z1.h}, {z0.h-z1.h}
+.*: c13eb180 bfscale {z0.h-z1.h}, {z0.h-z1.h}, {z30.h-z31.h}
+.*: c120b19e bfscale {z30.h-z31.h}, {z30.h-z31.h}, {z0.h-z1.h}
+.*: c13eb19e bfscale {z30.h-z31.h}, {z30.h-z31.h}, {z30.h-z31.h}
+
+.* <bfscale_4x4>:
+.*: c120b980 bfscale {z0.h-z3.h}, {z0.h-z3.h}, {z0.h-z3.h}
+.*: c13cb980 bfscale {z0.h-z3.h}, {z0.h-z3.h}, {z28.h-z31.h}
+.*: c120b99c bfscale {z28.h-z31.h}, {z28.h-z31.h}, {z0.h-z3.h}
+.*: c13cb99c bfscale {z28.h-z31.h}, {z28.h-z31.h}, {z28.h-z31.h}
+
+.* <bfmul_2x1>:
+.*: c120e800 bfmul {z0.h-z1.h}, {z0.h-z1.h}, z0.h
+.*: c13ee800 bfmul {z0.h-z1.h}, {z0.h-z1.h}, z15.h
+.*: c120ebde bfmul {z30.h-z31.h}, {z30.h-z31.h}, z0.h
+.*: c13eebde bfmul {z30.h-z31.h}, {z30.h-z31.h}, z15.h
+
+.* <bfmul_4x1>:
+.*: c121e800 bfmul {z0.h-z3.h}, {z0.h-z3.h}, z0.h
+.*: c13fe800 bfmul {z0.h-z3.h}, {z0.h-z3.h}, z15.h
+.*: c121eb9c bfmul {z28.h-z31.h}, {z28.h-z31.h}, z0.h
+.*: c13feb9c bfmul {z28.h-z31.h}, {z28.h-z31.h}, z15.h
+
+.* <bfmul_2x2>:
+.*: c120e400 bfmul {z0.h-z1.h}, {z0.h-z1.h}, {z0.h-z1.h}
+.*: c13ee400 bfmul {z0.h-z1.h}, {z0.h-z1.h}, {z30.h-z31.h}
+.*: c120e7de bfmul {z30.h-z31.h}, {z30.h-z31.h}, {z0.h-z1.h}
+.*: c13ee7de bfmul {z30.h-z31.h}, {z30.h-z31.h}, {z30.h-z31.h}
+
+.* <bfmul_4x4>:
+.*: c121e400 bfmul {z0.h-z3.h}, {z0.h-z3.h}, {z0.h-z3.h}
+.*: c13de400 bfmul {z0.h-z3.h}, {z0.h-z3.h}, {z28.h-z31.h}
+.*: c121e79c bfmul {z28.h-z31.h}, {z28.h-z31.h}, {z0.h-z3.h}
+.*: c13de79c bfmul {z28.h-z31.h}, {z28.h-z31.h}, {z28.h-z31.h}
diff --git a/gas/testsuite/gas/aarch64/sve-bfscale-sme2.s b/gas/testsuite/gas/aarch64/sve-bfscale-sme2.s
new file mode 100644
index 00000000000..46bc6c649cb
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve-bfscale-sme2.s
@@ -0,0 +1,57 @@
+bfscale:
+ bfscale z0.h, p0/m, z0.h, z0.h
+ bfscale z0.h, p0/m, z0.h, z31.h
+ bfscale z0.h, p7/m, z0.h, z0.h
+ bfscale z0.h, p7/m, z0.h, z31.h
+ bfscale z31.h, p0/m, z31.h, z0.h
+ bfscale z31.h, p0/m, z31.h, z31.h
+ bfscale z31.h, p7/m, z31.h, z0.h
+ bfscale z31.h, p7/m, z31.h, z31.h
+
+bfscale_2x1:
+ bfscale {z0.h-z1.h}, {z0.h-z1.h}, z0.h
+ bfscale {z0.h-z1.h}, {z0.h-z1.h}, z15.h
+ bfscale {z30.h-z31.h}, {z30.h-z31.h}, z0.h
+ bfscale {z30.h-z31.h}, {z30.h-z31.h}, z15.h
+
+bfscale_4x1:
+ bfscale {z0.h-z3.h}, {z0.h-z3.h}, z0.h
+ bfscale {z0.h-z3.h}, {z0.h-z3.h}, z15.h
+ bfscale {z28.h-z31.h}, {z28.h-z31.h}, z0.h
+ bfscale {z28.h-z31.h}, {z28.h-z31.h}, z15.h
+
+bfscale_2x2:
+ bfscale {z0.h-z1.h}, {z0.h-z1.h}, {z0.h-z1.h}
+ bfscale {z0.h-z1.h}, {z0.h-z1.h}, {z30.h-z31.h}
+ bfscale {z30.h-z31.h}, {z30.h-z31.h}, {z0.h-z1.h}
+ bfscale {z30.h-z31.h}, {z30.h-z31.h}, {z30.h-z31.h}
+
+bfscale_4x4:
+ bfscale {z0.h-z3.h}, {z0.h-z3.h}, {z0.h-z3.h}
+ bfscale {z0.h-z3.h}, {z0.h-z3.h}, {z28.h-z31.h}
+ bfscale {z28.h-z31.h}, {z28.h-z31.h}, {z0.h-z3.h}
+ bfscale {z28.h-z31.h}, {z28.h-z31.h}, {z28.h-z31.h}
+
+bfmul_2x1:
+ bfmul {z0.h-z1.h}, {z0.h-z1.h}, z0.h
+ bfmul {z0.h-z1.h}, {z0.h-z1.h}, z15.h
+ bfmul {z30.h-z31.h}, {z30.h-z31.h}, z0.h
+ bfmul {z30.h-z31.h}, {z30.h-z31.h}, z15.h
+
+bfmul_4x1:
+ bfmul {z0.h-z3.h}, {z0.h-z3.h}, z0.h
+ bfmul {z0.h-z3.h}, {z0.h-z3.h}, z15.h
+ bfmul {z28.h-z31.h}, {z28.h-z31.h}, z0.h
+ bfmul {z28.h-z31.h}, {z28.h-z31.h}, z15.h
+
+bfmul_2x2:
+ bfmul {z0.h-z1.h}, {z0.h-z1.h}, {z0.h-z1.h}
+ bfmul {z0.h-z1.h}, {z0.h-z1.h}, {z30.h-z31.h}
+ bfmul {z30.h-z31.h}, {z30.h-z31.h}, {z0.h-z1.h}
+ bfmul {z30.h-z31.h}, {z30.h-z31.h}, {z30.h-z31.h}
+
+bfmul_4x4:
+ bfmul {z0.h-z3.h}, {z0.h-z3.h}, {z0.h-z3.h}
+ bfmul {z0.h-z3.h}, {z0.h-z3.h}, {z28.h-z31.h}
+ bfmul {z28.h-z31.h}, {z28.h-z31.h}, {z0.h-z3.h}
+ bfmul {z28.h-z31.h}, {z28.h-z31.h}, {z28.h-z31.h}
diff --git a/gas/testsuite/gas/aarch64/sve-bfscale-sve2.d b/gas/testsuite/gas/aarch64/sve-bfscale-sve2.d
new file mode 100644
index 00000000000..874dda04fe7
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve-bfscale-sve2.d
@@ -0,0 +1,18 @@
+#name: FEAT_SVE_BFSCALE instruction test
+#as: -march=armv8-a+sve-bfscale+sve2
+#objdump: -dr
+
+.*: file format .*
+
+
+Disassembly of section .*:
+
+.* <bfscale>:
+.*: 65098000 bfscale z0.h, p0/m, z0.h, z0.h
+.*: 650983e0 bfscale z0.h, p0/m, z0.h, z31.h
+.*: 65099c00 bfscale z0.h, p7/m, z0.h, z0.h
+.*: 65099fe0 bfscale z0.h, p7/m, z0.h, z31.h
+.*: 6509801f bfscale z31.h, p0/m, z31.h, z0.h
+.*: 650983ff bfscale z31.h, p0/m, z31.h, z31.h
+.*: 65099c1f bfscale z31.h, p7/m, z31.h, z0.h
+.*: 65099fff bfscale z31.h, p7/m, z31.h, z31.h
diff --git a/gas/testsuite/gas/aarch64/sve-bfscale-sve2.s b/gas/testsuite/gas/aarch64/sve-bfscale-sve2.s
new file mode 100644
index 00000000000..33155242a23
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve-bfscale-sve2.s
@@ -0,0 +1,9 @@
+bfscale:
+ bfscale z0.h, p0/m, z0.h, z0.h
+ bfscale z0.h, p0/m, z0.h, z31.h
+ bfscale z0.h, p7/m, z0.h, z0.h
+ bfscale z0.h, p7/m, z0.h, z31.h
+ bfscale z31.h, p0/m, z31.h, z0.h
+ bfscale z31.h, p0/m, z31.h, z31.h
+ bfscale z31.h, p7/m, z31.h, z0.h
+ bfscale z31.h, p7/m, z31.h, z31.h
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index acae2c57dd0..3efd0b24db4 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -264,6 +264,8 @@ enum aarch64_feature_bit {
AARCH64_FEATURE_SME_F8F16,
/* Non-widening half-precision FP16 to FP16 arithmetic for SME2. */
AARCH64_FEATURE_SME_F16F16,
+ /* FEAT_SVE_BFSCALE. */
+ AARCH64_FEATURE_SVE_BFSCALE,
/* SVE Z-targeting non-widening BFloat16 instructions. */
AARCH64_FEATURE_SVE_B16B16,
/* SME non-widening BFloat16 instructions. */
@@ -291,6 +293,8 @@ enum aarch64_feature_bit {
AARCH64_FEATURE_FP8DOT2_SVE,
/* +sme-f16f16 or +sme-f8f16 */
AARCH64_FEATURE_SME_F16F16_F8F16,
+ /* +sve2 or +sme2 */
+ AARCH64_FEATURE_SVE2_SME2,
/* +sve2p1 or +sme */
AARCH64_FEATURE_SVE2p1_SME,
/* +sve2p1 or +sme2 */
@@ -894,6 +898,7 @@ enum aarch64_opnd
AARCH64_OPND_SME_Zdnx2, /* SVE vector register list from [4:1]*2. */
AARCH64_OPND_SME_Zdnx4, /* SVE vector register list from [4:2]*4. */
AARCH64_OPND_SME_Zm, /* SVE vector register list in 4-bit Zm. */
+ AARCH64_OPND_SME_Zm_17, /* SVE vector register list in [20:17]. */
AARCH64_OPND_SME_Zmx2, /* SVE vector register list from [20:17]*2. */
AARCH64_OPND_SME_Zmx4, /* SVE vector register list from [20:18]*4. */
AARCH64_OPND_SME_Znx2, /* SVE vector register list from [9:6]*2. */
diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
index 4c99b6aa431..222c4572355 100644
--- a/opcodes/aarch64-asm-2.c
+++ b/opcodes/aarch64-asm-2.c
@@ -426,7 +426,7 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
case 1230: /* movz */
value = 1230; /* --> movz. */
break;
- case 3202: /* clrbhb */
+ case 3211: /* clrbhb */
case 1311: /* autibsp */
case 1310: /* autibz */
case 1309: /* autiasp */
@@ -466,7 +466,7 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
case 1266: /* dsb */
value = 1266; /* --> dsb. */
break;
- case 3203: /* trcit */
+ case 3212: /* trcit */
case 1297: /* brb */
case 1296: /* cosp */
case 1295: /* cpp */
@@ -737,21 +737,22 @@ aarch64_insert_operand (const aarch64_operand *self,
case 245:
case 249:
case 253:
- case 261:
+ case 254:
case 262:
case 263:
- case 270:
+ case 264:
case 271:
case 272:
case 273:
- case 307:
- case 311:
+ case 274:
+ case 308:
+ case 312:
return aarch64_ins_regno (self, info, code, inst, errors);
case 6:
case 119:
case 120:
- case 317:
- case 320:
+ case 318:
+ case 321:
return aarch64_ins_none (self, info, code, inst, errors);
case 17:
return aarch64_ins_reg_extended (self, info, code, inst, errors);
@@ -766,7 +767,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case 37:
case 38:
case 39:
- case 322:
+ case 323:
return aarch64_ins_reglane (self, info, code, inst, errors);
case 40:
case 41:
@@ -774,9 +775,8 @@ aarch64_insert_operand (const aarch64_operand *self,
case 235:
case 236:
case 239:
- case 274:
case 275:
- case 290:
+ case 276:
case 291:
case 292:
case 293:
@@ -793,12 +793,13 @@ aarch64_insert_operand (const aarch64_operand *self,
case 304:
case 305:
case 306:
- case 308:
+ case 307:
case 309:
case 310:
- case 312:
+ case 311:
case 313:
case 314:
+ case 315:
return aarch64_ins_simple_index (self, info, code, inst, errors);
case 43:
return aarch64_ins_reglist (self, info, code, inst, errors);
@@ -848,14 +849,14 @@ aarch64_insert_operand (const aarch64_operand *self,
case 214:
case 215:
case 216:
- case 276:
- case 315:
+ case 277:
case 316:
- case 318:
+ case 317:
case 319:
- case 321:
- case 326:
+ case 320:
+ case 322:
case 327:
+ case 328:
return aarch64_ins_imm (self, info, code, inst, errors);
case 52:
case 53:
@@ -1008,7 +1009,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case 205:
case 206:
case 207:
- case 289:
+ case 290:
return aarch64_ins_sve_shrimm (self, info, code, inst, errors);
case 221:
case 222:
@@ -1035,53 +1036,53 @@ aarch64_insert_operand (const aarch64_operand *self,
return aarch64_ins_sve_index (self, info, code, inst, errors);
case 248:
case 250:
- case 269:
+ case 270:
return aarch64_ins_sve_reglist (self, info, code, inst, errors);
case 251:
case 252:
- case 254:
case 255:
case 256:
case 257:
case 258:
- case 268:
- return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors);
case 259:
+ case 269:
+ return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors);
case 260:
+ case 261:
return aarch64_ins_sve_strided_reglist (self, info, code, inst, errors);
- case 264:
- case 266:
- case 277:
- return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors);
case 265:
case 267:
- return aarch64_ins_sme_za_hv_tiles_range (self, info, code, inst, errors);
case 278:
+ return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors);
+ case 266:
+ case 268:
+ return aarch64_ins_sme_za_hv_tiles_range (self, info, code, inst, errors);
case 279:
case 280:
case 281:
case 282:
case 283:
case 284:
- return aarch64_ins_sme_za_array (self, info, code, inst, errors);
case 285:
- return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors);
+ return aarch64_ins_sme_za_array (self, info, code, inst, errors);
case 286:
- return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
+ return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors);
case 287:
- return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
+ return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
case 288:
+ return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
+ case 289:
return aarch64_ins_plain_shrimm (self, info, code, inst, errors);
- case 323:
case 324:
case 325:
+ case 326:
return aarch64_ins_x0_to_x30 (self, info, code, inst, errors);
- case 328:
case 329:
case 330:
case 331:
- return aarch64_ins_rcpc3_addr_opt_offset (self, info, code, inst, errors);
case 332:
+ return aarch64_ins_rcpc3_addr_opt_offset (self, info, code, inst, errors);
+ case 333:
return aarch64_ins_rcpc3_addr_offset (self, info, code, inst, errors);
default: assert (0); abort ();
}
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index a20fead95f7..c096dbc9725 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -216,7 +216,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000000x0010xxxxxx1xxxxxxxxx
movaz. */
- return 3334;
+ return 3343;
}
else
{
@@ -224,7 +224,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000100x0010xxxxxx1xxxxxxxxx
movaz. */
- return 3336;
+ return 3345;
}
}
else
@@ -235,7 +235,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000010x0010xxxxxx1xxxxxxxxx
movaz. */
- return 3335;
+ return 3344;
}
else
{
@@ -243,7 +243,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000110x0010xxxxxx1xxxxxxxxx
movaz. */
- return 3337;
+ return 3346;
}
}
}
@@ -253,7 +253,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx0x0011xxxxxx1xxxxxxxxx
movaz. */
- return 3338;
+ return 3347;
}
}
}
@@ -271,7 +271,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000x000101x00xxxxxxxxxxxxxx
luti4. */
- return 3474;
+ return 3483;
}
else
{
@@ -310,7 +310,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx01101x00xxxxxxxxxxxxxx
luti4. */
- return 3475;
+ return 3484;
}
else
{
@@ -318,7 +318,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx01101x10xxxxxxxxxxxxxx
luti4. */
- return 3331;
+ return 3340;
}
}
else
@@ -327,7 +327,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx01101xx1xxxxxxxxxxxxxx
luti4. */
- return 3330;
+ return 3339;
}
}
}
@@ -369,7 +369,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000000x011xxxxx001xxxxxxxxx
movaz. */
- return 3324;
+ return 3333;
}
else
{
@@ -377,7 +377,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000100x011xxxxx001xxxxxxxxx
movaz. */
- return 3326;
+ return 3335;
}
}
else
@@ -388,7 +388,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000010x011xxxxx001xxxxxxxxx
movaz. */
- return 3325;
+ return 3334;
}
else
{
@@ -396,7 +396,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000110x011xxxxx001xxxxxxxxx
movaz. */
- return 3327;
+ return 3336;
}
}
}
@@ -420,7 +420,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000000011000xxx00xxxxxxxxxx
zero. */
- return 3339;
+ return 3348;
}
else
{
@@ -428,7 +428,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000000011100xxx00xxxxxxxxxx
zero. */
- return 3340;
+ return 3349;
}
}
else
@@ -439,7 +439,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000000011010xxx00xxxxxxxxxx
zero. */
- return 3342;
+ return 3351;
}
else
{
@@ -447,7 +447,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000000011110xxx00xxxxxxxxxx
zero. */
- return 3345;
+ return 3354;
}
}
}
@@ -461,7 +461,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000000011001xxx00xxxxxxxxxx
zero. */
- return 3341;
+ return 3350;
}
else
{
@@ -469,7 +469,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000000011101xxx00xxxxxxxxxx
zero. */
- return 3344;
+ return 3353;
}
}
else
@@ -480,7 +480,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000000011011xxx00xxxxxxxxxx
zero. */
- return 3343;
+ return 3352;
}
else
{
@@ -488,7 +488,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000000011111xxx00xxxxxxxxxx
zero. */
- return 3346;
+ return 3355;
}
}
}
@@ -542,7 +542,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000010011x1xxxx00xxxxxxxxxx
movt. */
- return 3476;
+ return 3485;
}
}
else
@@ -563,7 +563,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx0111xxx0xx00xxxxxxxxxx
luti2. */
- return 3329;
+ return 3338;
}
else
{
@@ -571,7 +571,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx0111xxx1xx00xxxxxxxxxx
luti2. */
- return 3328;
+ return 3337;
}
}
}
@@ -602,7 +602,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx0xx11xxxxx101xxxxxxxxx
movaz. */
- return 3332;
+ return 3341;
}
}
}
@@ -639,7 +639,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000000xx11xxxxx011xxxxxxxxx
movaz. */
- return 3320;
+ return 3329;
}
else
{
@@ -647,7 +647,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000100xx11xxxxx011xxxxxxxxx
movaz. */
- return 3322;
+ return 3331;
}
}
else
@@ -658,7 +658,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000010xx11xxxxx011xxxxxxxxx
movaz. */
- return 3321;
+ return 3330;
}
else
{
@@ -666,7 +666,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000110xx11xxxxx011xxxxxxxxx
movaz. */
- return 3323;
+ return 3332;
}
}
}
@@ -698,7 +698,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx0xx11xxxxx111xxxxxxxxx
movaz. */
- return 3333;
+ return 3342;
}
}
}
@@ -1366,7 +1366,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000000101xxxxxxxxxxxxxxxx00xxx
fmopa. */
- return 3542;
+ return 3551;
}
else
{
@@ -1374,7 +1374,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000000101xxxxxxxxxxxxxxxx01xxx
fmopa. */
- return 3541;
+ return 3550;
}
}
else
@@ -1722,7 +1722,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010001xxxx1xx0xxxxx1000xxx
fmlall. */
- return 3535;
+ return 3544;
}
}
}
@@ -1754,7 +1754,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010001xxxx0xx1xxxxxx00xxxx
fmla. */
- return 3349;
+ return 3358;
}
else
{
@@ -1764,7 +1764,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010001xxxx1xx1xxxxx000xxxx
fmla. */
- return 3350;
+ return 3359;
}
else
{
@@ -1772,7 +1772,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010001xxxx1xx1xxxxx100xxxx
fdot. */
- return 3520;
+ return 3529;
}
}
}
@@ -1806,7 +1806,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010001xxxx0xx1xxxxxx10xxxx
bfmla. */
- return 3306;
+ return 3315;
}
else
{
@@ -1814,7 +1814,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010001xxxx1xx1xxxxxx10xxxx
bfmla. */
- return 3307;
+ return 3316;
}
}
}
@@ -1905,7 +1905,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010001xxxx0xx1xxxxxx01xxxx
fmls. */
- return 3355;
+ return 3364;
}
else
{
@@ -1913,7 +1913,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010001xxxx1xx1xxxxxx01xxxx
fmls. */
- return 3356;
+ return 3365;
}
}
}
@@ -1946,7 +1946,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010001xxxx0xx1xxxxxx11xxxx
bfmls. */
- return 3312;
+ return 3321;
}
else
{
@@ -1954,7 +1954,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010001xxxx1xx1xxxxxx11xxxx
bfmls. */
- return 3313;
+ return 3322;
}
}
}
@@ -2179,7 +2179,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0000001100xxxxxxxxxxxxxxxx01xxx
fmopa. */
- return 3347;
+ return 3356;
}
}
else
@@ -2223,7 +2223,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011001xxxxxxx0xxxxxx100xxx
fmlall. */
- return 3534;
+ return 3543;
}
}
}
@@ -2328,7 +2328,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011001xxxxxxx1xxxxxx10xxxx
fmlal. */
- return 3527;
+ return 3536;
}
}
}
@@ -2374,7 +2374,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0000001100xxxxxxxxxxxxxxxx11xxx
fmops. */
- return 3348;
+ return 3357;
}
}
else
@@ -2512,7 +2512,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011001xxxxxxx1xxxxxx11xxxx
fmlal. */
- return 3526;
+ return 3535;
}
}
}
@@ -2554,7 +2554,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010100xxxxxxxxxxxxxxxx0xxx
fmlall. */
- return 3533;
+ return 3542;
}
else
{
@@ -2922,7 +2922,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx000010101xxxx0xx0xxxxxx111xxx
fdot. */
- return 3513;
+ return 3522;
}
else
{
@@ -2991,7 +2991,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx000010101xxxx1xx0xxxxxx001xxx
fdot. */
- return 3514;
+ return 3523;
}
else
{
@@ -3070,7 +3070,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011100xxxxxxx0xxxxxxx0xxxx
fmlal. */
- return 3525;
+ return 3534;
}
else
{
@@ -3125,7 +3125,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011101xxxx0xx01xxxxx00xxxx
fvdotb. */
- return 3544;
+ return 3553;
}
else
{
@@ -3143,7 +3143,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011101xxxxxxx0xxxxxx10xxxx
fdot. */
- return 3519;
+ return 3528;
}
}
}
@@ -3217,7 +3217,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011101xxxxxxx1xxxxxx10xxxx
fvdot. */
- return 3543;
+ return 3552;
}
}
}
@@ -3297,7 +3297,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000001110xxxxx0xx01xxxxxx1xxxx
fvdott. */
- return 3545;
+ return 3554;
}
else
{
@@ -3418,7 +3418,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0000001xx1xxxxxxxxxxxxxxxx01xxx
bfmopa. */
- return 3318;
+ return 3327;
}
else
{
@@ -3426,7 +3426,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0000001xx1xxxxxxxxxxxxxxxx11xxx
bfmops. */
- return 3319;
+ return 3328;
}
}
}
@@ -3496,7 +3496,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx00xx000xxxx10000x
fmlall. */
- return 3539;
+ return 3548;
}
else
{
@@ -3504,7 +3504,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx10xx000xxxx10000x
fmlall. */
- return 3540;
+ return 3549;
}
}
}
@@ -3559,7 +3559,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx10xxxx0xx000xxxxx00x1x
fmlall. */
- return 3537;
+ return 3546;
}
else
{
@@ -3567,7 +3567,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx000xxxxx00x1x
fmlall. */
- return 3538;
+ return 3547;
}
}
}
@@ -3621,7 +3621,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx00xx100xxxx100xxx
fdot. */
- return 3523;
+ return 3532;
}
else
{
@@ -3629,7 +3629,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx10xx100xxxx100xxx
fdot. */
- return 3524;
+ return 3533;
}
}
}
@@ -3691,7 +3691,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001101xxxx00xx010xxxx1000xx
fmlal. */
- return 3531;
+ return 3540;
}
else
{
@@ -3699,7 +3699,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001101xxxx10xx010xxxx1000xx
fmlal. */
- return 3532;
+ return 3541;
}
}
}
@@ -3754,7 +3754,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx10xxxx0xx010xxxxx001xx
fmlal. */
- return 3529;
+ return 3538;
}
else
{
@@ -3762,7 +3762,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx010xxxxx001xx
fmlal. */
- return 3530;
+ return 3539;
}
}
}
@@ -3831,7 +3831,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx001xxxxx000xx
fmlall. */
- return 3536;
+ return 3545;
}
}
else
@@ -3914,7 +3914,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx011xxxxx00xxx
fmlal. */
- return 3528;
+ return 3537;
}
}
else
@@ -3929,7 +3929,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000010010xxxx0xx111xxxxx00xxx
fmla. */
- return 3351;
+ return 3360;
}
else
{
@@ -3937,7 +3937,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000010110xxxx0xx111xxxxx00xxx
bfmla. */
- return 3308;
+ return 3317;
}
}
else
@@ -3960,7 +3960,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011010x1x00xx111xxxxx00xxx
fadd. */
- return 3477;
+ return 3486;
}
else
{
@@ -3968,7 +3968,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011110x1x00xx111xxxxx00xxx
bfadd. */
- return 3302;
+ return 3311;
}
}
}
@@ -3990,7 +3990,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011010x1x10xx111xxxxx00xxx
fadd. */
- return 3478;
+ return 3487;
}
else
{
@@ -3998,7 +3998,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011110x1x10xx111xxxxx00xxx
bfadd. */
- return 3303;
+ return 3312;
}
}
}
@@ -4012,7 +4012,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001x011xxxx0xx111xxxxx00xxx
fmla. */
- return 3352;
+ return 3361;
}
else
{
@@ -4020,7 +4020,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001x111xxxx0xx111xxxxx00xxx
bfmla. */
- return 3309;
+ return 3318;
}
}
}
@@ -4146,7 +4146,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx00xx100xxxx110xxx
fdot. */
- return 3517;
+ return 3526;
}
else
{
@@ -4154,7 +4154,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx10xx100xxxx110xxx
fdot. */
- return 3518;
+ return 3527;
}
}
}
@@ -4449,7 +4449,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000010010xxxx0xx100xxxxx01xxx
fdot. */
- return 3521;
+ return 3530;
}
else
{
@@ -4457,7 +4457,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000010011xxxx0xx100xxxxx01xxx
fdot. */
- return 3522;
+ return 3531;
}
}
else
@@ -4468,7 +4468,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001101xxxx00xx100xxxxx01xxx
fmla. */
- return 3353;
+ return 3362;
}
else
{
@@ -4476,7 +4476,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001101xxxx10xx100xxxxx01xxx
fmla. */
- return 3354;
+ return 3363;
}
}
}
@@ -4488,7 +4488,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001x11xxxx00xx100xxxxx01xxx
bfmla. */
- return 3310;
+ return 3319;
}
else
{
@@ -4496,7 +4496,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001x11xxxx10xx100xxxxx01xxx
bfmla. */
- return 3311;
+ return 3320;
}
}
}
@@ -4762,7 +4762,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000010010xxxx0xx111xxxxx01xxx
fmls. */
- return 3357;
+ return 3366;
}
else
{
@@ -4770,7 +4770,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000010110xxxx0xx111xxxxx01xxx
bfmls. */
- return 3314;
+ return 3323;
}
}
else
@@ -4793,7 +4793,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011010x1x00xx111xxxxx01xxx
fsub. */
- return 3479;
+ return 3488;
}
else
{
@@ -4801,7 +4801,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011110x1x00xx111xxxxx01xxx
bfsub. */
- return 3304;
+ return 3313;
}
}
}
@@ -4823,7 +4823,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011010x1x10xx111xxxxx01xxx
fsub. */
- return 3480;
+ return 3489;
}
else
{
@@ -4831,7 +4831,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011110x1x10xx111xxxxx01xxx
bfsub. */
- return 3305;
+ return 3314;
}
}
}
@@ -4845,7 +4845,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001x011xxxx0xx111xxxxx01xxx
fmls. */
- return 3358;
+ return 3367;
}
else
{
@@ -4853,7 +4853,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001x111xxxx0xx111xxxxx01xxx
bfmls. */
- return 3315;
+ return 3324;
}
}
}
@@ -4919,7 +4919,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000010010xxxx0xx100xxxxx11xxx
fdot. */
- return 3515;
+ return 3524;
}
else
{
@@ -4927,7 +4927,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000010011xxxx0xx100xxxxx11xxx
fdot. */
- return 3516;
+ return 3525;
}
}
else
@@ -4938,7 +4938,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001101xxxx00xx100xxxxx11xxx
fmls. */
- return 3359;
+ return 3368;
}
else
{
@@ -4946,7 +4946,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001101xxxx10xx100xxxxx11xxx
fmls. */
- return 3360;
+ return 3369;
}
}
}
@@ -4958,7 +4958,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001x11xxxx00xx100xxxxx11xxx
bfmls. */
- return 3316;
+ return 3325;
}
else
{
@@ -4966,7 +4966,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001x11xxxx10xx100xxxxx11xxx
bfmls. */
- return 3317;
+ return 3326;
}
}
}
@@ -5501,8 +5501,8 @@ aarch64_opcode_lookup_1 (uint32_t word)
/* 33222222222211111111110000000000
10987654321098765432109876543210
x1000001xx1xxxxx101000xx1x0xxxx0
- fscale. */
- return 3451;
+ bfscale. */
+ return 2971;
}
}
else
@@ -5628,7 +5628,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001101x0000111000xxxxxxxxx0
fcvt. */
- return 3361;
+ return 3370;
}
else
{
@@ -5636,7 +5636,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001101x0000111000xxxxxxxxx1
fcvtl. */
- return 3362;
+ return 3371;
}
}
}
@@ -5694,7 +5694,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001x0100100111000xxxx0xxxxx
fcvt. */
- return 3448;
+ return 3457;
}
else
{
@@ -5702,7 +5702,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001x1100100111000xxxx0xxxxx
[...]
[diff truncated at 100000 bytes]