[binutils-gdb] RISC-V: Add Smrnmi extension imply relation.

[Nelson Chu]

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=3f8fc746d6bd837c082a41cbc37a2f8ec2325bf2

commit 3f8fc746d6bd837c082a41cbc37a2f8ec2325bf2
Author: Jiawei <jiawei@iscas.ac.cn>
Date:   Fri Jun 6 10:50:50 2025 +0800

    RISC-V: Add Smrnmi extension imply relation.
    
    This patch adds the dependency of Smrnmi extension on Zicsr extension.
    
    bfd/ChangeLog:
    
            * elfxx-riscv.c: New imply.
    
    gas/ChangeLog:
    
            * testsuite/gas/riscv/imply.d: New test check.
            * testsuite/gas/riscv/imply.s: New imply test.
    
    Signed-off-by: Jiawei <jiawei@iscas.ac.cn>

Diff:
---
 bfd/elfxx-riscv.c               | 1 +
 gas/testsuite/gas/riscv/imply.d | 1 +
 gas/testsuite/gas/riscv/imply.s | 1 +
 3 files changed, 3 insertions(+)

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 3e5d01c3e9b..0884bb7bf3d 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1293,6 +1293,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"smcsrind", "+sscsrind", check_implicit_always},
   {"smcntrpmf", "+zicsr", check_implicit_always},
   {"smctr", "+zicsr", check_implicit_always},
+  {"smrnmi", "+zicsr", check_implicit_always},
   {"smstateen", "+ssstateen", check_implicit_always},
   {"smepmp", "+zicsr", check_implicit_always},
   {"smdbltrp", "+zicsr", check_implicit_always},
diff --git a/gas/testsuite/gas/riscv/imply.d b/gas/testsuite/gas/riscv/imply.d
index 988524fdffc..b68da92b07c 100644
--- a/gas/testsuite/gas/riscv/imply.d
+++ b/gas/testsuite/gas/riscv/imply.d
@@ -88,6 +88,7 @@ SYMBOL TABLE:
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zicsr2p0_smcdeleg1p0_ssccfg1p0_sscsrind1p0
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zicsr2p0_smcsrind1p0_sscsrind1p0
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zicsr2p0_smcntrpmf1p0
+[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zicsr2p0_smrnmi1p0
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zicsr2p0_smstateen1p0_ssstateen1p0
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zicsr2p0_smepmp1p0
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zicsr2p0_smdbltrp1p0
diff --git a/gas/testsuite/gas/riscv/imply.s b/gas/testsuite/gas/riscv/imply.s
index de1f0dfc24d..35c68d3efbb 100644
--- a/gas/testsuite/gas/riscv/imply.s
+++ b/gas/testsuite/gas/riscv/imply.s
@@ -102,6 +102,7 @@ imply smaia
 imply smcdeleg
 imply smcsrind
 imply smcntrpmf
+imply smrnmi
 imply smstateen
 imply smepmp
 imply smdbltrp