[binutils-gdb] aarch64: Support for FEAT_SVE_AES2
Ezra Sitorus
ezrasitorus@sourceware.org
Fri Jul 11 11:55:07 GMT 2025
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=87dcc3ddd648bf5b9de965d9eb572e7f91beeeef
commit 87dcc3ddd648bf5b9de965d9eb572e7f91beeeef
Author: Ezra Sitorus <ezra.sitorus@arm.com>
Date: Thu May 15 12:33:39 2025 +0100
aarch64: Support for FEAT_SVE_AES2
FEAT_SVE_AES2 implements the SVE multi-vector Advanced Encryption
Standard and 128-bit destination element polynomial multiply long
instructions, when the PE is not in Streaming SVE mode.
Diff:
---
gas/config/tc-aarch64.c | 8 +-
gas/doc/c-aarch64.texi | 6 +
gas/testsuite/gas/aarch64/illegal-sve-aes2.d | 4 +
gas/testsuite/gas/aarch64/illegal-sve-aes2.l | 103 +
gas/testsuite/gas/aarch64/illegal-sve-aes2.s | 59 +
gas/testsuite/gas/aarch64/illegal-sve2.l | 12 +-
gas/testsuite/gas/aarch64/sve-aes2-sve2-ssve-aes.d | 109 +
gas/testsuite/gas/aarch64/sve-aes2.s | 99 +
include/opcode/aarch64.h | 9 +
opcodes/aarch64-asm-2.c | 99 +-
opcodes/aarch64-dis-2.c | 3001 ++++++++++----------
opcodes/aarch64-opc-2.c | 1 +
opcodes/aarch64-opc.c | 2 +
opcodes/aarch64-tbl.h | 25 +-
14 files changed, 2035 insertions(+), 1502 deletions(-)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index daf34fd223f..29d9cdb3fdc 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -6919,6 +6919,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
case AARCH64_OPND_SME_Zn_INDEX1_16:
case AARCH64_OPND_SME_Zn_INDEX2_15:
case AARCH64_OPND_SME_Zn_INDEX2_16:
+ case AARCH64_OPND_SME_Zn_INDEX2_19:
case AARCH64_OPND_SME_Zn_INDEX3_14:
case AARCH64_OPND_SME_Zn_INDEX3_15:
case AARCH64_OPND_SME_Zn_INDEX4_14:
@@ -10756,7 +10757,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
{"sve2-sm4", AARCH64_FEATURE (SVE2_SM4),
AARCH64_FEATURES (2, SVE2, SM4)},
{"sve2-aes", AARCH64_FEATURE (SVE2_AES),
- AARCH64_FEATURES (2, SVE2, AES)},
+ AARCH64_FEATURES (2, SVE2, SVE_AES)},
{"sve2-sha3", AARCH64_FEATURE (SVE2_SHA3),
AARCH64_FEATURES (2, SVE2, SHA3)},
{"sve2-bitperm", AARCH64_FEATURE (SVE2_BITPERM),
@@ -10794,6 +10795,9 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
{"sve-f16f32mm", AARCH64_FEATURE (SVE_F16F32MM), AARCH64_FEATURE (SVE)},
{"f8f32mm", AARCH64_FEATURE (F8F32MM), AARCH64_FEATURES (2, SIMD, FP8)},
{"f8f16mm", AARCH64_FEATURE (F8F16MM), AARCH64_FEATURES (2, SIMD, FP8)},
+ {"sve-aes", AARCH64_FEATURE (SVE_AES), AARCH64_FEATURE (AES)},
+ {"sve-aes2", AARCH64_FEATURE (SVE_AES2), AARCH64_NO_FEATURES},
+ {"ssve-aes", AARCH64_FEATURE (SSVE_AES), AARCH64_FEATURES (2, SME2, SVE_AES)},
{"rcpc3", AARCH64_FEATURE (RCPC3), AARCH64_FEATURE (RCPC2)},
{"cpa", AARCH64_FEATURE (CPA), AARCH64_NO_FEATURES},
{"faminmax", AARCH64_FEATURE (FAMINMAX), AARCH64_FEATURE (SIMD)},
@@ -10832,6 +10836,8 @@ struct aarch64_virtual_dependency_table
};
static const struct aarch64_virtual_dependency_table aarch64_dependencies[] = {
+ {AARCH64_FEATURE (SVE2), AARCH64_FEATURE (SVE2_SSVE_AES)},
+ {AARCH64_FEATURE (SSVE_AES), AARCH64_FEATURE (SVE2_SSVE_AES)},
{AARCH64_FEATURES (2, FP8FMA, SVE2), AARCH64_FEATURE (FP8FMA_SVE)},
{AARCH64_FEATURE (SSVE_FP8FMA), AARCH64_FEATURE (FP8FMA_SVE)},
{AARCH64_FEATURES (2, FP8DOT4, SVE2), AARCH64_FEATURE (FP8DOT4_SVE)},
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 06121dd182d..d300ab2beef 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -307,12 +307,18 @@ automatically cause those extensions to be disabled.
@tab Enable Speculative Store Bypassing Safe state read and write.
@item @code{ssve-fp8dot2} @tab @code{sme2}, @code{fp8}
@tab Enable the Streaming SVE FP8 2-way dot product instructions.
+@item @code{ssve-aes} @tab @code{sme2}, @code{sve-aes}
+ @tab Enable SVE AES instructions in streaming mode.
@item @code{ssve-fp8dot4} @tab @code{sme2}, @code{fp8}
@tab Enable the Streaming SVE FP8 4-way dot product instructions.
@item @code{ssve-fp8fma} @tab @code{sme2}, @code{fp8}
@tab Enable the Streaming SVE FP8 FMA instructions.
@item @code{sve} @tab @code{fcma}
@tab Enable the Scalable Vector Extension.
+@item @code{sve-aes} @tab @code{aes}
+ @tab Enable the SVE PMULL128 instructions.
+@item @code{sve-aes2} @tab
+@tab Enable the SVE-AES2 extension.
@item @code{sve-b16b16} @tab
@tab Enable the SVE B16B16 extension. These instructions also require either @code{+sve2} or @code{+sme2}.
@item @code{sve-bfscale} @tab
diff --git a/gas/testsuite/gas/aarch64/illegal-sve-aes2.d b/gas/testsuite/gas/aarch64/illegal-sve-aes2.d
new file mode 100644
index 00000000000..23c391dfae1
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-sve-aes2.d
@@ -0,0 +1,4 @@
+#name: Illegal SVE-AES2
+#as: -march=armv8-a+sve-aes2
+#source: illegal-sve-aes2.s
+#error_output: illegal-sve-aes2.l
diff --git a/gas/testsuite/gas/aarch64/illegal-sve-aes2.l b/gas/testsuite/gas/aarch64/illegal-sve-aes2.l
new file mode 100644
index 00000000000..3f0c1ed59d9
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-sve-aes2.l
@@ -0,0 +1,103 @@
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `aesdimc { ?z0\.b-z1\.b ?},{ ?z0\.b-z1\.b ?},z0\.q\[4\]'
+[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `aesdimc { ?z0\.b-z1\.b ?},{ ?z1\.b-z2\.b ?},z0\.q\[0\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `aesdimc { ?z0\.q-z1\.q ?},{ ?z0\.b-z1\.b ?},z0\.q\[0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: aesdimc { ?z0\.b-z1\.b ?}, { ?z0\.b-z1\.b ?}, z0\.q\[0\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `aesdimc { ?z0\.q-z1\.q ?},{ ?z0\.q-z1\.q ?},z0\.q\[0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: aesdimc { ?z0\.b-z1\.b ?}, { ?z0\.b-z1\.b ?}, z0\.q\[0\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `aesdimc { ?z0\.b-z1\.b ?},{ ?z0\.b-z1\.b ?},z0\.b\[0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: aesdimc { ?z0\.b-z1\.b ?}, { ?z0\.b-z1\.b ?}, z0\.q\[0\]
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `aesdimc { ?z0\.b-z3\.b ?},{ ?z0\.b-z3\.b ?},z0\.q\[4\]'
+[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 2 -- `aesdimc { ?z0\.b-z3\.b ?},{ ?z3\.b-z2\.b ?},z0\.q\[0\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `aesdimc { ?z0\.q-z3\.q ?},{ ?z0\.b-z3\.b ?},z0\.q\[0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: aesdimc { ?z0\.b-z3\.b ?}, { ?z0\.b-z3\.b ?}, z0\.q\[0\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `aesdimc { ?z0\.q-z3\.q ?},{ ?z0\.q-z3\.q ?},z0\.q\[0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: aesdimc { ?z0\.b-z3\.b ?}, { ?z0\.b-z3\.b ?}, z0\.q\[0\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `aesdimc { ?z0\.b-z3\.b ?},{ ?z0\.b-z3\.b ?},z0\.b\[0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: aesdimc { ?z0\.b-z3\.b ?}, { ?z0\.b-z3\.b ?}, z0\.q\[0\]
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `aesd { ?z0\.b-z1\.b ?},{ ?z0\.b-z1\.b ?},z0\.q\[4\]'
+[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `aesd { ?z0\.b-z1\.b ?},{ ?z1\.b-z2\.b ?},z0\.q\[0\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `aesd { ?z0\.q-z1\.q ?},{ ?z0\.b-z1\.b ?},z0\.q\[0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: aesd { ?z0\.b-z1\.b ?}, { ?z0\.b-z1\.b ?}, z0\.q\[0\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `aesd { ?z0\.q-z1\.q ?},{ ?z0\.q-z1\.q ?},z0\.q\[0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: aesd { ?z0\.b-z1\.b ?}, { ?z0\.b-z1\.b ?}, z0\.q\[0\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `aesd { ?z0\.b-z1\.b ?},{ ?z0\.b-z1\.b ?},z0\.b\[0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: aesd { ?z0\.b-z1\.b ?}, { ?z0\.b-z1\.b ?}, z0\.q\[0\]
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `aesd { ?z0\.b-z3\.b ?},{ ?z0\.b-z3\.b ?},z0\.q\[4\]'
+[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 2 -- `aesd { ?z0\.b-z3\.b ?},{ ?z3\.b-z2\.b ?},z0\.q\[0\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `aesd { ?z0\.q-z3\.q ?},{ ?z0\.b-z3\.b ?},z0\.q\[0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: aesd { ?z0\.b-z3\.b ?}, { ?z0\.b-z3\.b ?}, z0\.q\[0\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `aesd { ?z0\.q-z3\.q ?},{ ?z0\.q-z3\.q ?},z0\.q\[0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: aesd { ?z0\.b-z3\.b ?}, { ?z0\.b-z3\.b ?}, z0\.q\[0\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `aesd { ?z0\.b-z3\.b ?},{ ?z0\.b-z3\.b ?},z0\.b\[0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: aesd { ?z0\.b-z3\.b ?}, { ?z0\.b-z3\.b ?}, z0\.q\[0\]
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `aesemc { ?z0\.b-z1\.b ?},{ ?z0\.b-z1\.b ?},z0\.q\[4\]'
+[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `aesemc { ?z0\.b-z1\.b ?},{ ?z1\.b-z2\.b ?},z0\.q\[0\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `aesemc { ?z0\.q-z1\.q ?},{ ?z0\.b-z1\.b ?},z0\.q\[0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: aesemc { ?z0\.b-z1\.b ?}, { ?z0\.b-z1\.b ?}, z0\.q\[0\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `aesemc { ?z0\.q-z1\.q ?},{ ?z0\.q-z1\.q ?},z0\.q\[0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: aesemc { ?z0\.b-z1\.b ?}, { ?z0\.b-z1\.b ?}, z0\.q\[0\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `aesemc { ?z0\.b-z1\.b ?},{ ?z0\.b-z1\.b ?},z0\.b\[0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: aesemc { ?z0\.b-z1\.b ?}, { ?z0\.b-z1\.b ?}, z0\.q\[0\]
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `aesemc { ?z0\.b-z3\.b ?},{ ?z0\.b-z3\.b ?},z0\.q\[4\]'
+[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 2 -- `aesemc { ?z0\.b-z3\.b ?},{ ?z3\.b-z2\.b ?},z0\.q\[0\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `aesemc { ?z0\.q-z3\.q ?},{ ?z0\.b-z3\.b ?},z0\.q\[0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: aesemc { ?z0\.b-z3\.b ?}, { ?z0\.b-z3\.b ?}, z0\.q\[0\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `aesemc { ?z0\.q-z3\.q ?},{ ?z0\.q-z3\.q ?},z0\.q\[0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: aesemc { ?z0\.b-z3\.b ?}, { ?z0\.b-z3\.b ?}, z0\.q\[0\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `aesemc { ?z0\.b-z3\.b ?},{ ?z0\.b-z3\.b ?},z0\.b\[0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: aesemc { ?z0\.b-z3\.b ?}, { ?z0\.b-z3\.b ?}, z0\.q\[0\]
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `aese { ?z0\.b-z1\.b ?},{ ?z0\.b-z1\.b ?},z0\.q\[4\]'
+[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `aese { ?z0\.b-z1\.b ?},{ ?z1\.b-z2\.b ?},z0\.q\[0\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `aese { ?z0\.q-z1\.q ?},{ ?z0\.b-z1\.b ?},z0\.q\[0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: aese { ?z0\.b-z1\.b ?}, { ?z0\.b-z1\.b ?}, z0\.q\[0\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `aese { ?z0\.q-z1\.q ?},{ ?z0\.q-z1\.q ?},z0\.q\[0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: aese { ?z0\.b-z1\.b ?}, { ?z0\.b-z1\.b ?}, z0\.q\[0\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `aese { ?z0\.b-z1\.b ?},{ ?z0\.b-z1\.b ?},z0\.b\[0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: aese { ?z0\.b-z1\.b ?}, { ?z0\.b-z1\.b ?}, z0\.q\[0\]
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `aese { ?z0\.b-z3\.b ?},{ ?z0\.b-z3\.b ?},z0\.q\[4\]'
+[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 2 -- `aese { ?z0\.b-z3\.b ?},{ ?z3\.b-z2\.b ?},z0\.q\[0\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `aese { ?z0\.q-z3\.q ?},{ ?z0\.b-z3\.b ?},z0\.q\[0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: aese { ?z0\.b-z3\.b ?}, { ?z0\.b-z3\.b ?}, z0\.q\[0\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `aese { ?z0\.q-z3\.q ?},{ ?z0\.q-z3\.q ?},z0\.q\[0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: aese { ?z0\.b-z3\.b ?}, { ?z0\.b-z3\.b ?}, z0\.q\[0\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `aese { ?z0\.b-z3\.b ?},{ ?z0\.b-z3\.b ?},z0\.b\[0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: aese { ?z0\.b-z3\.b ?}, { ?z0\.b-z3\.b ?}, z0\.q\[0\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `pmlal { ?z0\.b-z1\.b},z0\.d,z0\.d'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: pmlal { ?z0\.q-z1\.q}, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 1 -- `pmlal { ?z0\.q-z3\.q},z0\.d,z0\.d'
+[^ :]+:[0-9]+: Error: missing braces at operand 1 -- `pmlal z0\.q,z0\.q,z0\.d'
+[^ :]+:[0-9]+: Error: missing braces at operand 1 -- `pmlal z0\.q,{ ?z0\.q-z1\.q},z0\.d'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `pmlal { ?z0\.b-z1\.b},z0\.d,{ ?z1\.d-z2\.d}'
+[^ :]+:[0-9]+: Error: operand mismatch -- `pmull { ?z0\.b-z1\.b},z0\.d,z0\.d'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: pmull { ?z0\.q-z1\.q}, z0\.d, z0\.d
+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 1 -- `pmull { ?z0\.q-z3\.q},z0\.d,z0\.d'
+[^ :]+:[0-9]+: Error: missing braces at operand 1 -- `pmull z0\.q,z0\.q,z0\.d'
+[^ :]+:[0-9]+: Error: missing braces at operand 1 -- `pmull z0\.q,{ ?z0\.q-z1\.q},z0\.d'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `pmull { ?z0\.b-z1\.b},z0\.d,{ ?z1\.d-z2\.d}'
diff --git a/gas/testsuite/gas/aarch64/illegal-sve-aes2.s b/gas/testsuite/gas/aarch64/illegal-sve-aes2.s
new file mode 100644
index 00000000000..4eb7810862e
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-sve-aes2.s
@@ -0,0 +1,59 @@
+aesdimc {z0.b-z1.b}, {z0.b-z1.b}, z0.q[4]
+aesdimc {z0.b-z1.b}, {z1.b-z2.b}, z0.q[0]
+aesdimc {z0.q-z1.q}, {z0.b-z1.b}, z0.q[0]
+aesdimc {z0.q-z1.q}, {z0.q-z1.q}, z0.q[0]
+aesdimc {z0.b-z1.b}, {z0.b-z1.b}, z0.b[0]
+
+aesdimc {z0.b-z3.b}, {z0.b-z3.b}, z0.q[4]
+aesdimc {z0.b-z3.b}, {z3.b-z2.b}, z0.q[0]
+aesdimc {z0.q-z3.q}, {z0.b-z3.b}, z0.q[0]
+aesdimc {z0.q-z3.q}, {z0.q-z3.q}, z0.q[0]
+aesdimc {z0.b-z3.b}, {z0.b-z3.b}, z0.b[0]
+
+aesd {z0.b-z1.b}, {z0.b-z1.b}, z0.q[4]
+aesd {z0.b-z1.b}, {z1.b-z2.b}, z0.q[0]
+aesd {z0.q-z1.q}, {z0.b-z1.b}, z0.q[0]
+aesd {z0.q-z1.q}, {z0.q-z1.q}, z0.q[0]
+aesd {z0.b-z1.b}, {z0.b-z1.b}, z0.b[0]
+
+aesd {z0.b-z3.b}, {z0.b-z3.b}, z0.q[4]
+aesd {z0.b-z3.b}, {z3.b-z2.b}, z0.q[0]
+aesd {z0.q-z3.q}, {z0.b-z3.b}, z0.q[0]
+aesd {z0.q-z3.q}, {z0.q-z3.q}, z0.q[0]
+aesd {z0.b-z3.b}, {z0.b-z3.b}, z0.b[0]
+
+aesemc {z0.b-z1.b}, {z0.b-z1.b}, z0.q[4]
+aesemc {z0.b-z1.b}, {z1.b-z2.b}, z0.q[0]
+aesemc {z0.q-z1.q}, {z0.b-z1.b}, z0.q[0]
+aesemc {z0.q-z1.q}, {z0.q-z1.q}, z0.q[0]
+aesemc {z0.b-z1.b}, {z0.b-z1.b}, z0.b[0]
+
+aesemc {z0.b-z3.b}, {z0.b-z3.b}, z0.q[4]
+aesemc {z0.b-z3.b}, {z3.b-z2.b}, z0.q[0]
+aesemc {z0.q-z3.q}, {z0.b-z3.b}, z0.q[0]
+aesemc {z0.q-z3.q}, {z0.q-z3.q}, z0.q[0]
+aesemc {z0.b-z3.b}, {z0.b-z3.b}, z0.b[0]
+
+aese {z0.b-z1.b}, {z0.b-z1.b}, z0.q[4]
+aese {z0.b-z1.b}, {z1.b-z2.b}, z0.q[0]
+aese {z0.q-z1.q}, {z0.b-z1.b}, z0.q[0]
+aese {z0.q-z1.q}, {z0.q-z1.q}, z0.q[0]
+aese {z0.b-z1.b}, {z0.b-z1.b}, z0.b[0]
+
+aese {z0.b-z3.b}, {z0.b-z3.b}, z0.q[4]
+aese {z0.b-z3.b}, {z3.b-z2.b}, z0.q[0]
+aese {z0.q-z3.q}, {z0.b-z3.b}, z0.q[0]
+aese {z0.q-z3.q}, {z0.q-z3.q}, z0.q[0]
+aese {z0.b-z3.b}, {z0.b-z3.b}, z0.b[0]
+
+pmlal {z0.b-z1.b}, z0.d, z0.d
+pmlal {z0.q-z3.q}, z0.d, z0.d
+pmlal z0.q, z0.q, z0.d
+pmlal z0.q, {z0.q-z1.q}, z0.d
+pmlal {z0.b-z1.b}, z0.d, {z1.d-z2.d}
+
+pmull {z0.b-z1.b}, z0.d, z0.d
+pmull {z0.q-z3.q}, z0.d, z0.d
+pmull z0.q, z0.q, z0.d
+pmull z0.q, {z0.q-z1.q}, z0.d
+pmull {z0.b-z1.b}, z0.d, {z1.d-z2.d}
diff --git a/gas/testsuite/gas/aarch64/illegal-sve2.l b/gas/testsuite/gas/aarch64/illegal-sve2.l
index ca13c4423c0..62f063ab1fe 100644
--- a/gas/testsuite/gas/aarch64/illegal-sve2.l
+++ b/gas/testsuite/gas/aarch64/illegal-sve2.l
@@ -50,27 +50,27 @@
[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `addp z32\.s,p0/m,z32\.s,z0\.s'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `addp z0\.s,p0/m,z0\.s,z32\.s'
[^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `addp z0\.s,p8/m,z0\.s,z0\.s'
-[^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `aesd z0\.b,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Warning: SVE instruction expected after `movprfx' -- `aesd z0\.b,z0\.b,z0\.b'
[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `aesd z0\.b,z1\.b,z0\.b'
[^ :]+:[0-9]+: Error: operand mismatch -- `aesd z0\.b,z0\.s,z0\.b'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: aesd z0\.b, z0\.b, z0\.b
-[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `aesd z32\.b,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `aesd z32\.b,z0\.b,z0\.b'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `aesd z0\.b,z0\.b,z32\.b'
-[^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `aese z0\.b,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Warning: SVE instruction expected after `movprfx' -- `aese z0\.b,z0\.b,z0\.b'
[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `aese z0\.b,z1\.b,z0\.b'
[^ :]+:[0-9]+: Error: operand mismatch -- `aese z0\.b,z0\.s,z0\.b'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: aese z0\.b, z0\.b, z0\.b
-[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `aese z32\.b,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `aese z32\.b,z0\.b,z0\.b'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `aese z0\.b,z0\.b,z32\.b'
-[^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `aesimc z0\.b,z0\.b'
+[^ :]+:[0-9]+: Warning: SVE instruction expected after `movprfx' -- `aesimc z0\.b,z0\.b'
[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `aesimc z0\.b,z1\.b'
[^ :]+:[0-9]+: Error: operand mismatch -- `aesimc z0\.b,z0\.s'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: aesimc z0\.b, z0\.b
[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `aesimc z32\.b,z0\.b'
-[^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `aesmc z0\.b,z0\.b'
+[^ :]+:[0-9]+: Warning: SVE instruction expected after `movprfx' -- `aesmc z0\.b,z0\.b'
[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `aesmc z0\.b,z1\.b'
[^ :]+:[0-9]+: Error: operand mismatch -- `aesmc z0\.b,z0\.s'
[^ :]+:[0-9]+: Info: did you mean this\?
diff --git a/gas/testsuite/gas/aarch64/sve-aes2-sve2-ssve-aes.d b/gas/testsuite/gas/aarch64/sve-aes2-sve2-ssve-aes.d
new file mode 100644
index 00000000000..33ca9c41e06
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve-aes2-sve2-ssve-aes.d
@@ -0,0 +1,109 @@
+#name: Test of SVE-AES2 instructions.
+#as: -march=armv9-a+sve-aes2+ssve-aes
+#as: -march=armv9-a+sve-aes2+sve2
+#source: sve-aes2.s
+#objdump: -dr
+
+[^:]+: file format .*
+
+.*:
+
+.*:
+.*: 4523ec00 aesdimc { ?z0\.b-z1\.b ?}, { ?z0\.b-z1\.b ?}, z0\.q\[0\]
+.*: 453bec00 aesdimc { ?z0\.b-z1\.b ?}, { ?z0\.b-z1\.b ?}, z0\.q\[3\]
+.*: 4523efe0 aesdimc { ?z0\.b-z1\.b ?}, { ?z0\.b-z1\.b ?}, z31\.q\[0\]
+.*: 453befe0 aesdimc { ?z0\.b-z1\.b ?}, { ?z0\.b-z1\.b ?}, z31\.q\[3\]
+.*: 4523ec1e aesdimc { ?z30\.b-z31\.b ?}, { ?z30\.b-z31\.b ?}, z0\.q\[0\]
+.*: 453bec1e aesdimc { ?z30\.b-z31\.b ?}, { ?z30\.b-z31\.b ?}, z0\.q\[3\]
+.*: 4523effe aesdimc { ?z30\.b-z31\.b ?}, { ?z30\.b-z31\.b ?}, z31\.q\[0\]
+.*: 453beffe aesdimc { ?z30\.b-z31\.b ?}, { ?z30\.b-z31\.b ?}, z31\.q\[3\]
+
+.*:
+.*: 4527ec00 aesdimc { ?z0\.b-z3\.b ?}, { ?z0\.b-z3\.b ?}, z0\.q\[0\]
+.*: 453fec00 aesdimc { ?z0\.b-z3\.b ?}, { ?z0\.b-z3\.b ?}, z0\.q\[3\]
+.*: 4527efe0 aesdimc { ?z0\.b-z3\.b ?}, { ?z0\.b-z3\.b ?}, z31\.q\[0\]
+.*: 453fefe0 aesdimc { ?z0\.b-z3\.b ?}, { ?z0\.b-z3\.b ?}, z31\.q\[3\]
+.*: 4527ec1c aesdimc { ?z28\.b-z31\.b ?}, { ?z28\.b-z31\.b ?}, z0\.q\[0\]
+.*: 453fec1c aesdimc { ?z28\.b-z31\.b ?}, { ?z28\.b-z31\.b ?}, z0\.q\[3\]
+.*: 4527effc aesdimc { ?z28\.b-z31\.b ?}, { ?z28\.b-z31\.b ?}, z31\.q\[0\]
+.*: 453feffc aesdimc { ?z28\.b-z31\.b ?}, { ?z28\.b-z31\.b ?}, z31\.q\[3\]
+
+.*:
+.*: 4522ec00 aesd { ?z0\.b-z1\.b ?}, { ?z0\.b-z1\.b ?}, z0\.q\[0\]
+.*: 453aec00 aesd { ?z0\.b-z1\.b ?}, { ?z0\.b-z1\.b ?}, z0\.q\[3\]
+.*: 4522efe0 aesd { ?z0\.b-z1\.b ?}, { ?z0\.b-z1\.b ?}, z31\.q\[0\]
+.*: 453aefe0 aesd { ?z0\.b-z1\.b ?}, { ?z0\.b-z1\.b ?}, z31\.q\[3\]
+.*: 4522ec1e aesd { ?z30\.b-z31\.b ?}, { ?z30\.b-z31\.b ?}, z0\.q\[0\]
+.*: 453aec1e aesd { ?z30\.b-z31\.b ?}, { ?z30\.b-z31\.b ?}, z0\.q\[3\]
+.*: 4522effe aesd { ?z30\.b-z31\.b ?}, { ?z30\.b-z31\.b ?}, z31\.q\[0\]
+.*: 453aeffe aesd { ?z30\.b-z31\.b ?}, { ?z30\.b-z31\.b ?}, z31\.q\[3\]
+
+.*:
+.*: 4526ec00 aesd { ?z0\.b-z3\.b ?}, { ?z0\.b-z3\.b ?}, z0\.q\[0\]
+.*: 453eec00 aesd { ?z0\.b-z3\.b ?}, { ?z0\.b-z3\.b ?}, z0\.q\[3\]
+.*: 4526efe0 aesd { ?z0\.b-z3\.b ?}, { ?z0\.b-z3\.b ?}, z31\.q\[0\]
+.*: 453eefe0 aesd { ?z0\.b-z3\.b ?}, { ?z0\.b-z3\.b ?}, z31\.q\[3\]
+.*: 4526ec1c aesd { ?z28\.b-z31\.b ?}, { ?z28\.b-z31\.b ?}, z0\.q\[0\]
+.*: 453eec1c aesd { ?z28\.b-z31\.b ?}, { ?z28\.b-z31\.b ?}, z0\.q\[3\]
+.*: 4526effc aesd { ?z28\.b-z31\.b ?}, { ?z28\.b-z31\.b ?}, z31\.q\[0\]
+.*: 453eeffc aesd { ?z28\.b-z31\.b ?}, { ?z28\.b-z31\.b ?}, z31\.q\[3\]
+
+.*:
+.*: 4523e800 aesemc { ?z0\.b-z1\.b ?}, { ?z0\.b-z1\.b ?}, z0\.q\[0\]
+.*: 453be800 aesemc { ?z0\.b-z1\.b ?}, { ?z0\.b-z1\.b ?}, z0\.q\[3\]
+.*: 4523ebe0 aesemc { ?z0\.b-z1\.b ?}, { ?z0\.b-z1\.b ?}, z31\.q\[0\]
+.*: 453bebe0 aesemc { ?z0\.b-z1\.b ?}, { ?z0\.b-z1\.b ?}, z31\.q\[3\]
+.*: 4523e81e aesemc { ?z30\.b-z31\.b ?}, { ?z30\.b-z31\.b ?}, z0\.q\[0\]
+.*: 453be81e aesemc { ?z30\.b-z31\.b ?}, { ?z30\.b-z31\.b ?}, z0\.q\[3\]
+.*: 4523ebfe aesemc { ?z30\.b-z31\.b ?}, { ?z30\.b-z31\.b ?}, z31\.q\[0\]
+.*: 453bebfe aesemc { ?z30\.b-z31\.b ?}, { ?z30\.b-z31\.b ?}, z31\.q\[3\]
+
+.*:
+.*: 4527e800 aesemc { ?z0\.b-z3\.b ?}, { ?z0\.b-z3\.b ?}, z0\.q\[0\]
+.*: 453fe800 aesemc { ?z0\.b-z3\.b ?}, { ?z0\.b-z3\.b ?}, z0\.q\[3\]
+.*: 4527ebe0 aesemc { ?z0\.b-z3\.b ?}, { ?z0\.b-z3\.b ?}, z31\.q\[0\]
+.*: 453febe0 aesemc { ?z0\.b-z3\.b ?}, { ?z0\.b-z3\.b ?}, z31\.q\[3\]
+.*: 4527e81c aesemc { ?z28\.b-z31\.b ?}, { ?z28\.b-z31\.b ?}, z0\.q\[0\]
+.*: 453fe81c aesemc { ?z28\.b-z31\.b ?}, { ?z28\.b-z31\.b ?}, z0\.q\[3\]
+.*: 4527ebfc aesemc { ?z28\.b-z31\.b ?}, { ?z28\.b-z31\.b ?}, z31\.q\[0\]
+.*: 453febfc aesemc { ?z28\.b-z31\.b ?}, { ?z28\.b-z31\.b ?}, z31\.q\[3\]
+
+.*:
+.*: 4522e800 aese { ?z0\.b-z1\.b ?}, { ?z0\.b-z1\.b ?}, z0\.q\[0\]
+.*: 453ae800 aese { ?z0\.b-z1\.b ?}, { ?z0\.b-z1\.b ?}, z0\.q\[3\]
+.*: 4522ebe0 aese { ?z0\.b-z1\.b ?}, { ?z0\.b-z1\.b ?}, z31\.q\[0\]
+.*: 453aebe0 aese { ?z0\.b-z1\.b ?}, { ?z0\.b-z1\.b ?}, z31\.q\[3\]
+.*: 4522e81e aese { ?z30\.b-z31\.b ?}, { ?z30\.b-z31\.b ?}, z0\.q\[0\]
+.*: 453ae81e aese { ?z30\.b-z31\.b ?}, { ?z30\.b-z31\.b ?}, z0\.q\[3\]
+.*: 4522ebfe aese { ?z30\.b-z31\.b ?}, { ?z30\.b-z31\.b ?}, z31\.q\[0\]
+.*: 453aebfe aese { ?z30\.b-z31\.b ?}, { ?z30\.b-z31\.b ?}, z31\.q\[3\]
+
+.*:
+.*: 4526e800 aese { ?z0\.b-z3\.b ?}, { ?z0\.b-z3\.b ?}, z0\.q\[0\]
+.*: 453ee800 aese { ?z0\.b-z3\.b ?}, { ?z0\.b-z3\.b ?}, z0\.q\[3\]
+.*: 4526ebe0 aese { ?z0\.b-z3\.b ?}, { ?z0\.b-z3\.b ?}, z31\.q\[0\]
+.*: 453eebe0 aese { ?z0\.b-z3\.b ?}, { ?z0\.b-z3\.b ?}, z31\.q\[3\]
+.*: 4526e81c aese { ?z28\.b-z31\.b ?}, { ?z28\.b-z31\.b ?}, z0\.q\[0\]
+.*: 453ee81c aese { ?z28\.b-z31\.b ?}, { ?z28\.b-z31\.b ?}, z0\.q\[3\]
+.*: 4526ebfc aese { ?z28\.b-z31\.b ?}, { ?z28\.b-z31\.b ?}, z31\.q\[0\]
+.*: 453eebfc aese { ?z28\.b-z31\.b ?}, { ?z28\.b-z31\.b ?}, z31\.q\[3\]
+
+.*:
+.*: 4520fc00 pmlal { ?z0\.q-z1\.q ?}, z0\.d, z0\.d
+.*: 453ffc00 pmlal { ?z0\.q-z1\.q ?}, z0\.d, z31\.d
+.*: 4520ffe0 pmlal { ?z0\.q-z1\.q ?}, z31\.d, z0\.d
+.*: 453fffe0 pmlal { ?z0\.q-z1\.q ?}, z31\.d, z31\.d
+.*: 4520fc1e pmlal { ?z30\.q-z31\.q ?}, z0\.d, z0\.d
+.*: 453ffc1e pmlal { ?z30\.q-z31\.q ?}, z0\.d, z31\.d
+.*: 4520fffe pmlal { ?z30\.q-z31\.q ?}, z31\.d, z0\.d
+.*: 453ffffe pmlal { ?z30\.q-z31\.q ?}, z31\.d, z31\.d
+
+.*:
+.*: 4520f800 pmull { ?z0\.q-z1\.q ?}, z0\.d, z0\.d
+.*: 453ff800 pmull { ?z0\.q-z1\.q ?}, z0\.d, z31\.d
+.*: 4520fbe0 pmull { ?z0\.q-z1\.q ?}, z31\.d, z0\.d
+.*: 453ffbe0 pmull { ?z0\.q-z1\.q ?}, z31\.d, z31\.d
+.*: 4520f81e pmull { ?z30\.q-z31\.q ?}, z0\.d, z0\.d
+.*: 453ff81e pmull { ?z30\.q-z31\.q ?}, z0\.d, z31\.d
+.*: 4520fbfe pmull { ?z30\.q-z31\.q ?}, z31\.d, z0\.d
+.*: 453ffbfe pmull { ?z30\.q-z31\.q ?}, z31\.d, z31\.d
diff --git a/gas/testsuite/gas/aarch64/sve-aes2.s b/gas/testsuite/gas/aarch64/sve-aes2.s
new file mode 100644
index 00000000000..d4f20915250
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve-aes2.s
@@ -0,0 +1,99 @@
+a:
+ aesdimc {z0.b-z1.b}, {z0.b-z1.b}, z0.q[0]
+ aesdimc {z0.b-z1.b}, {z0.b-z1.b}, z0.q[3]
+ aesdimc {z0.b-z1.b}, {z0.b-z1.b}, z31.q[0]
+ aesdimc {z0.b-z1.b}, {z0.b-z1.b}, z31.q[3]
+ aesdimc {z30.b-z31.b}, {z30.b-z31.b}, z0.q[0]
+ aesdimc {z30.b-z31.b}, {z30.b-z31.b}, z0.q[3]
+ aesdimc {z30.b-z31.b}, {z30.b-z31.b}, z31.q[0]
+ aesdimc {z30.b-z31.b}, {z30.b-z31.b}, z31.q[3]
+
+b:
+ aesdimc {z0.b-z3.b}, {z0.b-z3.b}, z0.q[0]
+ aesdimc {z0.b-z3.b}, {z0.b-z3.b}, z0.q[3]
+ aesdimc {z0.b-z3.b}, {z0.b-z3.b}, z31.q[0]
+ aesdimc {z0.b-z3.b}, {z0.b-z3.b}, z31.q[3]
+ aesdimc {z28.b-z31.b}, {z28.b-z31.b}, z0.q[0]
+ aesdimc {z28.b-z31.b}, {z28.b-z31.b}, z0.q[3]
+ aesdimc {z28.b-z31.b}, {z28.b-z31.b}, z31.q[0]
+ aesdimc {z28.b-z31.b}, {z28.b-z31.b}, z31.q[3]
+
+c:
+ aesd {z0.b-z1.b}, {z0.b-z1.b}, z0.q[0]
+ aesd {z0.b-z1.b}, {z0.b-z1.b}, z0.q[3]
+ aesd {z0.b-z1.b}, {z0.b-z1.b}, z31.q[0]
+ aesd {z0.b-z1.b}, {z0.b-z1.b}, z31.q[3]
+ aesd {z30.b-z31.b}, {z30.b-z31.b}, z0.q[0]
+ aesd {z30.b-z31.b}, {z30.b-z31.b}, z0.q[3]
+ aesd {z30.b-z31.b}, {z30.b-z31.b}, z31.q[0]
+ aesd {z30.b-z31.b}, {z30.b-z31.b}, z31.q[3]
+
+d:
+ aesd {z0.b-z3.b}, {z0.b-z3.b}, z0.q[0]
+ aesd {z0.b-z3.b}, {z0.b-z3.b}, z0.q[3]
+ aesd {z0.b-z3.b}, {z0.b-z3.b}, z31.q[0]
+ aesd {z0.b-z3.b}, {z0.b-z3.b}, z31.q[3]
+ aesd {z28.b-z31.b}, {z28.b-z31.b}, z0.q[0]
+ aesd {z28.b-z31.b}, {z28.b-z31.b}, z0.q[3]
+ aesd {z28.b-z31.b}, {z28.b-z31.b}, z31.q[0]
+ aesd {z28.b-z31.b}, {z28.b-z31.b}, z31.q[3]
+
+e:
+ aesemc {z0.b-z1.b}, {z0.b-z1.b}, z0.q[0]
+ aesemc {z0.b-z1.b}, {z0.b-z1.b}, z0.q[3]
+ aesemc {z0.b-z1.b}, {z0.b-z1.b}, z31.q[0]
+ aesemc {z0.b-z1.b}, {z0.b-z1.b}, z31.q[3]
+ aesemc {z30.b-z31.b}, {z30.b-z31.b}, z0.q[0]
+ aesemc {z30.b-z31.b}, {z30.b-z31.b}, z0.q[3]
+ aesemc {z30.b-z31.b}, {z30.b-z31.b}, z31.q[0]
+ aesemc {z30.b-z31.b}, {z30.b-z31.b}, z31.q[3]
+
+f:
+ aesemc {z0.b-z3.b}, {z0.b-z3.b}, z0.q[0]
+ aesemc {z0.b-z3.b}, {z0.b-z3.b}, z0.q[3]
+ aesemc {z0.b-z3.b}, {z0.b-z3.b}, z31.q[0]
+ aesemc {z0.b-z3.b}, {z0.b-z3.b}, z31.q[3]
+ aesemc {z28.b-z31.b}, {z28.b-z31.b}, z0.q[0]
+ aesemc {z28.b-z31.b}, {z28.b-z31.b}, z0.q[3]
+ aesemc {z28.b-z31.b}, {z28.b-z31.b}, z31.q[0]
+ aesemc {z28.b-z31.b}, {z28.b-z31.b}, z31.q[3]
+
+g:
+ aese {z0.b-z1.b}, {z0.b-z1.b}, z0.q[0]
+ aese {z0.b-z1.b}, {z0.b-z1.b}, z0.q[3]
+ aese {z0.b-z1.b}, {z0.b-z1.b}, z31.q[0]
+ aese {z0.b-z1.b}, {z0.b-z1.b}, z31.q[3]
+ aese {z30.b-z31.b}, {z30.b-z31.b}, z0.q[0]
+ aese {z30.b-z31.b}, {z30.b-z31.b}, z0.q[3]
+ aese {z30.b-z31.b}, {z30.b-z31.b}, z31.q[0]
+ aese {z30.b-z31.b}, {z30.b-z31.b}, z31.q[3]
+
+h:
+ aese {z0.b-z3.b}, {z0.b-z3.b}, z0.q[0]
+ aese {z0.b-z3.b}, {z0.b-z3.b}, z0.q[3]
+ aese {z0.b-z3.b}, {z0.b-z3.b}, z31.q[0]
+ aese {z0.b-z3.b}, {z0.b-z3.b}, z31.q[3]
+ aese {z28.b-z31.b}, {z28.b-z31.b}, z0.q[0]
+ aese {z28.b-z31.b}, {z28.b-z31.b}, z0.q[3]
+ aese {z28.b-z31.b}, {z28.b-z31.b}, z31.q[0]
+ aese {z28.b-z31.b}, {z28.b-z31.b}, z31.q[3]
+
+i:
+ pmlal {z0.q-z1.q}, z0.d, z0.d
+ pmlal {z0.q-z1.q}, z0.d, z31.d
+ pmlal {z0.q-z1.q}, z31.d, z0.d
+ pmlal {z0.q-z1.q}, z31.d, z31.d
+ pmlal {z30.q-z31.q}, z0.d, z0.d
+ pmlal {z30.q-z31.q}, z0.d, z31.d
+ pmlal {z30.q-z31.q}, z31.d, z0.d
+ pmlal {z30.q-z31.q}, z31.d, z31.d
+
+j:
+ pmull {z0.q-z1.q}, z0.d, z0.d
+ pmull {z0.q-z1.q}, z0.d, z31.d
+ pmull {z0.q-z1.q}, z31.d, z0.d
+ pmull {z0.q-z1.q}, z31.d, z31.d
+ pmull {z30.q-z31.q}, z0.d, z0.d
+ pmull {z30.q-z31.q}, z0.d, z31.d
+ pmull {z30.q-z31.q}, z31.d, z0.d
+ pmull {z30.q-z31.q}, z31.d, z31.d
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 3861c29ea40..826bd7d74d0 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -244,6 +244,12 @@ enum aarch64_feature_bit {
AARCH64_FEATURE_F8F32MM,
/* F8F16MM instructions. */
AARCH64_FEATURE_F8F16MM,
+ /* SVE_PMULL128 extension. */
+ AARCH64_FEATURE_SVE_AES,
+ /* SVE AES2 instructions. */
+ AARCH64_FEATURE_SVE_AES2,
+ /* SSVE_AES extension. */
+ AARCH64_FEATURE_SSVE_AES,
/* RCPC3 instructions. */
AARCH64_FEATURE_RCPC3,
/* Enhanced Software Step Extension. */
@@ -305,6 +311,8 @@ enum aarch64_feature_bit {
/* Virtual features. These are used to gate instructions that are enabled
by either of two (or more) sets of command line flags. */
+ /* +sve2 or +ssve-aes */
+ AARCH64_FEATURE_SVE2_SSVE_AES,
/* +fp8fma+sve or +ssve-fp8fma */
AARCH64_FEATURE_FP8FMA_SVE,
/* +fp8dot4+sve or +ssve-fp8dot4 */
@@ -977,6 +985,7 @@ enum aarch64_opnd
AARCH64_OPND_SME_Zn_INDEX1_16, /* Zn[index], bits [9:5] and [16:16]. */
AARCH64_OPND_SME_Zn_INDEX2_15, /* Zn[index], bits [9:5] and [16:15]. */
AARCH64_OPND_SME_Zn_INDEX2_16, /* Zn[index], bits [9:5] and [17:16]. */
+ AARCH64_OPND_SME_Zn_INDEX2_19, /* Zn[index], bits [9:5] and [20:19]. */
AARCH64_OPND_SME_Zn_INDEX3_14, /* Zn[index], bits [9:5] and [16:14]. */
AARCH64_OPND_SME_Zn_INDEX3_15, /* Zn[index], bits [9:5] and [17:15]. */
AARCH64_OPND_SME_Zn_INDEX4_14, /* Zn[index], bits [9:5] and [17:14]. */
diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
index 0250d7d6d89..30ec1e4d216 100644
--- a/opcodes/aarch64-asm-2.c
+++ b/opcodes/aarch64-asm-2.c
@@ -514,7 +514,7 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
case 1316: /* movz */
value = 1316; /* --> movz. */
break;
- case 3363: /* clrbhb */
+ case 3373: /* clrbhb */
case 1398: /* autibsp */
case 1397: /* autibz */
case 1396: /* autiasp */
@@ -555,7 +555,7 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
case 1353: /* dsb */
value = 1353; /* --> dsb. */
break;
- case 3364: /* trcit */
+ case 3374: /* trcit */
case 1384: /* brb */
case 1383: /* cosp */
case 1382: /* cpp */
@@ -710,49 +710,49 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
case 2091: /* str */
value = 2091; /* --> str. */
break;
- case 2519: /* mov */
- case 2521: /* mova */
- value = 2521; /* --> mova. */
+ case 2529: /* mov */
+ case 2531: /* mova */
+ value = 2531; /* --> mova. */
break;
- case 2520: /* mov */
- case 2522: /* mova */
- value = 2522; /* --> mova. */
+ case 2530: /* mov */
+ case 2532: /* mova */
+ value = 2532; /* --> mova. */
break;
- case 2540: /* psel */
- case 2539: /* psel */
- value = 2539; /* --> psel. */
+ case 2550: /* psel */
+ case 2549: /* psel */
+ value = 2549; /* --> psel. */
break;
- case 2745: /* mov */
- case 2753: /* mova */
- value = 2753; /* --> mova. */
+ case 2755: /* mov */
+ case 2763: /* mova */
+ value = 2763; /* --> mova. */
break;
- case 2746: /* mov */
- case 2754: /* mova */
- value = 2754; /* --> mova. */
+ case 2756: /* mov */
+ case 2764: /* mova */
+ value = 2764; /* --> mova. */
break;
- case 2747: /* mov */
- case 2755: /* mova */
- value = 2755; /* --> mova. */
+ case 2757: /* mov */
+ case 2765: /* mova */
+ value = 2765; /* --> mova. */
break;
- case 2748: /* mov */
- case 2756: /* mova */
- value = 2756; /* --> mova. */
+ case 2758: /* mov */
+ case 2766: /* mova */
+ value = 2766; /* --> mova. */
break;
- case 2749: /* mov */
- case 2757: /* mova */
- value = 2757; /* --> mova. */
+ case 2759: /* mov */
+ case 2767: /* mova */
+ value = 2767; /* --> mova. */
break;
- case 2750: /* mov */
- case 2758: /* mova */
- value = 2758; /* --> mova. */
+ case 2760: /* mov */
+ case 2768: /* mova */
+ value = 2768; /* --> mova. */
break;
- case 2751: /* mov */
- case 2759: /* mova */
- value = 2759; /* --> mova. */
+ case 2761: /* mov */
+ case 2769: /* mova */
+ value = 2769; /* --> mova. */
break;
- case 2752: /* mov */
- case 2760: /* mova */
- value = 2760; /* --> mova. */
+ case 2762: /* mov */
+ case 2770: /* mova */
+ value = 2770; /* --> mova. */
break;
default: return NULL;
}
@@ -834,14 +834,14 @@ aarch64_insert_operand (const aarch64_operand *self,
case 276:
case 277:
case 278:
- case 312:
- case 316:
+ case 313:
+ case 317:
return aarch64_ins_regno (self, info, code, inst, errors);
case 6:
case 122:
case 123:
- case 322:
- case 325:
+ case 323:
+ case 326:
return aarch64_ins_none (self, info, code, inst, errors);
case 17:
return aarch64_ins_reg_extended (self, info, code, inst, errors);
@@ -856,7 +856,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case 37:
case 38:
case 39:
- case 327:
+ case 328:
return aarch64_ins_reglane (self, info, code, inst, errors);
case 40:
case 41:
@@ -883,12 +883,13 @@ aarch64_insert_operand (const aarch64_operand *self,
case 309:
case 310:
case 311:
- case 313:
+ case 312:
case 314:
case 315:
- case 317:
+ case 316:
case 318:
case 319:
+ case 320:
return aarch64_ins_simple_index (self, info, code, inst, errors);
case 43:
return aarch64_ins_reglist (self, info, code, inst, errors);
@@ -942,13 +943,13 @@ aarch64_insert_operand (const aarch64_operand *self,
case 219:
case 220:
case 281:
- case 320:
case 321:
- case 323:
+ case 322:
case 324:
- case 326:
- case 331:
+ case 325:
+ case 327:
case 332:
+ case 333:
return aarch64_ins_imm (self, info, code, inst, errors);
case 52:
case 53:
@@ -1166,16 +1167,16 @@ aarch64_insert_operand (const aarch64_operand *self,
return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
case 293:
return aarch64_ins_plain_shrimm (self, info, code, inst, errors);
- case 328:
case 329:
case 330:
+ case 331:
return aarch64_ins_x0_to_x30 (self, info, code, inst, errors);
- case 333:
case 334:
case 335:
case 336:
- return aarch64_ins_rcpc3_addr_opt_offset (self, info, code, inst, errors);
case 337:
+ return aarch64_ins_rcpc3_addr_opt_offset (self, info, code, inst, errors);
+ case 338:
return aarch64_ins_rcpc3_addr_offset (self, info, code, inst, errors);
default: assert (0); abort ();
}
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index ee8fe7c5d10..f84562544cc 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -62,7 +62,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0000000100xxxxxxxxxxxxxxxx00xxx
fmopa. */
- return 2496;
+ return 2506;
}
else
{
@@ -70,7 +70,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0000000100xxxxxxxxxxxxxxxx10xxx
fmops. */
- return 2499;
+ return 2509;
}
}
else
@@ -81,7 +81,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0000000100xxxxxxxxxxxxxxxx01xxx
bmopa. */
- return 2600;
+ return 2610;
}
else
{
@@ -89,7 +89,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0000000100xxxxxxxxxxxxxxxx11xxx
bmops. */
- return 2601;
+ return 2611;
}
}
}
@@ -102,7 +102,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0000000x10xxxxxxxxxxxxxxxx0xxxx
fmopa. */
- return 2497;
+ return 2507;
}
else
{
@@ -110,7 +110,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0000000x10xxxxxxxxxxxxxxxx1xxxx
fmops. */
- return 2500;
+ return 2510;
}
}
}
@@ -128,7 +128,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx00000xxxxxxxxxxxxxxxxx
mova. */
- return 2522;
+ return 2532;
}
else
{
@@ -140,7 +140,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000x0010000xxxxxxxxxxxxxxxx
addha. */
- return 2488;
+ return 2498;
}
else
{
@@ -148,7 +148,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000x1010000xxxxxxxxxxxxxxxx
addha. */
- return 2489;
+ return 2499;
}
}
else
@@ -159,7 +159,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000x0010001xxxxxxxxxxxxxxxx
addva. */
- return 2492;
+ return 2502;
}
else
{
@@ -167,7 +167,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000x1010001xxxxxxxxxxxxxxxx
addva. */
- return 2493;
+ return 2503;
}
}
}
@@ -180,7 +180,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000x00x100xxxxxxxxxxxxxxxxx
zero. */
- return 2523;
+ return 2533;
}
else
{
@@ -188,7 +188,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000x10x100xxxxxxxxxxxxxxxxx
zero. */
- return 3030;
+ return 3040;
}
}
}
@@ -202,7 +202,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx0x001xxxxxxx0xxxxxxxxx
mova. */
- return 2521;
+ return 2531;
}
else
{
@@ -216,7 +216,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000000x0010xxxxxx1xxxxxxxxx
movaz. */
- return 3495;
+ return 3505;
}
else
{
@@ -224,7 +224,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000100x0010xxxxxx1xxxxxxxxx
movaz. */
- return 3497;
+ return 3507;
}
}
else
@@ -235,7 +235,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000010x0010xxxxxx1xxxxxxxxx
movaz. */
- return 3496;
+ return 3506;
}
else
{
@@ -243,7 +243,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000110x0010xxxxxx1xxxxxxxxx
movaz. */
- return 3498;
+ return 3508;
}
}
}
@@ -253,7 +253,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx0x0011xxxxxx1xxxxxxxxx
movaz. */
- return 3499;
+ return 3509;
}
}
}
@@ -271,7 +271,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000x000101x00xxxxxxxxxxxxxx
luti4. */
- return 3635;
+ return 3645;
}
else
{
@@ -279,7 +279,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000x000101x10xxxxxxxxxxxxxx
luti4. */
- return 2744;
+ return 2754;
}
}
else
@@ -288,7 +288,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000x000101xx1xxxxxxxxxxxxxx
luti4. */
- return 2743;
+ return 2753;
}
}
else
@@ -297,7 +297,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000x100101xxxxxxxxxxxxxxxxx
luti4. */
- return 2742;
+ return 2752;
}
}
else
@@ -310,7 +310,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx01101x00xxxxxxxxxxxxxx
luti4. */
- return 3636;
+ return 3646;
}
else
{
@@ -318,7 +318,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx01101x10xxxxxxxxxxxxxx
luti4. */
- return 3492;
+ return 3502;
}
}
else
@@ -327,7 +327,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx01101xx1xxxxxxxxxxxxxx
luti4. */
- return 3491;
+ return 3501;
}
}
}
@@ -347,7 +347,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx0x010xxxxx00xxxxxxxxxx
mova. */
- return 2759;
+ return 2769;
}
else
{
@@ -357,7 +357,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx0x011xxxxx000xxxxxxxxx
mova. */
- return 2755;
+ return 2765;
}
else
{
@@ -369,7 +369,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000000x011xxxxx001xxxxxxxxx
movaz. */
- return 3485;
+ return 3495;
}
else
{
@@ -377,7 +377,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000100x011xxxxx001xxxxxxxxx
movaz. */
- return 3487;
+ return 3497;
}
}
else
@@ -388,7 +388,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000010x011xxxxx001xxxxxxxxx
movaz. */
- return 3486;
+ return 3496;
}
else
{
@@ -396,7 +396,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000110x011xxxxx001xxxxxxxxx
movaz. */
- return 3488;
+ return 3498;
}
}
}
@@ -420,7 +420,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000000011000xxx00xxxxxxxxxx
zero. */
- return 3500;
+ return 3510;
}
else
{
@@ -428,7 +428,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000000011100xxx00xxxxxxxxxx
zero. */
- return 3501;
+ return 3511;
}
}
else
@@ -439,7 +439,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000000011010xxx00xxxxxxxxxx
zero. */
- return 3503;
+ return 3513;
}
else
{
@@ -447,7 +447,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000000011110xxx00xxxxxxxxxx
zero. */
- return 3506;
+ return 3516;
}
}
}
@@ -461,7 +461,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000000011001xxx00xxxxxxxxxx
zero. */
- return 3502;
+ return 3512;
}
else
{
@@ -469,7 +469,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000000011101xxx00xxxxxxxxxx
zero. */
- return 3505;
+ return 3515;
}
}
else
@@ -480,7 +480,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000000011011xxx00xxxxxxxxxx
zero. */
- return 3504;
+ return 3514;
}
else
{
@@ -488,7 +488,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000000011111xxx00xxxxxxxxxx
zero. */
- return 3507;
+ return 3517;
}
}
}
@@ -501,7 +501,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000100011xxx0xx00xxxxxxxxxx
luti2. */
- return 2741;
+ return 2751;
}
else
{
@@ -509,7 +509,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000100011xxx1xx00xxxxxxxxxx
luti2. */
- return 2740;
+ return 2750;
}
}
}
@@ -525,7 +525,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x100000001001100xxxx00xxxxxxxxxx
movt. */
- return 2762;
+ return 2772;
}
else
{
@@ -533,7 +533,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x100000001001110xxxx00xxxxxxxxxx
movt. */
- return 2761;
+ return 2771;
}
}
else
@@ -542,7 +542,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000010011x1xxxx00xxxxxxxxxx
movt. */
- return 3637;
+ return 3647;
}
}
else
@@ -551,7 +551,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000110011xxxxxx00xxxxxxxxxx
luti2. */
- return 2739;
+ return 2749;
}
}
}
@@ -563,7 +563,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx0111xxx0xx00xxxxxxxxxx
luti2. */
- return 3490;
+ return 3500;
}
else
{
@@ -571,7 +571,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx0111xxx1xx00xxxxxxxxxx
luti2. */
- return 3489;
+ return 3499;
}
}
}
@@ -584,7 +584,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx0xx10xxxxx10xxxxxxxxxx
mova. */
- return 2757;
+ return 2767;
}
else
{
@@ -594,7 +594,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx0xx11xxxxx100xxxxxxxxx
mova. */
- return 2753;
+ return 2763;
}
else
{
@@ -602,7 +602,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx0xx11xxxxx101xxxxxxxxx
movaz. */
- return 3493;
+ return 3503;
}
}
}
@@ -617,7 +617,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx0xx10xxxxx01xxxxxxxxxx
mova. */
- return 2760;
+ return 2770;
}
else
{
@@ -627,7 +627,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx0xx11xxxxx010xxxxxxxxx
mova. */
- return 2756;
+ return 2766;
}
else
{
@@ -639,7 +639,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000000xx11xxxxx011xxxxxxxxx
movaz. */
- return 3481;
+ return 3491;
}
else
{
@@ -647,7 +647,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000100xx11xxxxx011xxxxxxxxx
movaz. */
- return 3483;
+ return 3493;
}
}
else
@@ -658,7 +658,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000010xx11xxxxx011xxxxxxxxx
movaz. */
- return 3482;
+ return 3492;
}
else
{
@@ -666,7 +666,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000110xx11xxxxx011xxxxxxxxx
movaz. */
- return 3484;
+ return 3494;
}
}
}
@@ -680,7 +680,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx0xx10xxxxx11xxxxxxxxxx
mova. */
- return 2758;
+ return 2768;
}
else
{
@@ -690,7 +690,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx0xx11xxxxx110xxxxxxxxx
mova. */
- return 2754;
+ return 2764;
}
else
{
@@ -698,7 +698,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx0xx11xxxxx111xxxxxxxxx
movaz. */
- return 3494;
+ return 3504;
}
}
}
@@ -726,7 +726,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000000xxxxx000xxxxxxxxxxxx0
ld1b. */
- return 2678;
+ return 2688;
}
else
{
@@ -734,7 +734,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000000xxxxx100xxxxxxxxxxxx0
ld1b. */
- return 2679;
+ return 2689;
}
}
else
@@ -745,7 +745,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000000xxxxx010xxxxxxxxxxxx0
ld1w. */
- return 2702;
+ return 2712;
}
else
{
@@ -753,7 +753,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000000xxxxx110xxxxxxxxxxxx0
ld1w. */
- return 2703;
+ return 2713;
}
}
}
@@ -767,7 +767,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000000xxxxx001xxxxxxxxxxxx0
ld1h. */
- return 2694;
+ return 2704;
}
else
{
@@ -775,7 +775,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000000xxxxx101xxxxxxxxxxxx0
ld1h. */
- return 2695;
+ return 2705;
}
}
else
@@ -786,7 +786,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000000xxxxx011xxxxxxxxxxxx0
ld1d. */
- return 2686;
+ return 2696;
}
else
{
@@ -794,7 +794,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000000xxxxx111xxxxxxxxxxxx0
ld1d. */
- return 2687;
+ return 2697;
}
}
}
@@ -811,7 +811,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000000xxxxx000xxxxxxxxxxxx1
ldnt1b. */
- return 2710;
+ return 2720;
}
else
{
@@ -819,7 +819,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000000xxxxx100xxxxxxxxxxxx1
ldnt1b. */
- return 2711;
+ return 2721;
}
}
else
@@ -830,7 +830,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000000xxxxx010xxxxxxxxxxxx1
ldnt1w. */
- return 2734;
+ return 2744;
}
else
{
@@ -838,7 +838,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000000xxxxx110xxxxxxxxxxxx1
ldnt1w. */
- return 2735;
+ return 2745;
}
}
}
@@ -852,7 +852,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000000xxxxx001xxxxxxxxxxxx1
ldnt1h. */
- return 2726;
+ return 2736;
}
else
{
@@ -860,7 +860,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000000xxxxx101xxxxxxxxxxxx1
ldnt1h. */
- return 2727;
+ return 2737;
}
}
else
@@ -871,7 +871,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000000xxxxx011xxxxxxxxxxxx1
ldnt1d. */
- return 2718;
+ return 2728;
}
else
{
@@ -879,7 +879,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000000xxxxx111xxxxxxxxxxxx1
ldnt1d. */
- return 2719;
+ return 2729;
}
}
}
@@ -891,7 +891,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1100000000xxxxxxxxxxxxxxxxxxxxx
ld1b. */
- return 2524;
+ return 2534;
}
}
else
@@ -906,7 +906,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000100xxxxxxxxxxxxxxxx00xxx
smopa. */
- return 2503;
+ return 2513;
}
else
{
@@ -914,7 +914,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000100xxxxxxxxxxxxxxxx01xxx
smopa. */
- return 2824;
+ return 2834;
}
}
else
@@ -923,7 +923,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1100000100xxxxxxxxxxxxxxxx0xxxx
ld1w. */
- return 2526;
+ return 2536;
}
}
else
@@ -934,7 +934,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx100000100xxxxxxxxxxxxxxxx10xxx
smops. */
- return 2505;
+ return 2515;
}
else
{
@@ -942,7 +942,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx100000100xxxxxxxxxxxxxxxx11xxx
smops. */
- return 2825;
+ return 2835;
}
}
}
@@ -965,7 +965,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000010xxxxx000xxxxxxxxxxxx0
ld1b. */
- return 2674;
+ return 2684;
}
else
{
@@ -973,7 +973,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000010xxxxx100xxxxxxxxxxxx0
ld1b. */
- return 2675;
+ return 2685;
}
}
else
@@ -984,7 +984,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000010xxxxx010xxxxxxxxxxxx0
ld1w. */
- return 2698;
+ return 2708;
}
else
{
@@ -992,7 +992,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000010xxxxx110xxxxxxxxxxxx0
ld1w. */
- return 2699;
+ return 2709;
}
}
}
@@ -1006,7 +1006,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000010xxxxx001xxxxxxxxxxxx0
ld1h. */
- return 2690;
+ return 2700;
}
else
{
@@ -1014,7 +1014,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000010xxxxx101xxxxxxxxxxxx0
ld1h. */
- return 2691;
+ return 2701;
}
}
else
@@ -1025,7 +1025,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000010xxxxx011xxxxxxxxxxxx0
ld1d. */
- return 2682;
+ return 2692;
}
else
{
@@ -1033,7 +1033,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000010xxxxx111xxxxxxxxxxxx0
ld1d. */
- return 2683;
+ return 2693;
}
}
}
@@ -1050,7 +1050,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000010xxxxx000xxxxxxxxxxxx1
ldnt1b. */
- return 2706;
+ return 2716;
}
else
{
@@ -1058,7 +1058,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000010xxxxx100xxxxxxxxxxxx1
ldnt1b. */
- return 2707;
+ return 2717;
}
}
else
@@ -1069,7 +1069,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000010xxxxx010xxxxxxxxxxxx1
ldnt1w. */
- return 2730;
+ return 2740;
}
else
{
@@ -1077,7 +1077,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000010xxxxx110xxxxxxxxxxxx1
ldnt1w. */
- return 2731;
+ return 2741;
}
}
}
@@ -1091,7 +1091,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000010xxxxx001xxxxxxxxxxxx1
ldnt1h. */
- return 2722;
+ return 2732;
}
else
{
@@ -1099,7 +1099,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000010xxxxx101xxxxxxxxxxxx1
ldnt1h. */
- return 2723;
+ return 2733;
}
}
else
@@ -1110,7 +1110,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000010xxxxx011xxxxxxxxxxxx1
ldnt1d. */
- return 2714;
+ return 2724;
}
else
{
@@ -1118,7 +1118,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000010xxxxx111xxxxxxxxxxxx1
ldnt1d. */
- return 2715;
+ return 2725;
}
}
}
@@ -1130,7 +1130,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1100000010xxxxxxxxxxxxxxxxxxxxx
ld1h. */
- return 2525;
+ return 2535;
}
}
else
@@ -1143,7 +1143,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0100000110xxxxxxxxxxxxxxxx0xxxx
smopa. */
- return 2504;
+ return 2514;
}
else
{
@@ -1151,7 +1151,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1100000110xxxxxxxxxxxxxxxx0xxxx
ld1d. */
- return 2527;
+ return 2537;
}
[...]
[diff truncated at 100000 bytes]
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