[binutils-gdb] RISC-V: Cleanup the imply code and test cases for vendor xsf extensions.

[Nelson Chu]

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=a73bec4396c7da8b5a7a8eea178d9f80d0117062

commit a73bec4396c7da8b5a7a8eea178d9f80d0117062
Author: Nelson Chu <nelson@rivosinc.com>
Date:   Mon Jan 13 10:58:13 2025 +0800

    RISC-V: Cleanup the imply code and test cases for vendor xsf extensions.

Diff:
---
 bfd/elfxx-riscv.c                                     | 1 -
 gas/testsuite/gas/riscv/imply.d                       | 3 +++
 gas/testsuite/gas/riscv/imply.s                       | 4 ++++
 gas/testsuite/gas/riscv/march-imply-xsfvfnrclipxfqf.d | 6 ------
 gas/testsuite/gas/riscv/march-imply-xsfvqmaccdod.d    | 6 ------
 gas/testsuite/gas/riscv/march-imply-xsfvqmaccqoq.d    | 6 ------
 6 files changed, 7 insertions(+), 19 deletions(-)

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index ccece950664..a609781bc04 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1188,7 +1188,6 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
 
   {"xsfvcp", "+zve32x", check_implicit_always},
   {"xsfvqmaccqoq", "+zve32x,+zvl256b", check_implicit_always},
-  {"xsfvqmaccqoq", "+zvl256b", check_implicit_always},
   {"xsfvqmaccdod", "+zve32x,+zvl128b", check_implicit_always},
   {"xsfvfnrclipxfqf", "+zve32f", check_implicit_always},
 
diff --git a/gas/testsuite/gas/riscv/imply.d b/gas/testsuite/gas/riscv/imply.d
index 474694d9071..8337bd33e8f 100644
--- a/gas/testsuite/gas/riscv/imply.d
+++ b/gas/testsuite/gas/riscv/imply.d
@@ -19,6 +19,9 @@ SYMBOL TABLE:
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zaamo1p0_zacas1p0
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_a2p1_zaamo1p0_zalrsc1p0
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfvcp1p0
+[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zicsr2p0_zve32x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0
+[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zicsr2p0_zve32x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0
+[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvl32b1p0_xsfvfnrclipxfqf1p0
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_f2p2_zicsr2p0_zfhmin1p0_zve32f1p0_zve32x1p0_zvfh1p0_zvfhmin1p0_zvl32b1p0
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfhmin1p0_zvl32b1p0
diff --git a/gas/testsuite/gas/riscv/imply.s b/gas/testsuite/gas/riscv/imply.s
index 790c6f335ee..2ef14ab6713 100644
--- a/gas/testsuite/gas/riscv/imply.s
+++ b/gas/testsuite/gas/riscv/imply.s
@@ -21,6 +21,10 @@ imply zacas
 imply a
 
 imply xsfvcp
+imply xsfvqmaccqoq
+imply xsfvqmaccdod
+imply xsfvfnrclipxfqf
+
 imply v
 imply zvfh
 imply zvfhmin
diff --git a/gas/testsuite/gas/riscv/march-imply-xsfvfnrclipxfqf.d b/gas/testsuite/gas/riscv/march-imply-xsfvfnrclipxfqf.d
deleted file mode 100644
index e77fee0298c..00000000000
--- a/gas/testsuite/gas/riscv/march-imply-xsfvfnrclipxfqf.d
+++ /dev/null
@@ -1,6 +0,0 @@
-#as: -march=rv32i_xsfvfnrclipxfqf -march-attr -misa-spec=20191213
-#readelf: -A
-#source: empty.s
-Attribute Section: riscv
-File Attributes
-  Tag_RISCV_arch: "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvl32b1p0_xsfvfnrclipxfqf1p0"
diff --git a/gas/testsuite/gas/riscv/march-imply-xsfvqmaccdod.d b/gas/testsuite/gas/riscv/march-imply-xsfvqmaccdod.d
deleted file mode 100644
index 47e91f89367..00000000000
--- a/gas/testsuite/gas/riscv/march-imply-xsfvqmaccdod.d
+++ /dev/null
@@ -1,6 +0,0 @@
-#as: -march=rv32i_xsfvqmaccdod -march-attr -misa-spec=20191213
-#readelf: -A
-#source: empty.s
-Attribute Section: riscv
-File Attributes
-  Tag_RISCV_arch: "rv32i2p1_zicsr2p0_zve32x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccdod1p0"
diff --git a/gas/testsuite/gas/riscv/march-imply-xsfvqmaccqoq.d b/gas/testsuite/gas/riscv/march-imply-xsfvqmaccqoq.d
deleted file mode 100644
index 784a8acd09d..00000000000
--- a/gas/testsuite/gas/riscv/march-imply-xsfvqmaccqoq.d
+++ /dev/null
@@ -1,6 +0,0 @@
-#as: -march=rv32i_xsfvqmaccqoq -march-attr -misa-spec=20191213
-#readelf: -A
-#source: empty.s
-Attribute Section: riscv
-File Attributes
-  Tag_RISCV_arch: "rv32i2p1_zicsr2p0_zve32x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfvqmaccqoq1p0"