[binutils-gdb] aarch64: Fix incorrect gating of sme-lutv2 instructions

[Andrew Carlotti]

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=aeae65b3aafeed75d605ee479cfda3ec1a4d0f0d

commit aeae65b3aafeed75d605ee479cfda3ec1a4d0f0d
Author: Andrew Carlotti <andrew.carlotti@arm.com>
Date:   Mon Jan 6 16:56:22 2025 +0000

    aarch64: Fix incorrect gating of sme-lutv2 instructions
    
    Only the strided form of the luti4 intrinsic requires FEAT_SME2p1.

Diff:
---
 gas/testsuite/gas/aarch64/sme2-lutv2-bad-2.d |  3 +++
 gas/testsuite/gas/aarch64/sme2-lutv2-bad-2.l |  5 +++++
 opcodes/aarch64-tbl.h                        | 14 ++++++++++----
 3 files changed, 18 insertions(+), 4 deletions(-)

diff --git a/gas/testsuite/gas/aarch64/sme2-lutv2-bad-2.d b/gas/testsuite/gas/aarch64/sme2-lutv2-bad-2.d
new file mode 100644
index 00000000000..d96315f3fb3
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-lutv2-bad-2.d
@@ -0,0 +1,3 @@
+#as: -march=armv8-a+sme2+sme-lutv2
+#source: sme2-lutv2.s
+#error_output: sme2-lutv2-bad-2.l
diff --git a/gas/testsuite/gas/aarch64/sme2-lutv2-bad-2.l b/gas/testsuite/gas/aarch64/sme2-lutv2-bad-2.l
new file mode 100644
index 00000000000..ada6d3a5ed0
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-lutv2-bad-2.l
@@ -0,0 +1,5 @@
+[^ :]+: Assembler messages:
+.*: Error: selected processor does not support `luti4 { ?z0.b,z4.b,z8.b,z12.b ?},zt0,{ ?z0 ?- ?z1 ?}'
+.*: Error: selected processor does not support `luti4 { ?z19.b,z23.b,z27.b,z31.b ?},zt0,{ ?z0 ?- ?z1 ?}'
+.*: Error: selected processor does not support `luti4 { ?z0.b,z4.b,z8.b,z12.b ?},zt0,{ ?z30 ?- ?z31 ?}'
+.*: Error: selected processor does not support `luti4 { ?z17.b,z21.b,z25.b,z29.b ?},zt0,{ ?z12 ?- ?z13 ?}'
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index f7dea8f416c..1025ef95c23 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2849,8 +2849,10 @@ static const aarch64_feature_set aarch64_feature_lut_sve2 =
   AARCH64_FEATURES (2, LUT, SVE2);
 static const aarch64_feature_set aarch64_feature_brbe =
   AARCH64_FEATURE (BRBE);
-static const aarch64_feature_set aarch64_feature_sme_lutv2 =
-  AARCH64_FEATURES (3, SME_LUTv2, SME2, SME2p1);
+static const aarch64_feature_set aarch64_feature_lutv2_sme2 =
+  AARCH64_FEATURES (2, SME_LUTv2, SME2);
+static const aarch64_feature_set aarch64_feature_lutv2_sme2p1 =
+  AARCH64_FEATURES (2, SME_LUTv2, SME2p1);
 static const aarch64_feature_set aarch64_feature_fp8fma =
   AARCH64_FEATURE (FP8FMA);
 static const aarch64_feature_set aarch64_feature_fp8dot4 =
@@ -2948,7 +2950,8 @@ static const aarch64_feature_set aarch64_feature_sme_f16f16 =
 #define LUT &aarch64_feature_lut
 #define LUT_SVE2 &aarch64_feature_lut_sve2
 #define BRBE		&aarch64_feature_brbe
-#define LUTv2_SME2 &aarch64_feature_sme_lutv2
+#define LUTv2_SME2	&aarch64_feature_lutv2_sme2
+#define LUTv2_SME2p1	&aarch64_feature_lutv2_sme2p1
 #define FP8FMA		&aarch64_feature_fp8fma
 #define FP8DOT4		&aarch64_feature_fp8dot4
 #define FP8DOT2		&aarch64_feature_fp8dot2
@@ -3162,6 +3165,9 @@ static const aarch64_feature_set aarch64_feature_sme_f16f16 =
 #define LUTv2_SME2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS)	\
   { NAME, OPCODE, MASK, CLASS, 0, LUTv2_SME2, OPS, QUALS, \
     FLAGS, 0, 0, NULL }
+#define LUTv2_SME2p1_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS)	\
+  { NAME, OPCODE, MASK, CLASS, 0, LUTv2_SME2p1, OPS, QUALS, \
+    FLAGS, 0, 0, NULL }
 #define FP8FMA_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
   { NAME, OPCODE, MASK, CLASS, 0, FP8FMA, OPS, QUALS, FLAGS, 0, 0, NULL }
 #define FP8DOT4_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
@@ -6839,7 +6845,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
 
   /* SME2 lutv2.  */
   LUTv2_SME2_INSN ("luti4", 0xc08b0000, 0xffffcc23, sme_size_12_b, OP3 (SME_Zdnx4, SME_ZT0, SME_Znx2_BIT_INDEX), OP_SVE_VUU_B, F_STRICT | 0),
-  LUTv2_SME2_INSN ("luti4", 0xc09b0000, 0xffffcc2c, sme_size_12_b, OP3 (SME_Zdnx4_STRIDED, SME_ZT0, SME_Znx2_BIT_INDEX), OP_SVE_VUU_B, F_STRICT | 0),
+  LUTv2_SME2p1_INSN ("luti4", 0xc09b0000, 0xffffcc2c, sme_size_12_b, OP3 (SME_Zdnx4_STRIDED, SME_ZT0, SME_Znx2_BIT_INDEX), OP_SVE_VUU_B, F_STRICT | 0),
   LUTv2_SME2_INSN ("movt", 0xc04f03e0, 0xffffcfe0, sme_misc, OP2 (SME_ZT0_INDEX2_12, SVE_Zt), {}, 0),
   /* SME FP16 ZA-targeting addition instructions.  */
   SME_F16F16_F8F16_INSNC("fadd", 0xc1a41c00, 0xffff9c38, sme_misc, OP2 (SME_ZA_array_off3_0, SME_Znx2), OP_SVE_HH, F_OD (2), 0),