https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=5de345074fdaaacaee0f8e09bb44489516d30811
commit 5de345074fdaaacaee0f8e09bb44489516d30811
Author: Srinath Parvathaneni <srinath.parvathaneni@arm.com>
Date: Fri Jan 10 14:07:17 2025 +0000
aarch64: Add support for FEAT_SME_F16F16 fmla and fmls instructions.
This patch adds support for FEAT_SME_F16F16 instructions fmla and fmls,
which are available on passing command line flags +sme-f16f16 and the
spec is available here[1].
[1]: https://developer.arm.com/documentation/ddi0602/2024-06/SME-Instructions?lang=en
Diff:
---
gas/testsuite/gas/aarch64/sme-f16f16-3-bad.d | 4 +
gas/testsuite/gas/aarch64/sme-f16f16-3-bad.l | 141 ++++++
gas/testsuite/gas/aarch64/sme-f16f16-3-bad.s | 133 +++++
gas/testsuite/gas/aarch64/sme-f16f16-3.d | 102 ++++
gas/testsuite/gas/aarch64/sme-f16f16-3.s | 109 +++++
opcodes/aarch64-dis-2.c | 704 ++++++++++++++++-----------
opcodes/aarch64-tbl.h | 12 +
7 files changed, 919 insertions(+), 286 deletions(-)
diff --git a/gas/testsuite/gas/aarch64/sme-f16f16-3-bad.d b/gas/testsuite/gas/aarch64/sme-f16f16-3-bad.d
new file mode 100644
index 00000000000..633de4829dd
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme-f16f16-3-bad.d
@@ -0,0 +1,4 @@
+#name: Test of invalid FEAT_SME_F16F16 fmla and fmls instructions.
+#as: -march=armv8-a+sme-f16f16
+#source: sme-f16f16-3-bad.s
+#error_output: sme-f16f16-3-bad.l
diff --git a/gas/testsuite/gas/aarch64/sme-f16f16-3-bad.l b/gas/testsuite/gas/aarch64/sme-f16f16-3-bad.l
new file mode 100644
index 00000000000..7ce08d36d69
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme-f16f16-3-bad.l
@@ -0,0 +1,141 @@
+.*: Assembler messages:
+.*: Error: invalid vector group size at operand 1 -- `fmla za.s\[w8,0,vgx3\],{ ?z0.h-z1.h ?},z0.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `fmla za.h\[w14,0,vgx3\],{ ?z10.h-z1.h ?},z0.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `fmla za.h\[w8,15,vgx3\],{ ?z0.h-z1.h ?},z0.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `fmla za.d\[w8,0,vgx3\],{ ?z30.h-z31.h ?},z0.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `fmla za.h\[w8,0,vgx3\],{ ?z0.h-z1.h ?},z15.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `fmla za.h\[w8,0,vgx3\],{ ?z0.h-z1.h ?},z0.h\[7\]'
+.*: Error: expected a list of 2 registers at operand 2 -- `fmla za.h\[w8,0,vgx2\],{ ?z0.h ?},z0.h\[7\]'
+.*: Error: expected a list of 2 registers at operand 2 -- `fmla za.h\[w8,0,vgx2\],{ ?z0.h ?},z0.h'
+.*: Error: missing type suffix at operand 2 -- `fmla za.h\[w8,0,vgx2\],{ ?z0-z1 ?},z0.h\[7\]'
+.*: Error: missing type suffix at operand 2 -- `fmla za.h\[w8,0,vgx2\],{ ?z0-z1 ?}'
+.*: Error: invalid vector group size at operand 1 -- `fmla za.b\[w8,0,vgx1\],{ ?z0.h-z1.h ?},z0.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `fmla za.h\[w14,0,vgx1\],{ ?z10.h-z1.h ?},z0.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `fmla za.h\[w8,15,vgx1\],{ ?z0.h-z1.h ?},z0.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `fmla za.h\[w8,0,vgx1\],{ ?z30.h-z31.h ?},z0.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `fmla za.s\[w8,0,vgx1\],{ ?z0.h-z1.h ?},z15.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `fmla za.h\[w8,0,vgx1\],{ ?z0.h-z1.h ?},z0.h\[7\]'
+.*: Error: expected a list of 4 registers at operand 2 -- `fmla za.h\[w8,0,vgx4\],{ ?z0.h ?},z0.h\[7\]'
+.*: Error: expected a list of 4 registers at operand 2 -- `fmla za.h\[w8,0,vgx4\],{ ?z0.h ?},z0.h'
+.*: Error: missing type suffix at operand 2 -- `fmla za.h\[w8,0,vgx4\],{ ?z0-z1 ?},z0.h\[7\]'
+.*: Error: missing type suffix at operand 2 -- `fmla za.h\[w8,0,vgx4\],{ ?z0-z1 ?}'
+.*: Error: invalid vector group size at operand 1 -- `fmla za.s\[w8,0,vgx3\],{ ?z0.h-z1.h ?},z0.h'
+.*: Error: invalid vector group size at operand 1 -- `fmla za.h\[w14,0,vgx3\],{ ?z10.h-z1.h ?},z0.h'
+.*: Error: invalid vector group size at operand 1 -- `fmla za.h\[w8,15,vgx3\],{ ?z0.h-z1.h ?},z0.h'
+.*: Error: invalid vector group size at operand 1 -- `fmla za.d\[w8,0,vgx3\],{ ?z31.h-z0.h ?},z0.h'
+.*: Error: invalid vector group size at operand 1 -- `fmla za.h\[w8,0,vgx3\],{ ?z0.h-z1.h ?},z15.h'
+.*: Error: expected a list of 2 registers at operand 2 -- `fmla za.h\[w8,0,vgx2\],{ ?z0.h ?},z15.h'
+.*: Error: operand mismatch -- `fmla za.h\[w8,0,vgx2\],{ ?z0.h-z1.h ?},z15'
+.*: Info: did you mean this\?
+.*: Info: fmla za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}, z15.h
+.*: Error: operand mismatch -- `fmla za.h\[w8,0,vgx2\],{ ?z0.h-z1.h ?},z20'
+.*: Info: did you mean this\?
+.*: Info: fmla za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}, z20.h
+.*: Error: comma expected between operands at operand 3 -- `fmla za.h\[w8,0,vgx2\],{ ?z0.h-z1.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `fmla za.h\[w8,0,vgx1\],{ ?z0.h-z1.h ?},z0.h'
+.*: Error: invalid vector group size at operand 1 -- `fmla za.s\[w14,0,vgx1\],{ ?z10.h-z1.h ?},z0.h'
+.*: Error: invalid vector group size at operand 1 -- `fmla za.h\[w8,15,vgx1\],{ ?z0.h-z1.h ?},z0.h'
+.*: Error: invalid vector group size at operand 1 -- `fmla za.h\[w8,0,vgx1\],{ ?z31.h-z2.h ?},z0.h'
+.*: Error: invalid vector group size at operand 1 -- `fmla za.b\[w8,0,vgx1\],{ ?z0.h-z1.h ?},z15.h'
+.*: Error: expected a list of 4 registers at operand 2 -- `fmla za.h\[w8,0,vgx4\],{ ?z0.h ?},z15.h'
+.*: Error: operand mismatch -- `fmla za.h\[w8,0,vgx4\],{ ?z0.h-z1.h ?},z15'
+.*: Info: did you mean this\?
+.*: Info: fmla za.h\[w8, 0, vgx4\], { ?z0.h-z1.h ?}, z15.h
+.*: Error: operand mismatch -- `fmla za.h\[w8,0,vgx4\],{ ?z0.h-z1.h ?},z20'
+.*: Info: did you mean this\?
+.*: Info: fmla za.h\[w8, 0, vgx4\], { ?z0.h-z1.h ?}, z20.h
+.*: Error: comma expected between operands at operand 3 -- `fmla za.h\[w8,0,vgx4\],{ ?z0.h-z1.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `fmla za.s\[w8,0,vgx3\],{ ?z0.h-z1.h ?},{ ?z0.h-z1.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `fmla za.h\[w14,0,vgx3\],{ ?z10.h-z1.h ?},{ ?z0.h-z1.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `fmla za.d\[w8,15,vgx3\],{ ?z0.h-z1.h ?},{ ?z0.h-z1.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `fmla za.h\[w8,0,vgx3\],{ ?z30.h-z31.h ?},{ ?z0.h-z1.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `fmla za.b\[w8,0,vgx3\],{ ?z0.h-z1.h ?},{ ?z30.h-z31.h ?}'
+.*: Error: expected a list of 2 registers at operand 2 -- `fmla za.h\[w8,0,vgx2\],{ ?z0.h ?},{ ?z30.h-z31.h ?}'
+.*: Error: expected a list of 2 registers at operand 3 -- `fmla za.h\[w8,0,vgx2\],{ ?z0.h-z1.h ?},{ ?z30.h ?}'
+.*: Error: expected a list of 2 registers at operand 2 -- `fmla za.h\[w8,0,vgx2\],{ ?z0.h ?},{ ?z30.h ?}'
+.*: Error: expected a list of 2 registers at operand 2 -- `fmla za.h\[w8,0,vgx2\],{ ?z0.h ?},{ ?z30.h ?}'
+.*: Error: operand mismatch -- `fmla za.b\[w8,20,vgx2\],{ ?z0.h ?},{ ?z30.h ?}'
+.*: Info: did you mean this\?
+.*: Info: fmla za.h\[w8, 20, vgx2\], { ?z0.h ?}, { ?z30.h ?}
+.*: Error: invalid vector group size at operand 1 -- `fmla za.s\[w8,0,vgx1\],{ ?z0.h-z1.h ?},{ ?z0.h-z3.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `fmla za.h\[w14,0,vgx1\],{ ?z10.h-z1.h ?},{ ?z0.h-z3.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `fmla za.s\[w8,15,vgx1\],{ ?z0.h-z1.h ?},{ ?z0.h-z3.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `fmla za.h\[w8,0,vgx1\],{ ?z30.h-z31.h ?},{ ?z0.h-z1.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `fmla za.b\[w8,0,vgx1\],{ ?z0.h-z1.h ?},{ ?z30.h-z31.h ?}'
+.*: Error: expected a list of 4 registers at operand 2 -- `fmla za.h\[w8,0,vgx4\],{ ?z0.h ?},{ ?z30.h-z31.h ?}'
+.*: Error: expected a list of 4 registers at operand 2 -- `fmla za.h\[w8,0,vgx4\],{ ?z0.h-z1.h ?},{ ?z30.h ?}'
+.*: Error: expected a list of 4 registers at operand 2 -- `fmla za.h\[w8,0,vgx4\],{ ?z0.h ?},{ ?z30.h ?}'
+.*: Error: expected a list of 4 registers at operand 2 -- `fmla za.h\[w8,0,vgx4\],{ ?z0.h ?},{ ?z30.h ?}'
+.*: Error: operand mismatch -- `fmla za.b\[w8,20,vgx4\],{ ?z0.h ?},{ ?z30.h ?}'
+.*: Info: did you mean this\?
+.*: Info: fmla za.h\[w8, 20, vgx4\], { ?z0.h ?}, { ?z30.h ?}
+.*: Error: invalid vector group size at operand 1 -- `fmls za.s\[w8,0,vgx3\],{ ?z0.h-z1.h ?},z0.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `fmls za.h\[w14,0,vgx3\],{ ?z10.h-z1.h ?},z0.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `fmls za.h\[w8,15,vgx3\],{ ?z0.h-z1.h ?},z0.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `fmls za.d\[w8,0,vgx3\],{ ?z30.h-z31.h ?},z0.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `fmls za.h\[w8,0,vgx3\],{ ?z0.h-z1.h ?},z15.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `fmls za.h\[w8,0,vgx3\],{ ?z0.h-z1.h ?},z0.h\[7\]'
+.*: Error: expected a list of 2 registers at operand 2 -- `fmls za.h\[w8,0,vgx2\],{ ?z0.h ?},z0.h\[7\]'
+.*: Error: expected a list of 2 registers at operand 2 -- `fmls za.h\[w8,0,vgx2\],{ ?z0.h ?},z0.h'
+.*: Error: missing type suffix at operand 2 -- `fmls za.h\[w8,0,vgx2\],{ ?z0-z1 ?},z0.h\[7\]'
+.*: Error: missing type suffix at operand 2 -- `fmls za.h\[w8,0,vgx2\],{ ?z0-z1 ?}'
+.*: Error: invalid vector group size at operand 1 -- `fmls za.b\[w8,0,vgx1\],{ ?z0.h-z1.h ?},z0.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `fmls za.h\[w14,0,vgx1\],{ ?z10.h-z1.h ?},z0.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `fmls za.h\[w8,15,vgx1\],{ ?z0.h-z1.h ?},z0.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `fmls za.h\[w8,0,vgx1\],{ ?z30.h-z31.h ?},z0.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `fmls za.s\[w8,0,vgx1\],{ ?z0.h-z1.h ?},z15.h\[0\]'
+.*: Error: invalid vector group size at operand 1 -- `fmls za.h\[w8,0,vgx1\],{ ?z0.h-z1.h ?},z0.h\[7\]'
+.*: Error: expected a list of 4 registers at operand 2 -- `fmls za.h\[w8,0,vgx4\],{ ?z0.h ?},z0.h\[7\]'
+.*: Error: expected a list of 4 registers at operand 2 -- `fmls za.h\[w8,0,vgx4\],{ ?z0.h ?},z0.h'
+.*: Error: missing type suffix at operand 2 -- `fmls za.h\[w8,0,vgx4\],{ ?z0-z1 ?},z0.h\[7\]'
+.*: Error: missing type suffix at operand 2 -- `fmls za.h\[w8,0,vgx4\],{ ?z0-z1 ?}'
+.*: Error: invalid vector group size at operand 1 -- `fmls za.s\[w8,0,vgx3\],{ ?z0.h-z1.h ?},z0.h'
+.*: Error: invalid vector group size at operand 1 -- `fmls za.h\[w14,0,vgx3\],{ ?z10.h-z1.h ?},z0.h'
+.*: Error: invalid vector group size at operand 1 -- `fmls za.h\[w8,15,vgx3\],{ ?z0.h-z1.h ?},z0.h'
+.*: Error: invalid vector group size at operand 1 -- `fmls za.d\[w8,0,vgx3\],{ ?z31.h-z0.h ?},z0.h'
+.*: Error: invalid vector group size at operand 1 -- `fmls za.h\[w8,0,vgx3\],{ ?z0.h-z1.h ?},z15.h'
+.*: Error: expected a list of 2 registers at operand 2 -- `fmls za.h\[w8,0,vgx2\],{ ?z0.h ?},z15.h'
+.*: Error: operand mismatch -- `fmls za.h\[w8,0,vgx2\],{ ?z0.h-z1.h ?},z15'
+.*: Info: did you mean this\?
+.*: Info: fmls za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}, z15.h
+.*: Error: operand mismatch -- `fmls za.h\[w8,0,vgx2\],{ ?z0.h-z1.h ?},z20'
+.*: Info: did you mean this\?
+.*: Info: fmls za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}, z20.h
+.*: Error: comma expected between operands at operand 3 -- `fmls za.h\[w8,0,vgx2\],{ ?z0.h-z1.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `fmls za.h\[w8,0,vgx1\],{ ?z0.h-z1.h ?},z0.h'
+.*: Error: invalid vector group size at operand 1 -- `fmls za.s\[w14,0,vgx1\],{ ?z10.h-z1.h ?},z0.h'
+.*: Error: invalid vector group size at operand 1 -- `fmls za.h\[w8,15,vgx1\],{ ?z0.h-z1.h ?},z0.h'
+.*: Error: invalid vector group size at operand 1 -- `fmls za.h\[w8,0,vgx1\],{ ?z31.h-z2.h ?},z0.h'
+.*: Error: invalid vector group size at operand 1 -- `fmls za.b\[w8,0,vgx1\],{ ?z0.h-z1.h ?},z15.h'
+.*: Error: expected a list of 4 registers at operand 2 -- `fmls za.h\[w8,0,vgx4\],{ ?z0.h ?},z15.h'
+.*: Error: operand mismatch -- `fmls za.h\[w8,0,vgx4\],{ ?z0.h-z1.h ?},z15'
+.*: Info: did you mean this\?
+.*: Info: fmls za.h\[w8, 0, vgx4\], { ?z0.h-z1.h ?}, z15.h
+.*: Error: operand mismatch -- `fmls za.h\[w8,0,vgx4\],{ ?z0.h-z1.h ?},z20'
+.*: Info: did you mean this\?
+.*: Info: fmls za.h\[w8, 0, vgx4\], { ?z0.h-z1.h ?}, z20.h
+.*: Error: comma expected between operands at operand 3 -- `fmls za.h\[w8,0,vgx4\],{ ?z0.h-z1.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `fmls za.s\[w8,0,vgx3\],{ ?z0.h-z1.h ?},{ ?z0.h-z1.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `fmls za.h\[w14,0,vgx3\],{ ?z10.h-z1.h ?},{ ?z0.h-z1.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `fmls za.d\[w8,15,vgx3\],{ ?z0.h-z1.h ?},{ ?z0.h-z1.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `fmls za.h\[w8,0,vgx3\],{ ?z30.h-z31.h ?},{ ?z0.h-z1.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `fmls za.b\[w8,0,vgx3\],{ ?z0.h-z1.h ?},{ ?z30.h-z31.h ?}'
+.*: Error: expected a list of 2 registers at operand 2 -- `fmls za.h\[w8,0,vgx2\],{ ?z0.h ?},{ ?z30.h-z31.h ?}'
+.*: Error: expected a list of 2 registers at operand 3 -- `fmls za.h\[w8,0,vgx2\],{ ?z0.h-z1.h ?},{ ?z30.h ?}'
+.*: Error: expected a list of 2 registers at operand 2 -- `fmls za.h\[w8,0,vgx2\],{ ?z0.h ?},{ ?z30.h ?}'
+.*: Error: expected a list of 2 registers at operand 2 -- `fmls za.h\[w8,0,vgx2\],{ ?z0.h ?},{ ?z30.h ?}'
+.*: Error: operand mismatch -- `fmls za.b\[w8,20,vgx2\],{ ?z0.h ?},{ ?z30.h ?}'
+.*: Info: did you mean this\?
+.*: Info: fmls za.h\[w8, 20, vgx2\], { ?z0.h ?}, { ?z30.h ?}
+.*: Error: invalid vector group size at operand 1 -- `fmls za.s\[w8,0,vgx1\],{ ?z0.h-z1.h ?},{ ?z0.h-z3.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `fmls za.h\[w14,0,vgx1\],{ ?z10.h-z1.h ?},{ ?z0.h-z3.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `fmls za.s\[w8,15,vgx1\],{ ?z0.h-z1.h ?},{ ?z0.h-z3.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `fmls za.h\[w8,0,vgx1\],{ ?z30.h-z31.h ?},{ ?z0.h-z1.h ?}'
+.*: Error: invalid vector group size at operand 1 -- `fmls za.b\[w8,0,vgx1\],{ ?z0.h-z1.h ?},{ ?z30.h-z31.h ?}'
+.*: Error: expected a list of 4 registers at operand 2 -- `fmls za.h\[w8,0,vgx4\],{ ?z0.h ?},{ ?z30.h-z31.h ?}'
+.*: Error: expected a list of 4 registers at operand 2 -- `fmls za.h\[w8,0,vgx4\],{ ?z0.h-z1.h ?},{ ?z30.h ?}'
+.*: Error: expected a list of 4 registers at operand 2 -- `fmls za.h\[w8,0,vgx4\],{ ?z0.h ?},{ ?z30.h ?}'
+.*: Error: expected a list of 4 registers at operand 2 -- `fmls za.h\[w8,0,vgx4\],{ ?z0.h ?},{ ?z30.h ?}'
+.*: Error: operand mismatch -- `fmls za.b\[w8,20,vgx4\],{ ?z0.h ?},{ ?z30.h ?}'
+.*: Info: did you mean this\?
+.*: Info: fmls za.h\[w8, 20, vgx4\], { ?z0.h ?}, { ?z30.h ?}
diff --git a/gas/testsuite/gas/aarch64/sme-f16f16-3-bad.s b/gas/testsuite/gas/aarch64/sme-f16f16-3-bad.s
new file mode 100644
index 00000000000..40d1efa8510
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme-f16f16-3-bad.s
@@ -0,0 +1,133 @@
+/* FMLA (multiple and indexed vector). */
+fmla za.s[w8, 0, vgx3], {z0.h - z1.h}, z0.h[0]
+fmla za.h[w14, 0, vgx3], {z10.h - z1.h}, z0.h[0]
+fmla za.h[w8, 15, vgx3], {z0.h - z1.h}, z0.h[0]
+fmla za.d[w8, 0, vgx3], {z30.h - z31.h}, z0.h[0]
+fmla za.h[w8, 0, vgx3], {z0.h - z1.h}, z15.h[0]
+fmla za.h[w8, 0, vgx3], {z0.h - z1.h}, z0.h[7]
+fmla za.h[w8, 0, vgx2], {z0.h}, z0.h[7]
+fmla za.h[w8, 0, vgx2], {z0.h}, z0.h
+fmla za.h[w8, 0, vgx2], {z0 - z1}, z0.h[7]
+fmla za.h[w8, 0, vgx2], {z0 - z1}
+
+fmla za.b[w8, 0, vgx1], {z0.h - z1.h}, z0.h[0]
+fmla za.h[w14, 0, vgx1], {z10.h - z1.h}, z0.h[0]
+fmla za.h[w8, 15, vgx1], {z0.h - z1.h}, z0.h[0]
+fmla za.h[w8, 0, vgx1], {z30.h - z31.h}, z0.h[0]
+fmla za.s[w8, 0, vgx1], {z0.h - z1.h}, z15.h[0]
+fmla za.h[w8, 0, vgx1], {z0.h - z1.h}, z0.h[7]
+fmla za.h[w8, 0, vgx4], {z0.h}, z0.h[7]
+fmla za.h[w8, 0, vgx4], {z0.h}, z0.h
+fmla za.h[w8, 0, vgx4], {z0 - z1}, z0.h[7]
+fmla za.h[w8, 0, vgx4], {z0 - z1}
+
+/* FMLA (multiple and single vector). */
+fmla za.s[w8, 0, vgx3], {z0.h - z1.h}, z0.h
+fmla za.h[w14, 0, vgx3], {z10.h - z1.h}, z0.h
+fmla za.h[w8, 15, vgx3], {z0.h - z1.h}, z0.h
+fmla za.d[w8, 0, vgx3], {z31.h - z0.h}, z0.h
+fmla za.h[w8, 0, vgx3], {z0.h - z1.h}, z15.h
+fmla za.h[w8, 0, vgx2], {z0.h}, z15.h
+fmla za.h[w8, 0, vgx2], {z0.h -z1.h}, z15
+fmla za.h[w8, 0, vgx2], {z0.h -z1.h}, z20
+fmla za.h[w8, 0, vgx2], {z0.h -z1.h}
+
+fmla za.h[w8, 0, vgx1], {z0.h - z1.h}, z0.h
+fmla za.s[w14, 0, vgx1], {z10.h - z1.h}, z0.h
+fmla za.h[w8, 15, vgx1], {z0.h - z1.h}, z0.h
+fmla za.h[w8, 0, vgx1], {z31.h - z2.h}, z0.h
+fmla za.b[w8, 0, vgx1], {z0.h - z1.h}, z15.h
+fmla za.h[w8, 0, vgx4], {z0.h}, z15.h
+fmla za.h[w8, 0, vgx4], {z0.h -z1.h}, z15
+fmla za.h[w8, 0, vgx4], {z0.h -z1.h}, z20
+fmla za.h[w8, 0, vgx4], {z0.h -z1.h}
+
+/* FMLA (multiple vectors). */
+fmla za.s[w8, 0, vgx3], {z0.h - z1.h}, {z0.h - z1.h}
+fmla za.h[w14, 0, vgx3], {z10.h - z1.h}, {z0.h - z1.h}
+fmla za.d[w8, 15, vgx3], {z0.h - z1.h}, {z0.h - z1.h}
+fmla za.h[w8, 0, vgx3], {z30.h - z31.h}, {z0.h - z1.h}
+fmla za.b[w8, 0, vgx3], {z0.h - z1.h}, {z30.h - z31.h}
+fmla za.h[w8, 0, vgx2], {z0.h}, {z30.h - z31.h}
+fmla za.h[w8, 0, vgx2], {z0.h - z1.h}, {z30.h}
+fmla za.h[w8, 0, vgx2], {z0.h}, {z30.h}
+fmla za.h[w8, 0, vgx2], {z0.h}, {z30.h}
+fmla za.b[w8, 20, vgx2], {z0.h}, {z30.h}
+
+fmla za.s[w8, 0, vgx1], {z0.h - z1.h}, {z0.h - z3.h}
+fmla za.h[w14, 0, vgx1], {z10.h - z1.h}, {z0.h - z3.h}
+fmla za.s[w8, 15, vgx1], {z0.h - z1.h}, {z0.h - z3.h}
+fmla za.h[w8, 0, vgx1], {z30.h - z31.h}, {z0.h - z1.h}
+fmla za.b[w8, 0, vgx1], {z0.h - z1.h}, {z30.h - z31.h}
+fmla za.h[w8, 0, vgx4], {z0.h}, {z30.h - z31.h}
+fmla za.h[w8, 0, vgx4], {z0.h - z1.h}, {z30.h}
+fmla za.h[w8, 0, vgx4], {z0.h}, {z30.h}
+fmla za.h[w8, 0, vgx4], {z0.h}, {z30.h}
+fmla za.b[w8, 20, vgx4], {z0.h}, {z30.h}
+
+/* FMLS (multiple and indexed vector). */
+fmls za.s[w8, 0, vgx3], {z0.h - z1.h}, z0.h[0]
+fmls za.h[w14, 0, vgx3], {z10.h - z1.h}, z0.h[0]
+fmls za.h[w8, 15, vgx3], {z0.h - z1.h}, z0.h[0]
+fmls za.d[w8, 0, vgx3], {z30.h - z31.h}, z0.h[0]
+fmls za.h[w8, 0, vgx3], {z0.h - z1.h}, z15.h[0]
+fmls za.h[w8, 0, vgx3], {z0.h - z1.h}, z0.h[7]
+fmls za.h[w8, 0, vgx2], {z0.h}, z0.h[7]
+fmls za.h[w8, 0, vgx2], {z0.h}, z0.h
+fmls za.h[w8, 0, vgx2], {z0 - z1}, z0.h[7]
+fmls za.h[w8, 0, vgx2], {z0 - z1}
+
+fmls za.b[w8, 0, vgx1], {z0.h - z1.h}, z0.h[0]
+fmls za.h[w14, 0, vgx1], {z10.h - z1.h}, z0.h[0]
+fmls za.h[w8, 15, vgx1], {z0.h - z1.h}, z0.h[0]
+fmls za.h[w8, 0, vgx1], {z30.h - z31.h}, z0.h[0]
+fmls za.s[w8, 0, vgx1], {z0.h - z1.h}, z15.h[0]
+fmls za.h[w8, 0, vgx1], {z0.h - z1.h}, z0.h[7]
+fmls za.h[w8, 0, vgx4], {z0.h}, z0.h[7]
+fmls za.h[w8, 0, vgx4], {z0.h}, z0.h
+fmls za.h[w8, 0, vgx4], {z0 - z1}, z0.h[7]
+fmls za.h[w8, 0, vgx4], {z0 - z1}
+
+/* FMLS (multiple and single vector). */
+fmls za.s[w8, 0, vgx3], {z0.h - z1.h}, z0.h
+fmls za.h[w14, 0, vgx3], {z10.h - z1.h}, z0.h
+fmls za.h[w8, 15, vgx3], {z0.h - z1.h}, z0.h
+fmls za.d[w8, 0, vgx3], {z31.h - z0.h}, z0.h
+fmls za.h[w8, 0, vgx3], {z0.h - z1.h}, z15.h
+fmls za.h[w8, 0, vgx2], {z0.h}, z15.h
+fmls za.h[w8, 0, vgx2], {z0.h -z1.h}, z15
+fmls za.h[w8, 0, vgx2], {z0.h -z1.h}, z20
+fmls za.h[w8, 0, vgx2], {z0.h -z1.h}
+
+fmls za.h[w8, 0, vgx1], {z0.h - z1.h}, z0.h
+fmls za.s[w14, 0, vgx1], {z10.h - z1.h}, z0.h
+fmls za.h[w8, 15, vgx1], {z0.h - z1.h}, z0.h
+fmls za.h[w8, 0, vgx1], {z31.h - z2.h}, z0.h
+fmls za.b[w8, 0, vgx1], {z0.h - z1.h}, z15.h
+fmls za.h[w8, 0, vgx4], {z0.h}, z15.h
+fmls za.h[w8, 0, vgx4], {z0.h -z1.h}, z15
+fmls za.h[w8, 0, vgx4], {z0.h -z1.h}, z20
+fmls za.h[w8, 0, vgx4], {z0.h -z1.h}
+
+/* FMLS (multiple vectors). */
+fmls za.s[w8, 0, vgx3], {z0.h - z1.h}, {z0.h - z1.h}
+fmls za.h[w14, 0, vgx3], {z10.h - z1.h}, {z0.h - z1.h}
+fmls za.d[w8, 15, vgx3], {z0.h - z1.h}, {z0.h - z1.h}
+fmls za.h[w8, 0, vgx3], {z30.h - z31.h}, {z0.h - z1.h}
+fmls za.b[w8, 0, vgx3], {z0.h - z1.h}, {z30.h - z31.h}
+fmls za.h[w8, 0, vgx2], {z0.h}, {z30.h - z31.h}
+fmls za.h[w8, 0, vgx2], {z0.h - z1.h}, {z30.h}
+fmls za.h[w8, 0, vgx2], {z0.h}, {z30.h}
+fmls za.h[w8, 0, vgx2], {z0.h}, {z30.h}
+fmls za.b[w8, 20, vgx2], {z0.h}, {z30.h}
+
+fmls za.s[w8, 0, vgx1], {z0.h - z1.h}, {z0.h - z3.h}
+fmls za.h[w14, 0, vgx1], {z10.h - z1.h}, {z0.h - z3.h}
+fmls za.s[w8, 15, vgx1], {z0.h - z1.h}, {z0.h - z3.h}
+fmls za.h[w8, 0, vgx1], {z30.h - z31.h}, {z0.h - z1.h}
+fmls za.b[w8, 0, vgx1], {z0.h - z1.h}, {z30.h - z31.h}
+fmls za.h[w8, 0, vgx4], {z0.h}, {z30.h - z31.h}
+fmls za.h[w8, 0, vgx4], {z0.h - z1.h}, {z30.h}
+fmls za.h[w8, 0, vgx4], {z0.h}, {z30.h}
+fmls za.h[w8, 0, vgx4], {z0.h}, {z30.h}
+fmls za.b[w8, 20, vgx4], {z0.h}, {z30.h}
diff --git a/gas/testsuite/gas/aarch64/sme-f16f16-3.d b/gas/testsuite/gas/aarch64/sme-f16f16-3.d
new file mode 100644
index 00000000000..424e9c34883
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme-f16f16-3.d
@@ -0,0 +1,102 @@
+#name: Test of FEAT_SME_F16F16 fmla and fmls instructions.
+#as: -march=armv8-a+sme-f16f16
+#objdump: -dr
+
+[^:]+: file format .*
+
+
+[^:]+:
+
+[^:]+:
+.*: c1101000 fmla za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}, z0.h\[0\]
+.*: c1107000 fmla za.h\[w11, 0, vgx2\], { ?z0.h-z1.h ?}, z0.h\[0\]
+.*: c1101007 fmla za.h\[w8, 7, vgx2\], { ?z0.h-z1.h ?}, z0.h\[0\]
+.*: c11013c0 fmla za.h\[w8, 0, vgx2\], { ?z30.h-z31.h ?}, z0.h\[0\]
+.*: c11f1000 fmla za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}, z15.h\[0\]
+.*: c1101c08 fmla za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}, z0.h\[7\]
+.*: c11f7fcf fmla za.h\[w11, 7, vgx2\], { ?z30.h-z31.h ?}, z15.h\[7\]
+.*: c11f37cf fmla za.h\[w9, 7, vgx2\], { ?z30.h-z31.h ?}, z15.h\[3\]
+.*: c1101c0b fmla za.h\[w8, 3, vgx2\], { ?z0.h-z1.h ?}, z0.h\[7\]
+.*: c1109000 fmla za.h\[w8, 0, vgx4\], { ?z0.h-z3.h ?}, z0.h\[0\]
+.*: c110f000 fmla za.h\[w11, 0, vgx4\], { ?z0.h-z3.h ?}, z0.h\[0\]
+.*: c1109007 fmla za.h\[w8, 7, vgx4\], { ?z0.h-z3.h ?}, z0.h\[0\]
+.*: c1109380 fmla za.h\[w8, 0, vgx4\], { ?z28.h-z31.h ?}, z0.h\[0\]
+.*: c11f9000 fmla za.h\[w8, 0, vgx4\], { ?z0.h-z3.h ?}, z15.h\[0\]
+.*: c1109c08 fmla za.h\[w8, 0, vgx4\], { ?z0.h-z3.h ?}, z0.h\[7\]
+.*: c11fff8f fmla za.h\[w11, 7, vgx4\], { ?z28.h-z31.h ?}, z15.h\[7\]
+.*: c11fb78f fmla za.h\[w9, 7, vgx4\], { ?z28.h-z31.h ?}, z15.h\[3\]
+.*: c1109c0b fmla za.h\[w8, 3, vgx4\], { ?z0.h-z3.h ?}, z0.h\[7\]
+.*: c1201c00 fmla za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}, z0.h
+.*: c1207c00 fmla za.h\[w11, 0, vgx2\], { ?z0.h-z1.h ?}, z0.h
+.*: c1201c07 fmla za.h\[w8, 7, vgx2\], { ?z0.h-z1.h ?}, z0.h
+.*: c1201fe0 fmla za.h\[w8, 0, vgx2\], { ?z31.h-z0.h ?}, z0.h
+.*: c12f1c00 fmla za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}, z15.h
+.*: c12f7fc7 fmla za.h\[w11, 7, vgx2\], { ?z30.h-z31.h ?}, z15.h
+.*: c12f1c03 fmla za.h\[w8, 3, vgx2\], { ?z0.h-z1.h ?}, z15.h
+.*: c1301c00 fmla za.h\[w8, 0, vgx4\], { ?z0.h-z3.h ?}, z0.h
+.*: c1307c00 fmla za.h\[w11, 0, vgx4\], { ?z0.h-z3.h ?}, z0.h
+.*: c1301c07 fmla za.h\[w8, 7, vgx4\], { ?z0.h-z3.h ?}, z0.h
+.*: c1301fe0 fmla za.h\[w8, 0, vgx4\], { ?z31.h-z2.h ?}, z0.h
+.*: c13f1c00 fmla za.h\[w8, 0, vgx4\], { ?z0.h-z3.h ?}, z15.h
+.*: c13f7f87 fmla za.h\[w11, 7, vgx4\], { ?z28.h-z31.h ?}, z15.h
+.*: c13f1c03 fmla za.h\[w8, 3, vgx4\], { ?z0.h-z3.h ?}, z15.h
+.*: c1a01008 fmla za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}, { ?z0.h-z1.h ?}
+.*: c1a07008 fmla za.h\[w11, 0, vgx2\], { ?z0.h-z1.h ?}, { ?z0.h-z1.h ?}
+.*: c1a0100f fmla za.h\[w8, 7, vgx2\], { ?z0.h-z1.h ?}, { ?z0.h-z1.h ?}
+.*: c1a013c8 fmla za.h\[w8, 0, vgx2\], { ?z30.h-z31.h ?}, { ?z0.h-z1.h ?}
+.*: c1be1008 fmla za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}, { ?z30.h-z31.h ?}
+.*: c1be73cf fmla za.h\[w11, 7, vgx2\], { ?z30.h-z31.h ?}, { ?z30.h-z31.h ?}
+.*: c1be100b fmla za.h\[w8, 3, vgx2\], { ?z0.h-z1.h ?}, { ?z30.h-z31.h ?}
+.*: c1a11008 fmla za.h\[w8, 0, vgx4\], { ?z0.h-z3.h ?}, { ?z0.h-z3.h ?}
+.*: c1a17008 fmla za.h\[w11, 0, vgx4\], { ?z0.h-z3.h ?}, { ?z0.h-z3.h ?}
+.*: c1a1100f fmla za.h\[w8, 7, vgx4\], { ?z0.h-z3.h ?}, { ?z0.h-z3.h ?}
+.*: c1a11388 fmla za.h\[w8, 0, vgx4\], { ?z28.h-z31.h ?}, { ?z0.h-z3.h ?}
+.*: c1bd1008 fmla za.h\[w8, 0, vgx4\], { ?z0.h-z3.h ?}, { ?z28.h-z31.h ?}
+.*: c1bd738f fmla za.h\[w11, 7, vgx4\], { ?z28.h-z31.h ?}, { ?z28.h-z31.h ?}
+.*: c1bd100b fmla za.h\[w8, 3, vgx4\], { ?z0.h-z3.h ?}, { ?z28.h-z31.h ?}
+.*: c1101010 fmls za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}, z0.h\[0\]
+.*: c1107010 fmls za.h\[w11, 0, vgx2\], { ?z0.h-z1.h ?}, z0.h\[0\]
+.*: c1101017 fmls za.h\[w8, 7, vgx2\], { ?z0.h-z1.h ?}, z0.h\[0\]
+.*: c11013d0 fmls za.h\[w8, 0, vgx2\], { ?z30.h-z31.h ?}, z0.h\[0\]
+.*: c11f1010 fmls za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}, z15.h\[0\]
+.*: c1101c18 fmls za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}, z0.h\[7\]
+.*: c11f7fdf fmls za.h\[w11, 7, vgx2\], { ?z30.h-z31.h ?}, z15.h\[7\]
+.*: c11f37df fmls za.h\[w9, 7, vgx2\], { ?z30.h-z31.h ?}, z15.h\[3\]
+.*: c1101c1b fmls za.h\[w8, 3, vgx2\], { ?z0.h-z1.h ?}, z0.h\[7\]
+.*: c1109010 fmls za.h\[w8, 0, vgx4\], { ?z0.h-z3.h ?}, z0.h\[0\]
+.*: c110f010 fmls za.h\[w11, 0, vgx4\], { ?z0.h-z3.h ?}, z0.h\[0\]
+.*: c1109017 fmls za.h\[w8, 7, vgx4\], { ?z0.h-z3.h ?}, z0.h\[0\]
+.*: c1109390 fmls za.h\[w8, 0, vgx4\], { ?z28.h-z31.h ?}, z0.h\[0\]
+.*: c11f9010 fmls za.h\[w8, 0, vgx4\], { ?z0.h-z3.h ?}, z15.h\[0\]
+.*: c1109c18 fmls za.h\[w8, 0, vgx4\], { ?z0.h-z3.h ?}, z0.h\[7\]
+.*: c11fff9f fmls za.h\[w11, 7, vgx4\], { ?z28.h-z31.h ?}, z15.h\[7\]
+.*: c11fb79f fmls za.h\[w9, 7, vgx4\], { ?z28.h-z31.h ?}, z15.h\[3\]
+.*: c1109c1b fmls za.h\[w8, 3, vgx4\], { ?z0.h-z3.h ?}, z0.h\[7\]
+.*: c1201c08 fmls za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}, z0.h
+.*: c1207c08 fmls za.h\[w11, 0, vgx2\], { ?z0.h-z1.h ?}, z0.h
+.*: c1201c0f fmls za.h\[w8, 7, vgx2\], { ?z0.h-z1.h ?}, z0.h
+.*: c1201fe8 fmls za.h\[w8, 0, vgx2\], { ?z31.h-z0.h ?}, z0.h
+.*: c12f1c08 fmls za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}, z15.h
+.*: c12f7fcf fmls za.h\[w11, 7, vgx2\], { ?z30.h-z31.h ?}, z15.h
+.*: c12f1c0b fmls za.h\[w8, 3, vgx2\], { ?z0.h-z1.h ?}, z15.h
+.*: c1301c08 fmls za.h\[w8, 0, vgx4\], { ?z0.h-z3.h ?}, z0.h
+.*: c1307c08 fmls za.h\[w11, 0, vgx4\], { ?z0.h-z3.h ?}, z0.h
+.*: c1301c0f fmls za.h\[w8, 7, vgx4\], { ?z0.h-z3.h ?}, z0.h
+.*: c1301fe8 fmls za.h\[w8, 0, vgx4\], { ?z31.h-z2.h ?}, z0.h
+.*: c13f1c08 fmls za.h\[w8, 0, vgx4\], { ?z0.h-z3.h ?}, z15.h
+.*: c13f7f8f fmls za.h\[w11, 7, vgx4\], { ?z28.h-z31.h ?}, z15.h
+.*: c13f1c0b fmls za.h\[w8, 3, vgx4\], { ?z0.h-z3.h ?}, z15.h
+.*: c1a01018 fmls za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}, { ?z0.h-z1.h ?}
+.*: c1a07018 fmls za.h\[w11, 0, vgx2\], { ?z0.h-z1.h ?}, { ?z0.h-z1.h ?}
+.*: c1a0101f fmls za.h\[w8, 7, vgx2\], { ?z0.h-z1.h ?}, { ?z0.h-z1.h ?}
+.*: c1a013d8 fmls za.h\[w8, 0, vgx2\], { ?z30.h-z31.h ?}, { ?z0.h-z1.h ?}
+.*: c1be1018 fmls za.h\[w8, 0, vgx2\], { ?z0.h-z1.h ?}, { ?z30.h-z31.h ?}
+.*: c1be73df fmls za.h\[w11, 7, vgx2\], { ?z30.h-z31.h ?}, { ?z30.h-z31.h ?}
+.*: c1be101b fmls za.h\[w8, 3, vgx2\], { ?z0.h-z1.h ?}, { ?z30.h-z31.h ?}
+.*: c1a11018 fmls za.h\[w8, 0, vgx4\], { ?z0.h-z3.h ?}, { ?z0.h-z3.h ?}
+.*: c1a17018 fmls za.h\[w11, 0, vgx4\], { ?z0.h-z3.h ?}, { ?z0.h-z3.h ?}
+.*: c1a1101f fmls za.h\[w8, 7, vgx4\], { ?z0.h-z3.h ?}, { ?z0.h-z3.h ?}
+.*: c1a11398 fmls za.h\[w8, 0, vgx4\], { ?z28.h-z31.h ?}, { ?z0.h-z3.h ?}
+.*: c1bd1018 fmls za.h\[w8, 0, vgx4\], { ?z0.h-z3.h ?}, { ?z28.h-z31.h ?}
+.*: c1bd739f fmls za.h\[w11, 7, vgx4\], { ?z28.h-z31.h ?}, { ?z28.h-z31.h ?}
+.*: c1bd101b fmls za.h\[w8, 3, vgx4\], { ?z0.h-z3.h ?}, { ?z28.h-z31.h ?}
diff --git a/gas/testsuite/gas/aarch64/sme-f16f16-3.s b/gas/testsuite/gas/aarch64/sme-f16f16-3.s
new file mode 100644
index 00000000000..215fe5d691b
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme-f16f16-3.s
@@ -0,0 +1,109 @@
+/* FMLA (multiple and indexed vector). */
+fmla za.h[w8, 0, vgx2], {z0.h - z1.h}, z0.h[0]
+fmla za.h[w11, 0, vgx2], {z0.h - z1.h}, z0.h[0]
+fmla za.h[w8, 7, vgx2], {z0.h - z1.h}, z0.h[0]
+fmla za.h[w8, 0, vgx2], {z30.h - z31.h}, z0.h[0]
+fmla za.h[w8, 0, vgx2], {z0.h - z1.h}, z15.h[0]
+fmla za.h[w8, 0, vgx2], {z0.h - z1.h}, z0.h[7]
+fmla za.h[w11, 7, vgx2], {z30.h - z31.h}, z15.h[7]
+fmla za.h[w9, 7, vgx2], {z30.h - z31.h}, z15.h[3]
+fmla za.h[w8, 3], {z0.h - z1.h}, z0.h[7]
+
+fmla za.h[w8, 0, vgx4], {z0.h - z3.h}, z0.h[0]
+fmla za.h[w11, 0, vgx4], {z0.h - z3.h}, z0.h[0]
+fmla za.h[w8, 7, vgx4], {z0.h - z3.h}, z0.h[0]
+fmla za.h[w8, 0, vgx4], {z28.h - z31.h}, z0.h[0]
+fmla za.h[w8, 0, vgx4], {z0.h - z3.h}, z15.h[0]
+fmla za.h[w8, 0, vgx4], {z0.h - z3.h}, z0.h[7]
+fmla za.h[w11, 7, vgx4], {z28.h - z31.h}, z15.h[7]
+fmla za.h[w9, 7, vgx4], {z28.h - z31.h}, z15.h[3]
+fmla za.h[w8, 3], {z0.h - z3.h}, z0.h[7]
+
+/* FMLA (multiple and single vector). */
+fmla za.h[w8, 0, vgx2], {z0.h - z1.h}, z0.h
+fmla za.h[w11, 0, vgx2], {z0.h - z1.h}, z0.h
+fmla za.h[w8, 7, vgx2], {z0.h - z1.h}, z0.h
+fmla za.h[w8, 0, vgx2], {z31.h - z0.h}, z0.h
+fmla za.h[w8, 0, vgx2], {z0.h - z1.h}, z15.h
+fmla za.h[w11, 7, vgx2], {z30.h - z31.h}, z15.h
+fmla za.h[w8, 3], {z0.h - z1.h}, z15.h
+
+fmla za.h[w8, 0, vgx4], {z0.h - z3.h}, z0.h
+fmla za.h[w11, 0, vgx4], {z0.h - z3.h}, z0.h
+fmla za.h[w8, 7, vgx4], {z0.h - z3.h}, z0.h
+fmla za.h[w8, 0, vgx4], {z31.h - z2.h}, z0.h
+fmla za.h[w8, 0, vgx4], {z0.h - z3.h}, z15.h
+fmla za.h[w11, 7, vgx4], {z28.h - z31.h}, z15.h
+fmla za.h[w8, 3], {z0.h - z3.h}, z15.h
+
+/* FMLA (multiple vectors). */
+fmla za.h[w8, 0, vgx2], {z0.h - z1.h}, {z0.h - z1.h}
+fmla za.h[w11, 0, vgx2], {z0.h - z1.h}, {z0.h - z1.h}
+fmla za.h[w8, 7, vgx2], {z0.h - z1.h}, {z0.h - z1.h}
+fmla za.h[w8, 0, vgx2], {z30.h - z31.h}, {z0.h - z1.h}
+fmla za.h[w8, 0, vgx2], {z0.h - z1.h}, {z30.h - z31.h}
+fmla za.h[w11, 7, vgx2], {z30.h - z31.h}, {z30.h - z31.h}
+fmla za.h[w8, 3], {z0.h - z1.h}, {z30.h - z31.h}
+
+fmla za.h[w8, 0, vgx4], {z0.h - z3.h}, {z0.h - z3.h}
+fmla za.h[w11, 0, vgx4], {z0.h - z3.h}, {z0.h - z3.h}
+fmla za.h[w8, 7, vgx4], {z0.h - z3.h}, {z0.h - z3.h}
+fmla za.h[w8, 0, vgx4], {z28.h - z31.h}, {z0.h - z3.h}
+fmla za.h[w8, 0, vgx4], {z0.h - z3.h}, {z28.h - z31.h}
+fmla za.h[w11, 7, vgx4], {z28.h - z31.h}, {z28.h - z31.h}
+fmla za.h[w8, 3], {z0.h - z3.h}, {z28.h - z31.h}
+
+/* FMLS (multiple and indexed vector). */
+fmls za.h[w8, 0, vgx2], {z0.h - z1.h}, z0.h[0]
+fmls za.h[w11, 0, vgx2], {z0.h - z1.h}, z0.h[0]
+fmls za.h[w8, 7, vgx2], {z0.h - z1.h}, z0.h[0]
+fmls za.h[w8, 0, vgx2], {z30.h - z31.h}, z0.h[0]
+fmls za.h[w8, 0, vgx2], {z0.h - z1.h}, z15.h[0]
+fmls za.h[w8, 0, vgx2], {z0.h - z1.h}, z0.h[7]
+fmls za.h[w11, 7, vgx2], {z30.h - z31.h}, z15.h[7]
+fmls za.h[w9, 7, vgx2], {z30.h - z31.h}, z15.h[3]
+fmls za.h[w8, 3], {z0.h - z1.h}, z0.h[7]
+
+fmls za.h[w8, 0, vgx4], {z0.h - z3.h}, z0.h[0]
+fmls za.h[w11, 0, vgx4], {z0.h - z3.h}, z0.h[0]
+fmls za.h[w8, 7, vgx4], {z0.h - z3.h}, z0.h[0]
+fmls za.h[w8, 0, vgx4], {z28.h - z31.h}, z0.h[0]
+fmls za.h[w8, 0, vgx4], {z0.h - z3.h}, z15.h[0]
+fmls za.h[w8, 0, vgx4], {z0.h - z3.h}, z0.h[7]
+fmls za.h[w11, 7, vgx4], {z28.h - z31.h}, z15.h[7]
+fmls za.h[w9, 7, vgx4], {z28.h - z31.h}, z15.h[3]
+fmls za.h[w8, 3], {z0.h - z3.h}, z0.h[7]
+
+/* FMLS (multiple and single vector). */
+fmls za.h[w8, 0, vgx2], {z0.h - z1.h}, z0.h
+fmls za.h[w11, 0, vgx2], {z0.h - z1.h}, z0.h
+fmls za.h[w8, 7, vgx2], {z0.h - z1.h}, z0.h
+fmls za.h[w8, 0, vgx2], {z31.h - z0.h}, z0.h
+fmls za.h[w8, 0, vgx2], {z0.h - z1.h}, z15.h
+fmls za.h[w11, 7, vgx2], {z30.h - z31.h}, z15.h
+fmls za.h[w8, 3], {z0.h - z1.h}, z15.h
+
+fmls za.h[w8, 0, vgx4], {z0.h - z3.h}, z0.h
+fmls za.h[w11, 0, vgx4], {z0.h - z3.h}, z0.h
+fmls za.h[w8, 7, vgx4], {z0.h - z3.h}, z0.h
+fmls za.h[w8, 0, vgx4], {z31.h - z2.h}, z0.h
+fmls za.h[w8, 0, vgx4], {z0.h - z3.h}, z15.h
+fmls za.h[w11, 7, vgx4], {z28.h - z31.h}, z15.h
+fmls za.h[w8, 3], {z0.h - z3.h}, z15.h
+
+/* FMLS (multiple vectors). */
+fmls za.h[w8, 0, vgx2], {z0.h - z1.h}, {z0.h - z1.h}
+fmls za.h[w11, 0, vgx2], {z0.h - z1.h}, {z0.h - z1.h}
+fmls za.h[w8, 7, vgx2], {z0.h - z1.h}, {z0.h - z1.h}
+fmls za.h[w8, 0, vgx2], {z30.h - z31.h}, {z0.h - z1.h}
+fmls za.h[w8, 0, vgx2], {z0.h - z1.h}, {z30.h - z31.h}
+fmls za.h[w11, 7, vgx2], {z30.h - z31.h}, {z30.h - z31.h}
+fmls za.h[w8, 3], {z0.h - z1.h}, {z30.h - z31.h}
+
+fmls za.h[w8, 0, vgx4], {z0.h - z3.h}, {z0.h - z3.h}
+fmls za.h[w11, 0, vgx4], {z0.h - z3.h}, {z0.h - z3.h}
+fmls za.h[w8, 7, vgx4], {z0.h - z3.h}, {z0.h - z3.h}
+fmls za.h[w8, 0, vgx4], {z28.h - z31.h}, {z0.h - z3.h}
+fmls za.h[w8, 0, vgx4], {z0.h - z3.h}, {z28.h - z31.h}
+fmls za.h[w11, 7, vgx4], {z28.h - z31.h}, {z28.h - z31.h}
+fmls za.h[w8, 3], {z0.h - z3.h}, {z28.h - z31.h}
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index 5a26e805a54..ad4e8a9624d 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -271,7 +271,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000x000101x00xxxxxxxxxxxxxx
luti4. */
- return 3430;
+ return 3442;
}
else
{
@@ -310,7 +310,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx01101x00xxxxxxxxxxxxxx
luti4. */
- return 3431;
+ return 3443;
}
else
{
@@ -542,7 +542,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000010011x1xxxx00xxxxxxxxxx
movt. */
- return 3432;
+ return 3444;
}
}
else
@@ -1366,7 +1366,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000000101xxxxxxxxxxxxxxxx00xxx
fmopa. */
- return 3498;
+ return 3510;
}
else
{
@@ -1374,7 +1374,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000000101xxxxxxxxxxxxxxxx01xxx
fmopa. */
- return 3497;
+ return 3509;
}
}
else
@@ -1722,7 +1722,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010001xxxx1xx0xxxxx1000xxx
fmlall. */
- return 3491;
+ return 3503;
}
}
}
@@ -1748,11 +1748,33 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx0000010001xxxxxxx1xxxxxx00xxxx
- fdot. */
- return 3476;
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000010001xxxx0xx1xxxxxx00xxxx
+ fmla. */
+ return 3327;
+ }
+ else
+ {
+ if (((word >> 6) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000010001xxxx1xx1xxxxx000xxxx
+ fmla. */
+ return 3328;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000010001xxxx1xx1xxxxx100xxxx
+ fdot. */
+ return 3488;
+ }
+ }
}
}
else
@@ -1778,11 +1800,11 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- if (((word >> 3) & 0x1) == 0)
+ if (((word >> 20) & 0x1) == 0)
{
- if (((word >> 20) & 0x1) == 0)
+ if (((word >> 2) & 0x1) == 0)
{
- if (((word >> 2) & 0x1) == 0)
+ if (((word >> 3) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
@@ -1794,30 +1816,63 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- xx0000010000xxxxxxxxxxxxxxx101xx
- sumlall. */
- return 2848;
+ xx0000010000xxxxxxxxxxxxxxx110xx
+ umlsll. */
+ return 2906;
}
}
else
{
- if (((word >> 5) & 0x1) == 0)
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000010000xxxxxxxxxxxxxxx1x1xx
+ sumlall. */
+ return 2848;
+ }
+ }
+ else
+ {
+ if (((word >> 5) & 0x1) == 0)
+ {
+ if (((word >> 12) & 0x1) == 0)
{
- if (((word >> 15) & 0x1) == 0)
+ if (((word >> 3) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx0000010001xxxx0xxxxxxxxx010xxx
- umlall. */
- return 2891;
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000010001xxxx0xx0xxxxxx010xxx
+ umlall. */
+ return 2891;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000010001xxxx1xx0xxxxxx010xxx
+ umlall. */
+ return 2892;
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx0000010001xxxx1xxxxxxxxx010xxx
- umlall. */
- return 2892;
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000010001xxxx0xx0xxxxxx011xxx
+ umlsll. */
+ return 2907;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx0000010001xxxx1xx0xxxxxx011xxx
+ umlsll. */
+ return 2908;
+ }
}
}
else
@@ -1826,48 +1881,37 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- xx0000010001xxxx0xxxxxxxxx110xxx
- sumlall. */
- return 2849;
+ xx0000010001xxxx0xx1xxxxxx01xxxx
+ fmls. */
+ return 3333;
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- xx0000010001xxxx1xxxxxxxxx110xxx
- sumlall. */
- return 2850;
+ xx0000010001xxxx1xx1xxxxxx01xxxx
+ fmls. */
+ return 3334;
}
}
}
- }
- else
- {
- if (((word >> 20) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx0000010000xxxxxxxxxxxxxxx11xxx
- umlsll. */
- return 2906;
- }
else
{
if (((word >> 15) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- xx0000010001xxxx0xxxxxxxxxx11xxx
- umlsll. */
- return 2907;
+ xx0000010001xxxx0xxxxxxxxx11xxxx
+ sumlall. */
+ return 2849;
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- xx0000010001xxxx1xxxxxxxxxx11xxx
- umlsll. */
- return 2908;
+ xx0000010001xxxx1xxxxxxxxx11xxxx
+ sumlall. */
+ return 2850;
}
}
}
@@ -2135,7 +2179,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011001xxxxxxx0xxxxxx100xxx
fmlall. */
- return 3490;
+ return 3502;
}
}
}
@@ -2240,7 +2284,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011001xxxxxxx1xxxxxx10xxxx
fmlal. */
- return 3483;
+ return 3495;
}
}
}
@@ -2424,7 +2468,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011001xxxxxxx1xxxxxx11xxxx
fmlal. */
- return 3482;
+ return 3494;
}
}
}
@@ -2466,7 +2510,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010100xxxxxxxxxxxxxxxx0xxx
fmlall. */
- return 3489;
+ return 3501;
}
else
{
@@ -2834,7 +2878,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx000010101xxxx0xx0xxxxxx111xxx
fdot. */
- return 3469;
+ return 3481;
}
else
{
@@ -2903,7 +2947,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx000010101xxxx1xx0xxxxxx001xxx
fdot. */
- return 3470;
+ return 3482;
}
else
{
@@ -2982,7 +3026,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011100xxxxxxx0xxxxxxx0xxxx
fmlal. */
- return 3481;
+ return 3493;
}
else
{
@@ -3037,7 +3081,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011101xxxx0xx01xxxxx00xxxx
fvdotb. */
- return 3500;
+ return 3512;
}
else
{
@@ -3055,7 +3099,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011101xxxxxxx0xxxxxx10xxxx
fdot. */
- return 3475;
+ return 3487;
}
}
}
@@ -3129,7 +3173,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011101xxxxxxx1xxxxxx10xxxx
fvdot. */
- return 3499;
+ return 3511;
}
}
}
@@ -3209,7 +3253,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000001110xxxxx0xx01xxxxxx1xxxx
fvdott. */
- return 3501;
+ return 3513;
}
else
{
@@ -3386,7 +3430,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx00xx000xxxx10000x
fmlall. */
- return 3495;
+ return 3507;
}
else
{
@@ -3394,7 +3438,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx10xx000xxxx10000x
fmlall. */
- return 3496;
+ return 3508;
}
}
}
@@ -3449,7 +3493,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx10xxxx0xx000xxxxx00x1x
fmlall. */
- return 3493;
+ return 3505;
}
else
{
@@ -3457,7 +3501,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx000xxxxx00x1x
fmlall. */
- return 3494;
+ return 3506;
}
}
}
@@ -3511,7 +3555,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx00xx100xxxx100xxx
fdot. */
- return 3479;
+ return 3491;
}
else
{
@@ -3519,7 +3563,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx10xx100xxxx100xxx
fdot. */
- return 3480;
+ return 3492;
}
}
}
@@ -3581,7 +3625,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001101xxxx00xx010xxxx1000xx
fmlal. */
- return 3487;
+ return 3499;
}
else
{
@@ -3589,7 +3633,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001101xxxx10xx010xxxx1000xx
fmlal. */
- return 3488;
+ return 3500;
}
}
}
@@ -3644,7 +3688,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx10xxxx0xx010xxxxx001xx
fmlal. */
- return 3485;
+ return 3497;
}
else
{
@@ -3652,7 +3696,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx010xxxxx001xx
fmlal. */
- return 3486;
+ return 3498;
}
}
}
@@ -3721,7 +3765,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx001xxxxx000xx
fmlall. */
- return 3492;
+ return 3504;
}
}
else
@@ -3804,48 +3848,70 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx011xxxxx00xxx
fmlal. */
- return 3484;
+ return 3496;
}
}
else
{
- if (((word >> 16) & 0x1) == 0)
+ if (((word >> 20) & 0x1) == 0)
{
- if (((word >> 18) & 0x1) == 0)
+ if (((word >> 23) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x1000001xx1xx0x00xx111xxxxx00xxx
- fadd. */
- return 2530;
+ x10000010x10xxxx0xx111xxxxx00xxx
+ fmla. */
+ return 3329;
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx1xx1x00xx111xxxxx00xxx
- fadd. */
- return 3433;
+ if (((word >> 16) & 0x1) == 0)
+ {
+ if (((word >> 18) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011x10x0x00xx111xxxxx00xxx
+ fadd. */
+ return 2530;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011x10x1x00xx111xxxxx00xxx
+ fadd. */
+ return 3445;
+ }
+ }
+ else
+ {
+ if (((word >> 18) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011x10x0x10xx111xxxxx00xxx
+ fadd. */
+ return 2531;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011x10x1x10xx111xxxxx00xxx
+ fadd. */
+ return 3446;
+ }
+ }
}
}
else
{
- if (((word >> 18) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx1xx0x10xx111xxxxx00xxx
- fadd. */
- return 2531;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx1xx1x10xx111xxxxx00xxx
- fadd. */
- return 3434;
- }
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx11xxxx0xx111xxxxx00xxx
+ fmla. */
+ return 3330;
}
}
}
@@ -3970,7 +4036,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx00xx100xxxx110xxx
fdot. */
- return 3473;
+ return 3485;
}
else
{
@@ -3978,7 +4044,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx10xx100xxxx110xxx
fdot. */
- return 3474;
+ return 3486;
}
}
}
@@ -4263,21 +4329,43 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- if (((word >> 20) & 0x1) == 0)
+ if (((word >> 23) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx10xxxx0xx100xxxxx01xxx
- fdot. */
- return 3477;
+ if (((word >> 20) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000010x10xxxx0xx100xxxxx01xxx
+ fdot. */
+ return 3489;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000010x11xxxx0xx100xxxxx01xxx
+ fdot. */
+ return 3490;
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx11xxxx0xx100xxxxx01xxx
- fdot. */
- return 3478;
+ if (((word >> 16) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011x1xxxx00xx100xxxxx01xxx
+ fmla. */
+ return 3331;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011x1xxxx10xx100xxxxx01xxx
+ fmla. */
+ return 3332;
+ }
}
}
}
@@ -4532,43 +4620,65 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- if (((word >> 16) & 0x1) == 0)
+ if (((word >> 20) & 0x1) == 0)
{
- if (((word >> 18) & 0x1) == 0)
+ if (((word >> 23) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x1000001xx1xx0x00xx111xxxxx01xxx
- fsub. */
- return 2598;
+ x10000010x10xxxx0xx111xxxxx01xxx
+ fmls. */
+ return 3335;
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx1xx1x00xx111xxxxx01xxx
- fsub. */
- return 3435;
+ if (((word >> 16) & 0x1) == 0)
+ {
+ if (((word >> 18) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011x10x0x00xx111xxxxx01xxx
+ fsub. */
+ return 2598;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011x10x1x00xx111xxxxx01xxx
+ fsub. */
+ return 3447;
+ }
+ }
+ else
+ {
+ if (((word >> 18) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011x10x0x10xx111xxxxx01xxx
+ fsub. */
+ return 2599;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011x10x1x10xx111xxxxx01xxx
+ fsub. */
+ return 3448;
+ }
+ }
}
}
else
{
- if (((word >> 18) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx1xx0x10xx111xxxxx01xxx
- fsub. */
- return 2599;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx1xx1x10xx111xxxxx01xxx
- fsub. */
- return 3436;
- }
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx11xxxx0xx111xxxxx01xxx
+ fmls. */
+ return 3336;
}
}
}
@@ -4623,21 +4733,43 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- if (((word >> 20) & 0x1) == 0)
+ if (((word >> 23) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx10xxxx0xx100xxxxx11xxx
- fdot. */
- return 3471;
+ if (((word >> 20) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000010x10xxxx0xx100xxxxx11xxx
+ fdot. */
+ return 3483;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000010x11xxxx0xx100xxxxx11xxx
+ fdot. */
+ return 3484;
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx11xxxx0xx100xxxxx11xxx
- fdot. */
- return 3472;
+ if (((word >> 16) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011x1xxxx00xx100xxxxx11xxx
+ fmls. */
+ return 3337;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10000011x1xxxx10xx100xxxxx11xxx
+ fmls. */
+ return 3338;
+ }
}
}
}
@@ -5172,7 +5304,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xxxxx101000xx1x0xxxx0
fscale. */
- return 3407;
+ return 3419;
}
}
else
@@ -5320,7 +5452,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001x0100100111000xxxx0xxxxx
fcvt. */
- return 3404;
+ return 3416;
}
else
{
@@ -5328,7 +5460,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001x1100100111000xxxx0xxxxx
bfcvt. */
- return 3399;
+ return 3411;
}
}
else
@@ -5337,7 +5469,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx110100111000xxxx0xxxxx
fcvt. */
- return 3405;
+ return 3417;
}
}
else
@@ -5388,7 +5520,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xx100111000xxxx1xxxxx
fcvtn. */
- return 3406;
+ return 3418;
}
}
}
@@ -5471,7 +5603,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000010010x110111000xxxxxxxxx0
f1cvt. */
- return 3400;
+ return 3412;
}
else
{
@@ -5479,7 +5611,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011010x110111000xxxxxxxxx0
f2cvt. */
- return 3401;
+ return 3413;
}
}
else
@@ -5490,7 +5622,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000010110x110111000xxxxxxxxx0
bf1cvt. */
- return 3395;
+ return 3407;
}
else
{
@@ -5498,7 +5630,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011110x110111000xxxxxxxxx0
bf2cvt. */
- return 3396;
+ return 3408;
}
}
}
@@ -5533,7 +5665,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
[...]
[diff truncated at 100000 bytes]