[binutils-gdb/binutils-2_44-branch] Import AArch64 commits:
Nick Clifton
nickc@sourceware.org
Sun Feb 2 11:31:09 GMT 2025
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=6cf91d2b68768c936ea67a51cd5232f43ad188cf
commit 6cf91d2b68768c936ea67a51cd5232f43ad188cf
Author: Nick Clifton <nickc@redhat.com>
Date: Sun Feb 2 11:30:27 2025 +0000
Import AArch64 commits:
0fad7627cf8 aarch64: Fix overly lax +frintts dependency
99b90c46110 aarch64: Fix fp8 feature dependencies
71e59ebefc2 aarch64: Support +sme+nosve permissively
Diff:
---
gas/config/tc-aarch64.c | 35 ++++++++++++++++++++-----
gas/doc/c-aarch64.texi | 22 ++++++++--------
gas/testsuite/gas/aarch64/fp8-mul-illegal.d | 2 +-
gas/testsuite/gas/aarch64/fp8-sve-mul-illegal.d | 2 +-
gas/testsuite/gas/aarch64/sme-nosve-1.d | 15 +++++++++++
gas/testsuite/gas/aarch64/sme-nosve-1.s | 3 +++
opcodes/aarch64-tbl.h | 2 +-
7 files changed, 60 insertions(+), 21 deletions(-)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 8b074ff22dd..122ff49ca1a 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -10695,7 +10695,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
{"rcpc2", AARCH64_FEATURE (RCPC2), AARCH64_FEATURE (RCPC)},
{"dotprod", AARCH64_FEATURE (DOTPROD), AARCH64_FEATURE (SIMD)},
{"sha2", AARCH64_FEATURE (SHA2), AARCH64_FEATURE (SIMD)},
- {"frintts", AARCH64_FEATURE (FRINTTS), AARCH64_FEATURE (SIMD)},
+ {"frintts", AARCH64_FEATURE (FRINTTS), AARCH64_FEATURE (FP)},
{"sb", AARCH64_FEATURE (SB), AARCH64_NO_FEATURES},
{"predres", AARCH64_FEATURE (PREDRES), AARCH64_NO_FEATURES},
{"predres2", AARCH64_FEATURE (PREDRES2), AARCH64_FEATURE (PREDRES)},
@@ -10715,7 +10715,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
{"sve2-bitperm", AARCH64_FEATURE (SVE2_BITPERM),
AARCH64_FEATURE (SVE2)},
{"sme", AARCH64_FEATURE (SME),
- AARCH64_FEATURES (2, SVE2, BFLOAT16)},
+ AARCH64_FEATURES (3, BFLOAT16, F16, COMPNUM)},
{"sme-f64", AARCH64_FEATURE (SME_F64F64), AARCH64_FEATURE (SME)},
{"sme-f64f64", AARCH64_FEATURE (SME_F64F64), AARCH64_FEATURE (SME)},
{"sme-i64", AARCH64_FEATURE (SME_I16I64), AARCH64_FEATURE (SME)},
@@ -10751,18 +10751,18 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
{"brbe", AARCH64_FEATURE (BRBE), AARCH64_NO_FEATURES},
{"sme-lutv2", AARCH64_FEATURE (SME_LUTv2), AARCH64_FEATURE (SME2)},
{"fp8fma", AARCH64_FEATURE (FP8FMA), AARCH64_FEATURE (FP8)},
- {"fp8dot4", AARCH64_FEATURE (FP8DOT4), AARCH64_FEATURE (FP8FMA)},
- {"fp8dot2", AARCH64_FEATURE (FP8DOT2), AARCH64_FEATURE (FP8DOT4)},
+ {"fp8dot4", AARCH64_FEATURE (FP8DOT4), AARCH64_FEATURE (FP8)},
+ {"fp8dot2", AARCH64_FEATURE (FP8DOT2), AARCH64_FEATURE (FP8)},
{"ssve-fp8fma", AARCH64_FEATURE (SSVE_FP8FMA),
AARCH64_FEATURES (2, FP8, SME2)},
{"ssve-fp8dot4", AARCH64_FEATURE (SSVE_FP8DOT4),
- AARCH64_FEATURE (SSVE_FP8FMA)},
+ AARCH64_FEATURES (2, FP8, SME2)},
{"ssve-fp8dot2", AARCH64_FEATURE (SSVE_FP8DOT2),
- AARCH64_FEATURE (SSVE_FP8DOT4)},
+ AARCH64_FEATURES (2, FP8, SME2)},
{"sme-f8f32", AARCH64_FEATURE (SME_F8F32),
AARCH64_FEATURES (2, FP8, SME2)},
{"sme-f8f16", AARCH64_FEATURE (SME_F8F16),
- AARCH64_FEATURE (SME_F8F32)},
+ AARCH64_FEATURES (2, FP8, SME2)},
{"sme-f16f16", AARCH64_FEATURE (SME_F16F16), AARCH64_FEATURE (SME2)},
{"sme-b16b16", AARCH64_FEATURE (SME_B16B16),
AARCH64_FEATURES (2, SVE_B16B16, SME2)},
@@ -10837,6 +10837,13 @@ aarch64_feature_enable_set (aarch64_feature_set set)
for (opt = aarch64_features; opt->name != NULL; opt++)
if (AARCH64_CPU_HAS_ALL_FEATURES (set, opt->value))
AARCH64_MERGE_FEATURE_SETS (set, set, opt->require);
+ /* As a special case, we want +sme to imply +sve2, without letting
+ +nosve2 imply +nosme. This is to ensure maximum compatibility with
+ both toolchains that assume this dependency and those that don't. */
+ aarch64_feature_set sme = AARCH64_FEATURE (SME);
+ aarch64_feature_set sve2 = AARCH64_FEATURE (SVE2);
+ if (AARCH64_CPU_HAS_ALL_FEATURES (set, sme))
+ AARCH64_MERGE_FEATURE_SETS (set, set, sve2);
}
return set;
}
@@ -10941,6 +10948,20 @@ aarch64_parse_features (const char *str, const aarch64_feature_set **opt_p,
str = ext;
};
+ /* The special handling in aarch64_feature_enable_set ought to be sufficient
+ to accommodate uncertainty over whether or not +sme in a target string
+ implies +sve2. Unfortunately, many streaming SVE instructions are
+ currently marked as requiring SVE or SVE2, and some parsing and error
+ reporting decisions also depend on SVE or SVE2 being specified. So for
+ now we will reenable the SVE and SVE2 bits if SME is enabled. This allows
+ us to support, for example, a compiler passing the command line
+ `-march=armv9-a+sme+nosve` and expecting all SME instructions to remain
+ enabled. */
+ aarch64_feature_set sme = AARCH64_FEATURE (SME);
+ aarch64_feature_set sve_sve2 = AARCH64_FEATURES (2, SVE, SVE2);
+ if (AARCH64_CPU_HAS_ALL_FEATURES (*ext_set, sme))
+ AARCH64_MERGE_FEATURE_SETS (*ext_set, *ext_set, sve_sve2);
+
*ext_set = aarch64_update_virtual_dependencies (*ext_set);
return 1;
}
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index e75995323e9..7aea0cb8721 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -195,9 +195,9 @@ automatically cause those extensions to be disabled.
@tab Enable floating-point extensions.
@item @code{fp8} @tab
@tab Enable the Floating Point 8 (FP8) extension.
-@item @code{fp8dot2} @tab @code{fp8dot4}
+@item @code{fp8dot2} @tab @code{fp8}
@tab Enable the FP8 2-way dot product instructions.
-@item @code{fp8dot4} @tab @code{fp8fma}
+@item @code{fp8dot4} @tab @code{fp8}
@tab Enable the FP8 4-way dot product instructions.
@item @code{fp8fma} @tab @code{fp8}
@tab Enable the FP8 FMA instructions.
@@ -205,7 +205,7 @@ automatically cause those extensions to be disabled.
@tab Enable Armv8.2 16-bit floating-point multiplication variant support.
@item @code{fp16} @tab @code{fp}
@tab Enable Armv8.2 16-bit floating-point support.
-@item @code{frintts} @tab @code{simd}
+@item @code{frintts} @tab @code{fp}
@tab Enable floating-point round to integral value instructions.
@item @code{gcs} @tab
@tab Enable the Guarded Control Stack Extension.
@@ -267,11 +267,11 @@ automatically cause those extensions to be disabled.
@tab Enable Advanced SIMD extensions.
@item @code{sm4} @tab @code{simd}
@tab Enable the SM3 and SM4 cryptographic extensions.
-@item @code{sme} @tab @code{sve2}, @code{bf16}
- @tab Enable the Scalable Matrix Extension.
+@item @code{sme} @tab @code{bf16}, @code{fp16}, @code{fcma}
+ @tab Enable the Scalable Matrix Extension. This will also enable @code{sve2}, but disabling @code{sve2} does not disable @code{sme}.
@item @code{sme-b16b16} @tab @code{sme2}, @code{sve-b16b16}
@tab Enable SME ZA-targeting non-widening BFloat16 instructions.
-@item @code{sme-f8f16} @tab @code{sme-f8f32}
+@item @code{sme-f8f16} @tab @code{sme2}, @code{fp8}
@tab Enable the SME F8F16 Extension.
@item @code{sme-f8f32} @tab @code{sme2}, @code{fp8}
@tab Enable the SME F8F32 Extension.
@@ -287,12 +287,12 @@ automatically cause those extensions to be disabled.
@tab Enable SME2.1.
@item @code{ssbs} @tab
@tab Enable Speculative Store Bypassing Safe state read and write.
-@item @code{ssve-fp8dot2} @tab @code{ssve-fp8dot4}
- @tab Enable the Streaming SVE FP8 2-way dot product instructions. These can also be enabled using @code{+fp8dot2+sme2}.
-@item @code{ssve-fp8dot4} @tab @code{ssve-fp8fma}
- @tab Enable the Streaming SVE FP8 4-way dot product instructions. These can also be enabled using @code{+fp8dot4+sme2}.
+@item @code{ssve-fp8dot2} @tab @code{sme2}, @code{fp8}
+ @tab Enable the Streaming SVE FP8 2-way dot product instructions.
+@item @code{ssve-fp8dot4} @tab @code{sme2}, @code{fp8}
+ @tab Enable the Streaming SVE FP8 4-way dot product instructions.
@item @code{ssve-fp8fma} @tab @code{sme2}, @code{fp8}
- @tab Enable the Streaming SVE FP8 FMA instructions. These can also be enabled using @code{+fp8fma+sme2}.
+ @tab Enable the Streaming SVE FP8 FMA instructions.
@item @code{sve} @tab @code{fcma}
@tab Enable the Scalable Vector Extension.
@item @code{sve-b16b16} @tab
diff --git a/gas/testsuite/gas/aarch64/fp8-mul-illegal.d b/gas/testsuite/gas/aarch64/fp8-mul-illegal.d
index 1dac59a5d82..2a2224b0b09 100644
--- a/gas/testsuite/gas/aarch64/fp8-mul-illegal.d
+++ b/gas/testsuite/gas/aarch64/fp8-mul-illegal.d
@@ -1,2 +1,2 @@
-#as: -march=armv8-a+fp8dot2
+#as: -march=armv8-a+fp8dot2+fp8dot4+fp8fma
#error_output: fp8-mul-illegal.l
diff --git a/gas/testsuite/gas/aarch64/fp8-sve-mul-illegal.d b/gas/testsuite/gas/aarch64/fp8-sve-mul-illegal.d
index f1d98eec161..45dcca3c847 100644
--- a/gas/testsuite/gas/aarch64/fp8-sve-mul-illegal.d
+++ b/gas/testsuite/gas/aarch64/fp8-sve-mul-illegal.d
@@ -1,2 +1,2 @@
-#as: -march=armv8-a+sve2+fp8dot2
+#as: -march=armv8-a+sve2+fp8dot2+fp8dot4+fp8fma
#error_output: fp8-sve-mul-illegal.l
diff --git a/gas/testsuite/gas/aarch64/sme-nosve-1.d b/gas/testsuite/gas/aarch64/sme-nosve-1.d
new file mode 100644
index 00000000000..39abbe69067
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme-nosve-1.d
@@ -0,0 +1,15 @@
+#as: -march=armv8-a+sme
+#as: -march=armv8-a+sme+nosve
+#as: -march=armv8-a+sme+nosve2
+#as: -march=armv9-a+sme+nosve
+#objdump: -dr
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+
+0+ <\.text>:
+ *[0-9a-f]+: 04d6a441 abs z1\.d, p1/m, z2\.d
+ *[0-9a-f]+: 4503d041 adclb z1\.s, z2\.s, z3\.s
+ *[0-9a-f]+: c0904460 addha za0\.s, p1/m, p2/m, z3\.s
diff --git a/gas/testsuite/gas/aarch64/sme-nosve-1.s b/gas/testsuite/gas/aarch64/sme-nosve-1.s
new file mode 100644
index 00000000000..e41d791f2e4
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme-nosve-1.s
@@ -0,0 +1,3 @@
+abs z1.d, p1/m, z2.d
+adclb z1.s, z2.s, z3.s
+addha za0.s, p1/m, p2/m, z3.s
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 70cd3ffb6e0..0d42be3bef6 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2858,7 +2858,7 @@ static const aarch64_feature_set aarch64_feature_fp8dot2_sve =
static const aarch64_feature_set aarch64_feature_sme_f8f32 =
AARCH64_FEATURES (2, SME_F8F32, SME2);
static const aarch64_feature_set aarch64_feature_sme_f8f16 =
- AARCH64_FEATURES (2, SME_F8F32, SME2);
+ AARCH64_FEATURES (2, SME_F8F16, SME2);
static const aarch64_feature_set aarch64_feature_sme_f16f16_f8f16 =
AARCH64_FEATURES (2, SME_F16F16_F8F16, SME2);
static const aarch64_feature_set aarch64_feature_sme_f16f16 =
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