[binutils-gdb] arm, as: Support case incensitive VLDR/VSTR SYSREG
Andre Simoes Dias Vieira
avieira@sourceware.org
Wed Dec 31 16:15:18 GMT 2025
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=35554f7b14c0cd1c59be64010de67d895906fb21
commit 35554f7b14c0cd1c59be64010de67d895906fb21
Author: Andre Vieira <andre.simoesdiasvieira@arm.com>
Date: Wed Dec 31 16:14:29 2025 +0000
arm, as: Support case incensitive VLDR/VSTR SYSREG
To be consistent with VMRS/VMSR this changes VLDR/VSTR SYSREG to support case
insensitive system register operands.
Diff:
---
gas/config/tc-arm.c | 6 +----
gas/testsuite/gas/arm/archv8m_1m-cmse-main.d | 34 ++++++++++++++++++++++++++++
gas/testsuite/gas/arm/archv8m_1m-cmse-main.s | 34 ++++++++++++++++++++++++++++
3 files changed, 69 insertions(+), 5 deletions(-)
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index abad78a742f..7fdf4824957 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -6412,19 +6412,15 @@ parse_sys_vldr_vstr (char **str)
{"P0", 0x5, 0x1},
{"FPCXTNS", 0x6, 0x1},
{"FPCXT_NS", 0x6, 0x1},
- {"fpcxtns", 0x6, 0x1},
- {"fpcxt_ns", 0x6, 0x1},
{"FPCXTS", 0x7, 0x1},
{"FPCXT_S", 0x7, 0x1},
- {"fpcxts", 0x7, 0x1},
- {"fpcxt_s", 0x7, 0x1}
};
char *op_end = strchr (*str, ',');
size_t op_strlen = op_end - *str;
for (i = 0; i < sizeof (sysregs) / sizeof (sysregs[0]); i++)
{
- if (!strncmp (*str, sysregs[i].name, op_strlen))
+ if (!strncasecmp (*str, sysregs[i].name, op_strlen))
{
val = sysregs[i].regl | (sysregs[i].regh << 3);
*str = op_end;
diff --git a/gas/testsuite/gas/arm/archv8m_1m-cmse-main.d b/gas/testsuite/gas/arm/archv8m_1m-cmse-main.d
index 1ed543a04e8..b451258808d 100644
--- a/gas/testsuite/gas/arm/archv8m_1m-cmse-main.d
+++ b/gas/testsuite/gas/arm/archv8m_1m-cmse-main.d
@@ -54,4 +54,38 @@ Disassembly of section .text:
0+.* <[^>]*> edc3 ef80 vstr FPCXTS, \[r3\]
0+.* <[^>]*> bfa8 it ge
0+.* <[^>]*> edc3 ef80 vstrge FPCXTS, \[r3\]
+0+.* <[^>]*> ed92 2f80 vldr FPSCR, \[r2\]
+0+.* <[^>]*> ed92 2f82 vldr FPSCR, \[r2, #8\]
+0+.* <[^>]*> ed92 2f82 vldr FPSCR, \[r2, #8\]
+0+.* <[^>]*> ed12 2f82 vldr FPSCR, \[r2, #-8\]
+0+.* <[^>]*> edb2 2f82 vldr FPSCR, \[r2, #8\]!
+0+.* <[^>]*> edb2 2f82 vldr FPSCR, \[r2, #8\]!
+0+.* <[^>]*> ed32 2f82 vldr FPSCR, \[r2, #-8\]!
+0+.* <[^>]*> ecb2 2f82 vldr FPSCR, \[r2\], #8
+0+.* <[^>]*> ecb2 2f82 vldr FPSCR, \[r2\], #8
+0+.* <[^>]*> ec32 2f82 vldr FPSCR, \[r2\], #-8
+0+.* <[^>]*> ed93 4f80 vldr FPSCR_nzcvqc, \[r3\]
+0+.* <[^>]*> edd3 8f80 vldr VPR, \[r3\]
+0+.* <[^>]*> edd3 af80 vldr P0, \[r3\]
+0+.* <[^>]*> edd3 cf80 vldr FPCXTNS, \[r3\]
+0+.* <[^>]*> edd3 ef80 vldr FPCXTS, \[r3\]
+0+.* <[^>]*> bfa8 it ge
+0+.* <[^>]*> edd3 ef80 vldrge FPCXTS, \[r3\]
+0+.* <[^>]*> ed82 2f80 vstr FPSCR, \[r2\]
+0+.* <[^>]*> ed82 2f82 vstr FPSCR, \[r2, #8\]
+0+.* <[^>]*> ed82 2f82 vstr FPSCR, \[r2, #8\]
+0+.* <[^>]*> ed02 2f82 vstr FPSCR, \[r2, #-8\]
+0+.* <[^>]*> eda2 2f82 vstr FPSCR, \[r2, #8\]!
+0+.* <[^>]*> eda2 2f82 vstr FPSCR, \[r2, #8\]!
+0+.* <[^>]*> ed22 2f82 vstr FPSCR, \[r2, #-8\]!
+0+.* <[^>]*> eca2 2f82 vstr FPSCR, \[r2\], #8
+0+.* <[^>]*> eca2 2f82 vstr FPSCR, \[r2\], #8
+0+.* <[^>]*> ec22 2f82 vstr FPSCR, \[r2\], #-8
+0+.* <[^>]*> ed83 4f80 vstr FPSCR_nzcvqc, \[r3\]
+0+.* <[^>]*> edc3 8f80 vstr VPR, \[r3\]
+0+.* <[^>]*> edc3 af80 vstr P0, \[r3\]
+0+.* <[^>]*> edc3 cf80 vstr FPCXTNS, \[r3\]
+0+.* <[^>]*> edc3 ef80 vstr FPCXTS, \[r3\]
+0+.* <[^>]*> bfa8 it ge
+0+.* <[^>]*> edc3 ef80 vstrge FPCXTS, \[r3\]
#...
diff --git a/gas/testsuite/gas/arm/archv8m_1m-cmse-main.s b/gas/testsuite/gas/arm/archv8m_1m-cmse-main.s
index 9a20e1e4fe7..402f4ee2e55 100644
--- a/gas/testsuite/gas/arm/archv8m_1m-cmse-main.s
+++ b/gas/testsuite/gas/arm/archv8m_1m-cmse-main.s
@@ -52,3 +52,37 @@ vstr P0, [r3] @ Accepts P0 system register
vstr FPCXTNS, [r3] @ Accepts FPCXTNS system register
vstr FPCXTS, [r3] @ Accepts FPCXTS system register
vstrge FPCXTS, [r3] @ Accepts conditional execution
+
+vldr fpscr, [r2] @ Accepts offset variant without immediate
+vldr fpscr, [r2, #8] @ Likewise but with immediate without sign
+vldr fpscr, [r2, #+8] @ Likewise but with positive sign
+vldr fpscr, [r2, #-8] @ Likewise but with negative sign
+vldr fpscr, [r2, #8]! @ Accepts pre-index variant with immediate without sign
+vldr fpscr, [r2, #+8]! @ Likewise but with positive sign
+vldr fpscr, [r2, #-8]! @ Likewise but with negative sign
+vldr fpscr, [r2], #8 @ Accepts post-index variant with immediate without sign
+vldr fpscr, [r2], #+8 @ Likewise but with positive sign
+vldr fpscr, [r2], #-8 @ Likewise but with negative sign
+vldr fpscr_nzcvqc, [r3] @ Accepts FPSCR_nzcvqc system register
+vldr vpr, [r3] @ Accepts VPR system register
+vldr p0, [r3] @ Accepts P0 system register
+vldr fpcxtns, [r3] @ Accepts FPCXTNS system register
+vldr fpcxts, [r3] @ Accepts FPCXTS system register
+vldrge fpcxts, [r3] @ Accepts conditional execution
+
+vstr fpscr, [r2] @ Accepts offset variant without immediate
+vstr fpscr, [r2, #8] @ Likewise but with immediate without sign
+vstr fpscr, [r2, #+8] @ Likewise but with positive sign
+vstr fpscr, [r2, #-8] @ Likewise but with negative sign
+vstr fpscr, [r2, #8]! @ Accepts pre-index variant with immediate without sign
+vstr fpscr, [r2, #+8]! @ Likewise but with positive sign
+vstr fpscr, [r2, #-8]! @ Likewise but with negative sign
+vstr fpscr, [r2], #8 @ Accepts post-index variant with immediate without sign
+vstr fpscr, [r2], #+8 @ Likewise but with positive sign
+vstr fpscr, [r2], #-8 @ Likewise but with negative sign
+vstr fpscr_nzcvqc, [r3] @ Accepts FPSCR_nzcvqc system register
+vstr vpr, [r3] @ Accepts VPR system register
+vstr p0, [r3] @ Accepts P0 system register
+vstr fpcxtns, [r3] @ Accepts FPCXTNS system register
+vstr fpcxts, [r3] @ Accepts FPCXTS system register
+vstrge fpcxts, [r3] @ Accepts conditional execution
More information about the Binutils-cvs
mailing list