[binutils-gdb] aarch64: Add FEAT_MOPS_GO instructions
Alice Carlotti
acarlotti@sourceware.org
Sat Dec 27 14:02:59 GMT 2025
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=242e78b76a7894b65af1c6725239a553ba90870b
commit 242e78b76a7894b65af1c6725239a553ba90870b
Author: Yury Khrustalev <yury.khrustalev@arm.com>
Date: Thu Dec 18 13:43:51 2025 +0000
aarch64: Add FEAT_MOPS_GO instructions
Also add +mops-go feature flag and make the mops-go feature
depend on the memtag and mops features.
Diff:
---
gas/config/tc-aarch64.c | 2 +
include/opcode/aarch64.h | 2 +
opcodes/aarch64-dis-2.c | 128 +++++++++++++++++++++++++++++++++++++++++++++--
opcodes/aarch64-opc.c | 29 +++++++++++
opcodes/aarch64-tbl-2.h | 12 +++++
opcodes/aarch64-tbl.h | 32 ++++++++++++
6 files changed, 201 insertions(+), 4 deletions(-)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 6243ea240ad..887612c389c 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -10902,6 +10902,8 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
{"ssve-fexpa", AARCH64_FEATURE (SSVE_FEXPA), AARCH64_FEATURE (SME2)},
{"sme-tmop", AARCH64_FEATURE (SME_TMOP), AARCH64_FEATURE (SME2)},
{"sme-mop4", AARCH64_FEATURE (SME_MOP4), AARCH64_FEATURE (SME2)},
+ {"mops-go", AARCH64_FEATURE (MOPS_GO),
+ AARCH64_FEATURES (2, MOPS, MEMTAG)},
{NULL, AARCH64_NO_FEATURES, AARCH64_NO_FEATURES},
};
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 3754f7082a5..1af608fe5f9 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -265,6 +265,8 @@ enum aarch64_feature_bit {
AARCH64_FEATURE_SME_MOP4,
/* LSCP instructions. */
AARCH64_FEATURE_LSCP,
+ /* +mops-go */
+ AARCH64_FEATURE_MOPS_GO,
/* Virtual features. These are used to gate instructions that are enabled
by either of two (or more) sets of command line flags. */
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index 80f14b37af4..5845df88993 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -27928,10 +27928,130 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 10) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx011101x1xxxxxxxxxxx0xxxxxxxxxx. */
- return A64_OPID_1d400800_ldapur_Ft_RCPC3_ADDR_OFFSET;
+ if (((word >> 11) & 0x1) == 0)
+ {
+ if (((word >> 12) & 0x1) == 0)
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx011101x1xxxxxx000000xxxxxxxxxx. */
+ return A64_OPID_1ddf0000_setgop_MOPS_ADDR_Rd_MOPS_WB_Rn;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx011101x1xxxxxx100000xxxxxxxxxx. */
+ return A64_OPID_1ddf8000_setgoe_MOPS_ADDR_Rd_MOPS_WB_Rn;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx011101x1xxxxxxx10000xxxxxxxxxx. */
+ return A64_OPID_1ddf4000_setgom_MOPS_ADDR_Rd_MOPS_WB_Rn;
+ }
+ }
+ else
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx011101x1xxxxxx001000xxxxxxxxxx. */
+ return A64_OPID_1ddf2000_setgopn_MOPS_ADDR_Rd_MOPS_WB_Rn;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx011101x1xxxxxx101000xxxxxxxxxx. */
+ return A64_OPID_1ddfa000_setgoen_MOPS_ADDR_Rd_MOPS_WB_Rn;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx011101x1xxxxxxx11000xxxxxxxxxx. */
+ return A64_OPID_1ddf6000_setgomn_MOPS_ADDR_Rd_MOPS_WB_Rn;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx011101x1xxxxxx000100xxxxxxxxxx. */
+ return A64_OPID_1ddf1000_setgopt_MOPS_ADDR_Rd_MOPS_WB_Rn;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx011101x1xxxxxx100100xxxxxxxxxx. */
+ return A64_OPID_1ddf9000_setgoet_MOPS_ADDR_Rd_MOPS_WB_Rn;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx011101x1xxxxxxx10100xxxxxxxxxx. */
+ return A64_OPID_1ddf5000_setgomt_MOPS_ADDR_Rd_MOPS_WB_Rn;
+ }
+ }
+ else
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx011101x1xxxxxx001100xxxxxxxxxx. */
+ return A64_OPID_1ddf3000_setgoptn_MOPS_ADDR_Rd_MOPS_WB_Rn;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx011101x1xxxxxx101100xxxxxxxxxx. */
+ return A64_OPID_1ddfb000_setgoetn_MOPS_ADDR_Rd_MOPS_WB_Rn;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx011101x1xxxxxxx11100xxxxxxxxxx. */
+ return A64_OPID_1ddf7000_setgomtn_MOPS_ADDR_Rd_MOPS_WB_Rn;
+ }
+ }
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx011101x1xxxxxxxxxx10xxxxxxxxxx. */
+ return A64_OPID_1d400800_ldapur_Ft_RCPC3_ADDR_OFFSET;
+ }
}
else
{
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index b697d772556..db68d893fe4 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -5624,6 +5624,35 @@ verify_three_different_regs (const struct aarch64_inst *inst,
return ERR_OK;
}
+/* Check an instruction that takes two register operands and that
+ requires the register numbers to be distinct from each another. */
+
+static enum err_type
+verify_two_diff_regs (const struct aarch64_inst *inst,
+ const aarch64_insn insn ATTRIBUTE_UNUSED,
+ bfd_vma pc ATTRIBUTE_UNUSED,
+ bool encoding ATTRIBUTE_UNUSED,
+ aarch64_operand_error *mismatch_detail
+ ATTRIBUTE_UNUSED,
+ aarch64_instr_sequence *insn_sequence
+ ATTRIBUTE_UNUSED)
+{
+ int rd, rn;
+
+ rd = inst->operands[0].reg.regno;
+ rn = inst->operands[1].reg.regno;
+ if (rd == rn)
+ {
+ mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
+ mismatch_detail->error
+ = _("the two register operands must be distinct from each other");
+ mismatch_detail->index = -1;
+ return ERR_UND;
+ }
+
+ return ERR_OK;
+}
+
/* Add INST to the end of INSN_SEQUENCE. */
static void
diff --git a/opcodes/aarch64-tbl-2.h b/opcodes/aarch64-tbl-2.h
index c254440f323..97406b9750a 100644
--- a/opcodes/aarch64-tbl-2.h
+++ b/opcodes/aarch64-tbl-2.h
@@ -3398,6 +3398,18 @@ enum aarch64_opcode_idx
A64_OPID_1dc03400_setgptn_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm,
A64_OPID_1dc07400_setgmtn_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm,
A64_OPID_1dc0b400_setgetn_MOPS_ADDR_Rd_MOPS_WB_Rn_Rm,
+ A64_OPID_1ddf0000_setgop_MOPS_ADDR_Rd_MOPS_WB_Rn,
+ A64_OPID_1ddf4000_setgom_MOPS_ADDR_Rd_MOPS_WB_Rn,
+ A64_OPID_1ddf8000_setgoe_MOPS_ADDR_Rd_MOPS_WB_Rn,
+ A64_OPID_1ddf1000_setgopt_MOPS_ADDR_Rd_MOPS_WB_Rn,
+ A64_OPID_1ddf5000_setgomt_MOPS_ADDR_Rd_MOPS_WB_Rn,
+ A64_OPID_1ddf9000_setgoet_MOPS_ADDR_Rd_MOPS_WB_Rn,
+ A64_OPID_1ddf2000_setgopn_MOPS_ADDR_Rd_MOPS_WB_Rn,
+ A64_OPID_1ddf6000_setgomn_MOPS_ADDR_Rd_MOPS_WB_Rn,
+ A64_OPID_1ddfa000_setgoen_MOPS_ADDR_Rd_MOPS_WB_Rn,
+ A64_OPID_1ddf3000_setgoptn_MOPS_ADDR_Rd_MOPS_WB_Rn,
+ A64_OPID_1ddf7000_setgomtn_MOPS_ADDR_Rd_MOPS_WB_Rn,
+ A64_OPID_1ddfb000_setgoetn_MOPS_ADDR_Rd_MOPS_WB_Rn,
A64_OPID_54000010_bc_c_ADDR_PCREL19,
A64_OPID_11c00000_smax_Rd_Rn_CSSC_SIMM8,
A64_OPID_11c40000_umax_Rd_Rn_CSSC_UIMM8,
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 935a335b416..3a98e042378 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2929,6 +2929,8 @@ static const aarch64_feature_set aarch64_feature_mops =
AARCH64_FEATURE (MOPS);
static const aarch64_feature_set aarch64_feature_mops_memtag =
AARCH64_FEATURES (2, MOPS, MEMTAG);
+static const aarch64_feature_set aarch64_feature_mops_go =
+ AARCH64_FEATURE (MOPS_GO);
static const aarch64_feature_set aarch64_feature_hbc =
AARCH64_FEATURE (HBC);
static const aarch64_feature_set aarch64_feature_cssc =
@@ -3119,6 +3121,7 @@ static const aarch64_feature_set aarch64_feature_sme_mop4_i16i64 =
#define WFXT &aarch64_feature_wfxt
#define MOPS &aarch64_feature_mops
#define MOPS_MEMTAG &aarch64_feature_mops_memtag
+#define MOPS_GO &aarch64_feature_mops_go
#define HBC &aarch64_feature_hbc
#define CSSC &aarch64_feature_cssc
#define CHK &aarch64_feature_chk
@@ -3376,6 +3379,9 @@ static const aarch64_feature_set aarch64_feature_sme_mop4_i16i64 =
#define MOPS_MEMTAG_INSN(NAME, OPCODE, MASK, CLASS, OPS, QUALS, FLAGS, CONSTRAINTS, VERIFIER) \
{ NAME, OPCODE, MASK, CLASS, 0, MOPS_MEMTAG, OPS, QUALS, FLAGS, \
CONSTRAINTS, 0, VERIFIER }
+#define MOPS_GO_INSN(NAME, OPCODE, MASK, CLASS, OPS, QUALS, FLAGS, CONSTRAINTS, VERIFIER) \
+ { NAME, OPCODE, MASK, CLASS, 0, MOPS_GO, OPS, QUALS, FLAGS, \
+ CONSTRAINTS, 0, VERIFIER }
#define HBC_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, 0, HBC, OPS, QUALS, FLAGS, 0, 0, NULL }
#define CSSC_INSN(NAME,OPCODE,MASK,OPS,QUALS,FLAGS) \
@@ -3548,6 +3554,11 @@ static const aarch64_feature_set aarch64_feature_sme_mop4_i16i64 =
OP3 (MOPS_ADDR_Rd, MOPS_WB_Rn, Rm), QL_I3SAMEX, FLAGS, \
CONSTRAINTS, VERIFIER (three_different_regs))
+#define MOPS_GO_SET_OP1_OP2_PME_INSN(NAME, OPCODE, MASK, FLAGS, CONSTRAINTS, ISA) \
+ ISA (NAME, OPCODE, MASK, 0, \
+ OP2 (MOPS_ADDR_Rd, MOPS_WB_Rn), QL_I2SAMEX, FLAGS, \
+ CONSTRAINTS, VERIFIER (two_diff_regs))
+
/* These instructions must remain consecutive, since we rely on the order
when detecting invalid sequences. */
#define MOPS_SET_OP1_OP2_INSN(NAME, SUFFIX, OPCODE, MASK, ISA) \
@@ -3558,12 +3569,28 @@ static const aarch64_feature_set aarch64_feature_sme_mop4_i16i64 =
MOPS_SET_OP1_OP2_PME_INSN (NAME "e" SUFFIX, OPCODE | 0x8000, MASK, \
0, C_SCAN_MOPS_E, ISA)
+/* These instructions must remain consecutive, since we rely on the order
+ when detecting invalid sequences. */
+#define MOPS_GO_SET_OP1_OP2_INSN(NAME, SUFFIX, OPCODE, MASK, ISA) \
+ MOPS_GO_SET_OP1_OP2_PME_INSN (NAME "p" SUFFIX, OPCODE, MASK, \
+ F_SCAN, C_SCAN_MOPS_P, ISA), \
+ MOPS_GO_SET_OP1_OP2_PME_INSN (NAME "m" SUFFIX, OPCODE | 0x4000, MASK, \
+ 0, C_SCAN_MOPS_M, ISA), \
+ MOPS_GO_SET_OP1_OP2_PME_INSN (NAME "e" SUFFIX, OPCODE | 0x8000, MASK, \
+ 0, C_SCAN_MOPS_E, ISA)
+
#define MOPS_SET_INSN(NAME, OPCODE, MASK, ISA) \
MOPS_SET_OP1_OP2_INSN (NAME, "", OPCODE, MASK, ISA), \
MOPS_SET_OP1_OP2_INSN (NAME, "t", OPCODE | 0x1000, MASK, ISA), \
MOPS_SET_OP1_OP2_INSN (NAME, "n", OPCODE | 0x2000, MASK, ISA), \
MOPS_SET_OP1_OP2_INSN (NAME, "tn", OPCODE | 0x3000, MASK, ISA)
+#define MOPS_GO_SET_INSN(NAME, OPCODE, MASK, ISA) \
+ MOPS_GO_SET_OP1_OP2_INSN (NAME, "", OPCODE, MASK, ISA), \
+ MOPS_GO_SET_OP1_OP2_INSN (NAME, "t", OPCODE | 0x1000, MASK, ISA), \
+ MOPS_GO_SET_OP1_OP2_INSN (NAME, "n", OPCODE | 0x2000, MASK, ISA), \
+ MOPS_GO_SET_OP1_OP2_INSN (NAME, "tn", OPCODE | 0x3000, MASK, ISA)
+
#define PREDRES2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, 0, PREDRES2, OPS, QUALS, FLAGS, 0, 0, NULL }
@@ -7040,6 +7067,11 @@ const struct aarch64_opcode aarch64_opcode_table[] =
setge setget setgen setgetn */
MOPS_SET_INSN ("setg", 0x1dc00400, 0xffe0fc00, MOPS_MEMTAG_INSN),
+ /* setgop setgopt setgopn setgoptn
+ setgom setgomt setgomn setgomtn
+ setgoe setgoet setgoen setgoetn */
+ MOPS_GO_SET_INSN ("setgo", 0x1ddf0000, 0x3ffffc00, MOPS_GO_INSN),
+
HBC_INSN ("bc.c", 0x54000010, 0xff000010, condbranch, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_COND),
/* CSSC with immediates. */
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