[binutils-gdb] RISC-V: Fix implicit dependency of Zabha and Zacas

[Nelson Chu]

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=542d8137f9f6a2c66e898af136dc792a3963f932

commit 542d8137f9f6a2c66e898af136dc792a3963f932
Author: Xiao Zeng <zengxiao@eswincomputing.com>
Date:   Tue Oct 8 09:10:35 2024 +0800

    RISC-V: Fix implicit dependency of Zabha and Zacas
    
    1 Zabha depends on Zaamo:
    <https://github.com/riscv/riscv-isa-manual/blob/main/src/zabha.adoc>
    
    2 Zacas depends on Zaamo:
    <https://github.com/riscv/riscv-isa-manual/blob/main/src/zacas.adoc>
    
    bfd/ChangeLog:
    
            * elfxx-riscv.c: Zabha and Zacas implicitly depend on Zaamo.
    
    gas/ChangeLog:
    
            * testsuite/gas/riscv/imply.d: Updated.
    
    Signed-off-by: Xiao Zeng <zengxiao@eswincomputing.com>

Diff:
---
 bfd/elfxx-riscv.c               | 4 ++--
 gas/testsuite/gas/riscv/imply.d | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 26ec664d88a..4b48d8ee9f0 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1182,8 +1182,8 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
 
   {"m", "+zmmul", check_implicit_always},
 
-  {"zabha", "+a", check_implicit_always},
-  {"zacas", "+a", check_implicit_always},
+  {"zabha", "+zaamo", check_implicit_always},
+  {"zacas", "+zaamo", check_implicit_always},
   {"a", "+zaamo,+zalrsc", check_implicit_always},
 
   {"xsfvcp", "+zve32x", check_implicit_always},
diff --git a/gas/testsuite/gas/riscv/imply.d b/gas/testsuite/gas/riscv/imply.d
index 88b8c46bb89..26eff8c650a 100644
--- a/gas/testsuite/gas/riscv/imply.d
+++ b/gas/testsuite/gas/riscv/imply.d
@@ -15,8 +15,8 @@ SYMBOL TABLE:
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zicntr2p0_zicsr2p0
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zicsr2p0_zihpm2p0
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_m2p0_zmmul1p0
-[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_a2p1_zaamo1p0_zabha1p0_zalrsc1p0
-[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_a2p1_zaamo1p0_zacas1p0_zalrsc1p0
+[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zaamo1p0_zabha1p0
+[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zaamo1p0_zacas1p0
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_a2p1_zaamo1p0_zalrsc1p0
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfvcp1p0
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0