[binutils-gdb] x86/Intel: warn about undue mnemonic suffixes
Jan Beulich
jbeulich@sourceware.org
Wed May 29 08:03:25 GMT 2024
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=b83021de7a83a353b5e9ad1ef428aec05846803e
commit b83021de7a83a353b5e9ad1ef428aec05846803e
Author: Jan Beulich <jbeulich@suse.com>
Date: Wed May 29 10:03:00 2024 +0200
x86/Intel: warn about undue mnemonic suffixes
Except for very few insns mnemonic suffixes aren't permitted in Intel
syntax. Warn about such for now, indicating that they will be outright
refused down the road.
While fiddling with testcases to address fallout, drop a few things
which should never have been tested as valid Intel syntax.
Also add a previously missing line to simd-suffix.d.
Diff:
---
gas/NEWS | 3 +
gas/config/tc-i386.c | 13 +
gas/testsuite/gas/i386/ilp32/x86-64-branch.d | 4 -
gas/testsuite/gas/i386/intel-intel.d | 28 +-
gas/testsuite/gas/i386/intel-suffix.d | 1 +
gas/testsuite/gas/i386/intel-suffix.e | 22 +
gas/testsuite/gas/i386/intel.d | 66 +-
gas/testsuite/gas/i386/intel.s | 4 -
gas/testsuite/gas/i386/intel16.d | 1 +
gas/testsuite/gas/i386/intel16.e | 10 +
gas/testsuite/gas/i386/simd-intel.d | 4 -
gas/testsuite/gas/i386/simd-suffix.d | 5 +-
gas/testsuite/gas/i386/simd.d | 4 -
gas/testsuite/gas/i386/simd.s | 4 -
gas/testsuite/gas/i386/simd16.d | 4 -
gas/testsuite/gas/i386/x86-64-avx-intel.d | 2 -
gas/testsuite/gas/i386/x86-64-avx-scalar-intel.d | 2 -
gas/testsuite/gas/i386/x86-64-avx-scalar.d | 2 -
gas/testsuite/gas/i386/x86-64-avx-scalar.s | 10 +-
gas/testsuite/gas/i386/x86-64-avx.d | 2 -
gas/testsuite/gas/i386/x86-64-avx.s | 10 +-
gas/testsuite/gas/i386/x86-64-branch.d | 4 -
gas/testsuite/gas/i386/x86-64-branch.s | 8 +-
gas/testsuite/gas/i386/x86-64-gottpoff.s | 12 +-
gas/testsuite/gas/i386/x86-64-lkgs-intel.d | 1 -
gas/testsuite/gas/i386/x86-64-lkgs.d | 1 -
gas/testsuite/gas/i386/x86-64-lkgs.s | 1 -
gas/testsuite/gas/i386/x86-64-simd-intel.d | 8 -
gas/testsuite/gas/i386/x86-64-simd-suffix.d | 8 -
gas/testsuite/gas/i386/x86-64-simd.d | 8 -
gas/testsuite/gas/i386/x86-64-simd.s | 8 -
gas/testsuite/gas/i386/x86-64-sse2avx.s | 8 +-
gas/testsuite/gas/i386/x86-64-tlsdesc.s | 6 +-
opcodes/i386-gen.c | 1 +
opcodes/i386-opc.h | 4 +
opcodes/i386-opc.tbl | 174 +-
opcodes/i386-tbl.h | 11140 ++++++++++-----------
37 files changed, 5779 insertions(+), 5814 deletions(-)
diff --git a/gas/NEWS b/gas/NEWS
index b6f40a340d2..e51c3bbba6d 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,8 @@
-*- text -*-
+* In x86 Intel syntax undue mnemonic suffixes are now warned about. This is
+ a first step towards rejecting their use where unjustified.
+
* Assembler macros as well as the bodies of .irp / .irpc can now use the
syntax \+ to access the number of times a given macro has been executed.
This is similar to the already existing \@ syntax, except that the count is
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 65d992311b7..9e13f2fc9f1 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -9209,6 +9209,19 @@ match_template (char mnem_suffix)
affect assembly of the next line of code. */
as_warn (_("stand-alone `%s' prefix"), insn_name (t));
}
+
+ if (intel_syntax && mnem_suffix && !t->opcode_modifier.intelsuffix)
+ {
+ static bool noticed;
+
+ as_warn (_("mnemonic suffix used with `%s'"), insn_name (t));
+ if (!noticed)
+ {
+ noticed = true;
+ as_warn (_(
+"NOTE: Such forms are deprecated and will be rejected by a future version of the assembler"));
+ }
+ }
}
/* Copy the template we found. */
diff --git a/gas/testsuite/gas/i386/ilp32/x86-64-branch.d b/gas/testsuite/gas/i386/ilp32/x86-64-branch.d
index b553bb15b4a..53dadf3d01f 100644
--- a/gas/testsuite/gas/i386/ilp32/x86-64-branch.d
+++ b/gas/testsuite/gas/i386/ilp32/x86-64-branch.d
@@ -29,13 +29,9 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 2e 74 00[ ]+je,pn +[0-9a-fx]+ <.*>
[0-9a-f]+ <.*>:
[ ]*[a-f0-9]+: ff d0 call \*%rax
-[ ]*[a-f0-9]+: ff d0 call \*%rax
-[ ]*[a-f0-9]+: 66 ff d0 data16 call \*%rax
[ ]*[a-f0-9]+: 66 ff d0 data16 call \*%rax
[ ]*[a-f0-9]+: 66 ff 10 data16 call \*\(%rax\)
[ ]*[a-f0-9]+: ff e0 jmp \*%rax
-[ ]*[a-f0-9]+: ff e0 jmp \*%rax
-[ ]*[a-f0-9]+: 66 ff e0 data16 jmp \*%rax
[ ]*[a-f0-9]+: 66 ff e0 data16 jmp \*%rax
[ ]*[a-f0-9]+: 66 ff 20 data16 jmp \*\(%rax\)
[ ]*[a-f0-9]+: e8 00 00 00 00 call [0-9a-fx]* <.*> [0-9a-f]*: R_X86_64_PC32 \*ABS\*\+0x10003c
diff --git a/gas/testsuite/gas/i386/intel-intel.d b/gas/testsuite/gas/i386/intel-intel.d
index ee6d88cb756..88d867cbf24 100644
--- a/gas/testsuite/gas/i386/intel-intel.d
+++ b/gas/testsuite/gas/i386/intel-intel.d
@@ -202,8 +202,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c9 + leave
[ ]*[a-f0-9]+: ca 90 90 + retf 0x9090
[ ]*[a-f0-9]+: cb + retf
-[ ]*[a-f0-9]+: ca 90 90 + retf 0x9090
-[ ]*[a-f0-9]+: cb + retf
[ ]*[a-f0-9]+: cc + int3
[ ]*[a-f0-9]+: cd 90 + int 0x90
[ ]*[a-f0-9]+: ce + into
@@ -223,10 +221,10 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: dd 90 90 90 90 90 + fst QWORD PTR \[eax-0x6f6f6f70\]
[ ]*[a-f0-9]+: de 90 90 90 90 90 + ficom WORD PTR \[eax-0x6f6f6f70\]
[ ]*[a-f0-9]+: df 90 90 90 90 90 + fist WORD PTR \[eax-0x6f6f6f70\]
-[ ]*[a-f0-9]+: e0 90 + loopne 260 <foo\+0x260>
-[ ]*[a-f0-9]+: e1 90 + loope 262 <foo\+0x262>
-[ ]*[a-f0-9]+: e2 90 + loop 264 <foo\+0x264>
-[ ]*[a-f0-9]+: e3 90 + jecxz 266 <foo\+0x266>
+[ ]*[a-f0-9]+: e0 90 + loopne .*
+[ ]*[a-f0-9]+: e1 90 + loope .*
+[ ]*[a-f0-9]+: e2 90 + loop .*
+[ ]*[a-f0-9]+: e3 90 + jecxz .*
[ ]*[a-f0-9]+: e4 90 + in al,0x90
[ ]*[a-f0-9]+: e5 90 + in eax,0x90
[ ]*[a-f0-9]+: e6 90 + out 0x90,al
@@ -234,7 +232,7 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: e8 90 90 90 90 + call 90909... <barn\+0x90908...>
[ ]*[a-f0-9]+: e9 90 90 90 90 + jmp 90909... <barn\+0x90908...>
[ ]*[a-f0-9]+: ea 90 90 90 90 90 90 jmp 0x9090:0x90909090
-[ ]*[a-f0-9]+: eb 90 + jmp 281 <foo\+0x281>
+[ ]*[a-f0-9]+: eb 90 + jmp .*
[ ]*[a-f0-9]+: ec + in al,dx
[ ]*[a-f0-9]+: ed + in eax,dx
[ ]*[a-f0-9]+: ee + out dx,al
@@ -524,8 +522,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 c9 + leavew
[ ]*[a-f0-9]+: 66 ca 90 90 + retfw 0x9090
[ ]*[a-f0-9]+: 66 cb + retfw
-[ ]*[a-f0-9]+: 66 ca 90 90 + retfw 0x9090
-[ ]*[a-f0-9]+: 66 cb + retfw
[ ]*[a-f0-9]+: 66 cf + iretw
[ ]*[a-f0-9]+: 66 d1 90 90 90 90 90 rcl WORD PTR \[eax-0x6f6f6f70\],1
[ ]*[a-f0-9]+: 66 d3 90 90 90 90 90 rcl WORD PTR \[eax-0x6f6f6f70\],cl
@@ -585,15 +581,15 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c3 + ret
[a-f0-9]+ <bar>:
-[ ]*[a-f0-9]+: e8 f9 ff ff ff + call 9d9 <gs_foo>
-[ ]*[a-f0-9]+: e8 f5 ff ff ff + call 9da <short_foo>
+[ ]*[a-f0-9]+: e8 f9 ff ff ff + call .* <gs_foo>
+[ ]*[a-f0-9]+: e8 f5 ff ff ff + call .* <short_foo>
[ ]*[a-f0-9]+: dd 1c d0 + fstp QWORD PTR \[eax\+edx\*8\]
[ ]*[a-f0-9]+: b9 00 00 00 00 + mov ecx,0x0
[ ]*[a-f0-9]+: 88 04 16 + mov BYTE PTR \[esi\+edx\*1\],al
[ ]*[a-f0-9]+: 88 04 32 + mov BYTE PTR \[edx\+esi\*1\],al
[ ]*[a-f0-9]+: 88 04 56 + mov BYTE PTR \[esi\+edx\*2\],al
[ ]*[a-f0-9]+: 88 04 56 + mov BYTE PTR \[esi\+edx\*2\],al
-[ ]*[a-f0-9]+: eb 0c + jmp a07 <rot5>
+[ ]*[a-f0-9]+: eb 0c + jmp .* <rot5>
[ ]*[a-f0-9]+: 6c + ins BYTE PTR es:\[edi\],dx
[ ]*[a-f0-9]+: 66 0f c1 90 90 90 90 90 xadd WORD PTR \[eax-0x6f6f6f70\],dx
[ ]*[a-f0-9]+: 83 e0 f8 + and eax,0xfffffff8
@@ -609,8 +605,8 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 2f + das
[ ]*[a-f0-9]+: ea 90 90 90 90 90 90 jmp 0x9090:0x90909090
[ ]*[a-f0-9]+: 66 a5 + movs WORD PTR es:\[edi\],WORD PTR ds:\[esi\]
-[ ]*[a-f0-9]+: 70 90 + jo 9be <foo\+0x9be>
-[ ]*[a-f0-9]+: 75 fe + jne a2e <rot5\+0x27>
+[ ]*[a-f0-9]+: 70 90 + jo .* <foo\+.*>
+[ ]*[a-f0-9]+: 75 fe + jne .* <rot5\+.*>
[ ]*[a-f0-9]+: 0f 6f 35 28 00 00 00 movq mm6,QWORD PTR ds:0x28
[ ]*[a-f0-9]+: 03 3c c3 + add edi,DWORD PTR \[ebx\+eax\*8\]
[ ]*[a-f0-9]+: 0f 6e 44 c3 04 + movd mm0,DWORD PTR \[ebx\+eax\*8\+0x4\]
@@ -623,8 +619,8 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 8b 84 43 00 40 00 00 mov ax,WORD PTR \[ebx\+eax\*2\+0x4000\]
[ ]*[a-f0-9]+: ff e0 + jmp eax
[ ]*[a-f0-9]+: ff 20 + jmp DWORD PTR \[eax\]
-[ ]*[a-f0-9]+: ff 25 db 09 00 00 + jmp DWORD PTR ds:0x9db
-[ ]*[a-f0-9]+: e9 5b ff ff ff + jmp 9db <bar>
+[ ]*[a-f0-9]+: ff 25 .. .. 00 00 + jmp DWORD PTR ds:.*
+[ ]*[a-f0-9]+: e9 5b ff ff ff + jmp .* <bar>
[ ]*[a-f0-9]+: b8 12 00 00 00 + mov eax,0x12
[ ]*[a-f0-9]+: 25 ff ff fb ff + and eax,0xfffbffff
[ ]*[a-f0-9]+: 25 ff ff fb ff + and eax,0xfffbffff
diff --git a/gas/testsuite/gas/i386/intel-suffix.d b/gas/testsuite/gas/i386/intel-suffix.d
index 5ac3209e212..7da6d6e6e68 100644
--- a/gas/testsuite/gas/i386/intel-suffix.d
+++ b/gas/testsuite/gas/i386/intel-suffix.d
@@ -1,5 +1,6 @@
#objdump: -dw
#name: Intel syntax w/ suffixes
+#warning_output: intel-suffix.e
.*: +file format .*
diff --git a/gas/testsuite/gas/i386/intel-suffix.e b/gas/testsuite/gas/i386/intel-suffix.e
new file mode 100644
index 00000000000..02f0eadcda7
--- /dev/null
+++ b/gas/testsuite/gas/i386/intel-suffix.e
@@ -0,0 +1,22 @@
+.*: Assembler messages:
+.*:7: Warning: .*suffix.*`shl'
+.*:7: Warning: NOTE: .*deprecated.*
+.*:8: Warning: .*suffix.*`shl'
+.*:10: Warning: .*suffix.*`sal'
+.*:11: Warning: .*suffix.*`sal'
+.*:13: Warning: .*suffix.*`sal'
+.*:14: Warning: .*suffix.*`sal'
+.*:16: Warning: .*suffix.*`rol'
+.*:17: Warning: .*suffix.*`rol'
+.*:19: Warning: .*suffix.*`rol'
+.*:20: Warning: .*suffix.*`rol'
+.*:26: Warning: .*suffix.*`shr'
+.*:27: Warning: .*suffix.*`shr'
+.*:29: Warning: .*suffix.*`sar'
+.*:30: Warning: .*suffix.*`sar'
+.*:32: Warning: .*suffix.*`sar'
+.*:33: Warning: .*suffix.*`sar'
+.*:35: Warning: .*suffix.*`ror'
+.*:36: Warning: .*suffix.*`ror'
+.*:38: Warning: .*suffix.*`ror'
+.*:39: Warning: .*suffix.*`ror'
diff --git a/gas/testsuite/gas/i386/intel.d b/gas/testsuite/gas/i386/intel.d
index 1ac6ae93cfe..5d2336d7d2e 100644
--- a/gas/testsuite/gas/i386/intel.d
+++ b/gas/testsuite/gas/i386/intel.d
@@ -201,8 +201,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c9 [ ]*leave
[ ]*[a-f0-9]+: ca 90 90 [ ]*lret \$0x9090
[ ]*[a-f0-9]+: cb [ ]*lret
-[ ]*[a-f0-9]+: ca 90 90 [ ]*lret \$0x9090
-[ ]*[a-f0-9]+: cb [ ]*lret
[ ]*[a-f0-9]+: cc [ ]*int3
[ ]*[a-f0-9]+: cd 90 [ ]*int \$0x90
[ ]*[a-f0-9]+: ce [ ]*into
@@ -222,18 +220,18 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: dd 90 90 90 90 90 [ ]*fstl -0x6f6f6f70\(%eax\)
[ ]*[a-f0-9]+: de 90 90 90 90 90 [ ]*ficoms -0x6f6f6f70\(%eax\)
[ ]*[a-f0-9]+: df 90 90 90 90 90 [ ]*fists -0x6f6f6f70\(%eax\)
-[ ]*[a-f0-9]+: e0 90 [ ]*loopne (0x)?260.*
-[ ]*[a-f0-9]+: e1 90 [ ]*loope (0x)?262.*
-[ ]*[a-f0-9]+: e2 90 [ ]*loop (0x)?264.*
-[ ]*[a-f0-9]+: e3 90 [ ]*jecxz (0x)?266.*
+[ ]*[a-f0-9]+: e0 90 [ ]*loopne .*
+[ ]*[a-f0-9]+: e1 90 [ ]*loope .*
+[ ]*[a-f0-9]+: e2 90 [ ]*loop .*
+[ ]*[a-f0-9]+: e3 90 [ ]*jecxz .*
[ ]*[a-f0-9]+: e4 90 [ ]*in \$0x90,%al
[ ]*[a-f0-9]+: e5 90 [ ]*in \$0x90,%eax
[ ]*[a-f0-9]+: e6 90 [ ]*out %al,\$0x90
[ ]*[a-f0-9]+: e7 90 [ ]*out %eax,\$0x90
-[ ]*[a-f0-9]+: e8 90 90 90 90 [ ]*call (0x)?90909373.*
-[ ]*[a-f0-9]+: e9 90 90 90 90 [ ]*jmp (0x)?90909378.*
+[ ]*[a-f0-9]+: e8 90 90 90 90 [ ]*call .*
+[ ]*[a-f0-9]+: e9 90 90 90 90 [ ]*jmp .*
[ ]*[a-f0-9]+: ea 90 90 90 90 90 90 [ ]*ljmp \$0x9090,\$0x90909090
-[ ]*[a-f0-9]+: eb 90 [ ]*jmp (0x)?281.*
+[ ]*[a-f0-9]+: eb 90 [ ]*jmp .*
[ ]*[a-f0-9]+: ec [ ]*in \(%dx\),%al
[ ]*[a-f0-9]+: ed [ ]*in \(%dx\),%eax
[ ]*[a-f0-9]+: ee [ ]*out %al,\(%dx\)
@@ -306,22 +304,22 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 0f 77 [ ]*emms
[ ]*[a-f0-9]+: 0f 7e 90 90 90 90 90 [ ]*movd %mm2,-0x6f6f6f70\(%eax\)
[ ]*[a-f0-9]+: 0f 7f 90 90 90 90 90 [ ]*movq %mm2,-0x6f6f6f70\(%eax\)
-[ ]*[a-f0-9]+: 0f 80 90 90 90 90 [ ]*jo (0x)?909094e6.*
-[ ]*[a-f0-9]+: 0f 81 90 90 90 90 [ ]*jno (0x)?909094ec.*
-[ ]*[a-f0-9]+: 0f 82 90 90 90 90 [ ]*jb (0x)?909094f2.*
-[ ]*[a-f0-9]+: 0f 83 90 90 90 90 [ ]*jae (0x)?909094f8.*
-[ ]*[a-f0-9]+: 0f 84 90 90 90 90 [ ]*je (0x)?909094fe.*
-[ ]*[a-f0-9]+: 0f 85 90 90 90 90 [ ]*jne (0x)?90909504.*
-[ ]*[a-f0-9]+: 0f 86 90 90 90 90 [ ]*jbe (0x)?9090950a.*
-[ ]*[a-f0-9]+: 0f 87 90 90 90 90 [ ]*ja (0x)?90909510.*
-[ ]*[a-f0-9]+: 0f 88 90 90 90 90 [ ]*js (0x)?90909516.*
-[ ]*[a-f0-9]+: 0f 89 90 90 90 90 [ ]*jns (0x)?9090951c.*
-[ ]*[a-f0-9]+: 0f 8a 90 90 90 90 [ ]*jp (0x)?90909522.*
-[ ]*[a-f0-9]+: 0f 8b 90 90 90 90 [ ]*jnp (0x)?90909528.*
-[ ]*[a-f0-9]+: 0f 8c 90 90 90 90 [ ]*jl (0x)?9090952e.*
-[ ]*[a-f0-9]+: 0f 8d 90 90 90 90 [ ]*jge (0x)?90909534.*
-[ ]*[a-f0-9]+: 0f 8e 90 90 90 90 [ ]*jle (0x)?9090953a.*
-[ ]*[a-f0-9]+: 0f 8f 90 90 90 90 [ ]*jg (0x)?90909540.*
+[ ]*[a-f0-9]+: 0f 80 90 90 90 90 [ ]*jo .*
+[ ]*[a-f0-9]+: 0f 81 90 90 90 90 [ ]*jno .*
+[ ]*[a-f0-9]+: 0f 82 90 90 90 90 [ ]*jb .*
+[ ]*[a-f0-9]+: 0f 83 90 90 90 90 [ ]*jae .*
+[ ]*[a-f0-9]+: 0f 84 90 90 90 90 [ ]*je .*
+[ ]*[a-f0-9]+: 0f 85 90 90 90 90 [ ]*jne .*
+[ ]*[a-f0-9]+: 0f 86 90 90 90 90 [ ]*jbe .*
+[ ]*[a-f0-9]+: 0f 87 90 90 90 90 [ ]*ja .*
+[ ]*[a-f0-9]+: 0f 88 90 90 90 90 [ ]*js .*
+[ ]*[a-f0-9]+: 0f 89 90 90 90 90 [ ]*jns .*
+[ ]*[a-f0-9]+: 0f 8a 90 90 90 90 [ ]*jp .*
+[ ]*[a-f0-9]+: 0f 8b 90 90 90 90 [ ]*jnp .*
+[ ]*[a-f0-9]+: 0f 8c 90 90 90 90 [ ]*jl .*
+[ ]*[a-f0-9]+: 0f 8d 90 90 90 90 [ ]*jge .*
+[ ]*[a-f0-9]+: 0f 8e 90 90 90 90 [ ]*jle .*
+[ ]*[a-f0-9]+: 0f 8f 90 90 90 90 [ ]*jg .*
[ ]*[a-f0-9]+: 0f 90 80 90 90 90 90 [ ]*seto -0x6f6f6f70\(%eax\)
[ ]*[a-f0-9]+: 0f 91 80 90 90 90 90 [ ]*setno -0x6f6f6f70\(%eax\)
[ ]*[a-f0-9]+: 0f 92 80 90 90 90 90 [ ]*setb -0x6f6f6f70\(%eax\)
@@ -523,14 +521,12 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 c9 [ ]*leavew
[ ]*[a-f0-9]+: 66 ca 90 90 [ ]*lretw \$0x9090
[ ]*[a-f0-9]+: 66 cb [ ]*lretw
-[ ]*[a-f0-9]+: 66 ca 90 90 [ ]*lretw \$0x9090
-[ ]*[a-f0-9]+: 66 cb [ ]*lretw
[ ]*[a-f0-9]+: 66 cf [ ]*iretw
[ ]*[a-f0-9]+: 66 d1 90 90 90 90 90 [ ]*rclw \$1,-0x6f6f6f70\(%eax\)
[ ]*[a-f0-9]+: 66 d3 90 90 90 90 90 [ ]*rclw %cl,-0x6f6f6f70\(%eax\)
[ ]*[a-f0-9]+: 66 e5 90 [ ]*in \$0x90,%ax
[ ]*[a-f0-9]+: 66 e7 90 [ ]*out %ax,\$0x90
-[ ]*[a-f0-9]+: 66 e8 8f 90 [ ]*callw (0x)?9922.*
+[ ]*[a-f0-9]+: 66 e8 8f 90 [ ]*callw .*
[ ]*[a-f0-9]+: 66 ea 90 90 90 90 [ ]*ljmpw \$0x9090,\$0x9090
[ ]*[a-f0-9]+: 66 ed [ ]*in \(%dx\),%ax
[ ]*[a-f0-9]+: 66 ef [ ]*out %ax,\(%dx\)
@@ -584,15 +580,15 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c3 [ ]*ret
[a-f0-9]+ <bar>:
-[ ]*[a-f0-9]+: e8 f9 ff ff ff [ ]*call 9d9 <gs_foo>
-[ ]*[a-f0-9]+: e8 f5 ff ff ff [ ]*call 9da <short_foo>
+[ ]*[a-f0-9]+: e8 f9 ff ff ff [ ]*call .* <gs_foo>
+[ ]*[a-f0-9]+: e8 f5 ff ff ff [ ]*call .* <short_foo>
[ ]*[a-f0-9]+: dd 1c d0 [ ]*fstpl \(%eax,%edx,8\)
[ ]*[a-f0-9]+: b9 00 00 00 00 [ ]*mov \$0x0,%ecx
[ ]*[a-f0-9]+: 88 04 16 [ ]*mov %al,\(%esi,%edx,1\)
[ ]*[a-f0-9]+: 88 04 32 [ ]*mov %al,\(%edx,%esi,1\)
[ ]*[a-f0-9]+: 88 04 56 [ ]*mov %al,\(%esi,%edx,2\)
[ ]*[a-f0-9]+: 88 04 56 [ ]*mov %al,\(%esi,%edx,2\)
-[ ]*[a-f0-9]+: eb 0c [ ]*jmp a07 <rot5>
+[ ]*[a-f0-9]+: eb 0c [ ]*jmp .* <rot5>
[ ]*[a-f0-9]+: 6c [ ]*insb \(%dx\),%es:\(%edi\)
[ ]*[a-f0-9]+: 66 0f c1 90 90 90 90 90 [ ]*xadd %dx,-0x6f6f6f70\(%eax\)
[ ]*[a-f0-9]+: 83 e0 f8 [ ]*and \$0xfffffff8,%eax
@@ -608,8 +604,8 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 2f [ ]*das
[ ]*[a-f0-9]+: ea 90 90 90 90 90 90 [ ]*ljmp \$0x9090,\$0x90909090
[ ]*[a-f0-9]+: 66 a5 [ ]*movsw %ds:\(%esi\),%es:\(%edi\)
-[ ]*[a-f0-9]+: 70 90 [ ]*jo 9be <foo\+0x9be>
-[ ]*[a-f0-9]+: 75 fe [ ]*jne a2e <rot5\+0x27>
+[ ]*[a-f0-9]+: 70 90 [ ]*jo .* <foo\+.*>
+[ ]*[a-f0-9]+: 75 fe [ ]*jne .* <rot5\+.*>
[ ]*[a-f0-9]+: 0f 6f 35 28 00 00 00 [ ]*movq 0x28,%mm6
[ ]*[a-f0-9]+: 03 3c c3 [ ]*add \(%ebx,%eax,8\),%edi
[ ]*[a-f0-9]+: 0f 6e 44 c3 04 [ ]*movd 0x4\(%ebx,%eax,8\),%mm0
@@ -622,8 +618,8 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 8b 84 43 00 40 00 00 [ ]*mov 0x4000\(%ebx,%eax,2\),%ax
[ ]*[a-f0-9]+: ff e0 [ ]*jmp \*%eax
[ ]*[a-f0-9]+: ff 20 [ ]*jmp \*\(%eax\)
-[ ]*[a-f0-9]+: ff 25 db 09 00 00 [ ]*jmp \*0x9db
-[ ]*[a-f0-9]+: e9 5b ff ff ff [ ]*jmp 9db <bar>
+[ ]*[a-f0-9]+: ff 25 .. .. 00 00 [ ]*jmp \*.*
+[ ]*[a-f0-9]+: e9 5b ff ff ff [ ]*jmp .* <bar>
[ ]*[a-f0-9]+: b8 12 00 00 00 [ ]*mov \$0x12,%eax
[ ]*[a-f0-9]+: 25 ff ff fb ff [ ]*and \$0xfffbffff,%eax
[ ]*[a-f0-9]+: 25 ff ff fb ff [ ]*and \$0xfffbffff,%eax
diff --git a/gas/testsuite/gas/i386/intel.s b/gas/testsuite/gas/i386/intel.s
index 9f816d95f81..ebf9bc261c0 100644
--- a/gas/testsuite/gas/i386/intel.s
+++ b/gas/testsuite/gas/i386/intel.s
@@ -195,8 +195,6 @@ foo:
leave
retf 0x9090
retf
- lret 0x9090
- lret
int3
int 0x90
into
@@ -517,8 +515,6 @@ foo:
leavew
retfw 0x9090
retfw
- lretw 0x9090
- lretw
iretw
rcl word ptr 0x90909090[eax]
rcl word ptr 0x90909090[eax], cl
diff --git a/gas/testsuite/gas/i386/intel16.d b/gas/testsuite/gas/i386/intel16.d
index 4adc41f27d1..2bdc445b023 100644
--- a/gas/testsuite/gas/i386/intel16.d
+++ b/gas/testsuite/gas/i386/intel16.d
@@ -1,5 +1,6 @@
#objdump: -dw -mi8086
#name: i386 intel16
+#warning_output: intel16.e
.*: +file format .*
diff --git a/gas/testsuite/gas/i386/intel16.e b/gas/testsuite/gas/i386/intel16.e
new file mode 100644
index 00000000000..614d00be061
--- /dev/null
+++ b/gas/testsuite/gas/i386/intel16.e
@@ -0,0 +1,10 @@
+.*: Assembler messages:
+.*:21: Warning: .*suffix.*`not'
+.*:21: Warning: NOTE: .*deprecated.*
+.*:22: Warning: .*suffix.*`not'
+.*:24: Warning: .*suffix.*`nop'
+.*:25: Warning: .*suffix.*`nop'
+.*:27: Warning: .*suffix.*`add'
+.*:28: Warning: .*suffix.*`add'
+.*:30: Warning: .*suffix.*`mov'
+.*:31: Warning: .*suffix.*`mov'
diff --git a/gas/testsuite/gas/i386/simd-intel.d b/gas/testsuite/gas/i386/simd-intel.d
index 5b72fd7ad4c..b8a5c83eea3 100644
--- a/gas/testsuite/gas/i386/simd-intel.d
+++ b/gas/testsuite/gas/i386/simd-intel.d
@@ -188,13 +188,9 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: f2 0f c2 38 10 cmpsd xmm7,QWORD PTR \[eax\],0x10
[ ]*[a-f0-9]+: f3 0f 2a c8 cvtsi2ss xmm1,eax
[ ]*[a-f0-9]+: f2 0f 2a c8 cvtsi2sd xmm1,eax
-[ ]*[a-f0-9]+: f3 0f 2a c8 cvtsi2ss xmm1,eax
-[ ]*[a-f0-9]+: f2 0f 2a c8 cvtsi2sd xmm1,eax
[ ]*[a-f0-9]+: f3 0f 2a 08 cvtsi2ss xmm1,DWORD PTR \[eax\]
[ ]*[a-f0-9]+: f3 0f 2a 08 cvtsi2ss xmm1,DWORD PTR \[eax\]
[ ]*[a-f0-9]+: f2 0f 2a 08 cvtsi2sd xmm1,DWORD PTR \[eax\]
[ ]*[a-f0-9]+: f2 0f 2a 08 cvtsi2sd xmm1,DWORD PTR \[eax\]
-[ ]*[a-f0-9]+: f3 0f 2a 08 cvtsi2ss xmm1,DWORD PTR \[eax\]
-[ ]*[a-f0-9]+: f2 0f 2a 08 cvtsi2sd xmm1,DWORD PTR \[eax\]
[ ]*[a-f0-9]+: 0f 2c 00 cvttps2pi mm0,QWORD PTR \[eax\]
#pass
diff --git a/gas/testsuite/gas/i386/simd-suffix.d b/gas/testsuite/gas/i386/simd-suffix.d
index ad78f76cfaf..8dbb6e7f221 100644
--- a/gas/testsuite/gas/i386/simd-suffix.d
+++ b/gas/testsuite/gas/i386/simd-suffix.d
@@ -188,12 +188,9 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: f2 0f c2 38 10 cmpsd \$0x10,\(%eax\),%xmm7
[ ]*[a-f0-9]+: f3 0f 2a c8 cvtsi2ssl %eax,%xmm1
[ ]*[a-f0-9]+: f2 0f 2a c8 cvtsi2sdl %eax,%xmm1
-[ ]*[a-f0-9]+: f3 0f 2a c8 cvtsi2ssl %eax,%xmm1
-[ ]*[a-f0-9]+: f2 0f 2a c8 cvtsi2sdl %eax,%xmm1
[ ]*[a-f0-9]+: f3 0f 2a 08 cvtsi2ssl \(%eax\),%xmm1
[ ]*[a-f0-9]+: f3 0f 2a 08 cvtsi2ssl \(%eax\),%xmm1
[ ]*[a-f0-9]+: f2 0f 2a 08 cvtsi2sdl \(%eax\),%xmm1
[ ]*[a-f0-9]+: f2 0f 2a 08 cvtsi2sdl \(%eax\),%xmm1
-[ ]*[a-f0-9]+: f3 0f 2a 08 cvtsi2ssl \(%eax\),%xmm1
-[ ]*[a-f0-9]+: f2 0f 2a 08 cvtsi2sdl \(%eax\),%xmm1
+[ ]*[a-f0-9]+: 0f 2c 00 cvttps2pi \(%eax\),%mm0
#pass
diff --git a/gas/testsuite/gas/i386/simd.d b/gas/testsuite/gas/i386/simd.d
index 4e709500863..e56767b3d47 100644
--- a/gas/testsuite/gas/i386/simd.d
+++ b/gas/testsuite/gas/i386/simd.d
@@ -187,13 +187,9 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: f2 0f c2 38 10 cmpsd \$0x10,\(%eax\),%xmm7
[ ]*[a-f0-9]+: f3 0f 2a c8 cvtsi2ss %eax,%xmm1
[ ]*[a-f0-9]+: f2 0f 2a c8 cvtsi2sd %eax,%xmm1
-[ ]*[a-f0-9]+: f3 0f 2a c8 cvtsi2ss %eax,%xmm1
-[ ]*[a-f0-9]+: f2 0f 2a c8 cvtsi2sd %eax,%xmm1
[ ]*[a-f0-9]+: f3 0f 2a 08 cvtsi2ss \(%eax\),%xmm1
[ ]*[a-f0-9]+: f3 0f 2a 08 cvtsi2ss \(%eax\),%xmm1
[ ]*[a-f0-9]+: f2 0f 2a 08 cvtsi2sd \(%eax\),%xmm1
[ ]*[a-f0-9]+: f2 0f 2a 08 cvtsi2sd \(%eax\),%xmm1
-[ ]*[a-f0-9]+: f3 0f 2a 08 cvtsi2ss \(%eax\),%xmm1
-[ ]*[a-f0-9]+: f2 0f 2a 08 cvtsi2sd \(%eax\),%xmm1
[ ]*[a-f0-9]+: 0f 2c 00 cvttps2pi \(%eax\),%mm0
#pass
diff --git a/gas/testsuite/gas/i386/simd.s b/gas/testsuite/gas/i386/simd.s
index 75cd440f2cf..5f38e27fcfc 100644
--- a/gas/testsuite/gas/i386/simd.s
+++ b/gas/testsuite/gas/i386/simd.s
@@ -193,12 +193,8 @@ cmpsd xmm6,xmm7,0x10
cmpsd xmm7,QWORD PTR [eax],0x10
cvtsi2ss xmm1,eax
cvtsi2sd xmm1,eax
-cvtsi2ssd xmm1,eax
-cvtsi2sdd xmm1,eax
cvtsi2ss xmm1,DWORD PTR [eax]
cvtsi2ss xmm1,[eax]
cvtsi2sd xmm1,DWORD PTR [eax]
cvtsi2sd xmm1,[eax]
-cvtsi2ssd xmm1,DWORD PTR [eax]
-cvtsi2sdd xmm1,DWORD PTR [eax]
cvttps2pi mm0,QWORD PTR[eax]
diff --git a/gas/testsuite/gas/i386/simd16.d b/gas/testsuite/gas/i386/simd16.d
index 5900c77d403..59b90b7f8e1 100644
--- a/gas/testsuite/gas/i386/simd16.d
+++ b/gas/testsuite/gas/i386/simd16.d
@@ -125,13 +125,9 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 67 f2 0f c2 38 10 cmpsd \$0x10,\(%eax\),%xmm7
[ ]*[a-f0-9]+: f3 0f 2a c8 cvtsi2ss %eax,%xmm1
[ ]*[a-f0-9]+: f2 0f 2a c8 cvtsi2sd %eax,%xmm1
-[ ]*[a-f0-9]+: f3 0f 2a c8 cvtsi2ss %eax,%xmm1
-[ ]*[a-f0-9]+: f2 0f 2a c8 cvtsi2sd %eax,%xmm1
[ ]*[a-f0-9]+: 67 f3 0f 2a 08 cvtsi2ss \(%eax\),%xmm1
[ ]*[a-f0-9]+: 67 f3 0f 2a 08 cvtsi2ss \(%eax\),%xmm1
[ ]*[a-f0-9]+: 67 f2 0f 2a 08 cvtsi2sd \(%eax\),%xmm1
[ ]*[a-f0-9]+: 67 f2 0f 2a 08 cvtsi2sd \(%eax\),%xmm1
-[ ]*[a-f0-9]+: 67 f3 0f 2a 08 cvtsi2ss \(%eax\),%xmm1
-[ ]*[a-f0-9]+: 67 f2 0f 2a 08 cvtsi2sd \(%eax\),%xmm1
[ ]*[a-f0-9]+: 67 0f 2c 00 cvttps2pi \(%eax\),%mm0
#pass
diff --git a/gas/testsuite/gas/i386/x86-64-avx-intel.d b/gas/testsuite/gas/i386/x86-64-avx-intel.d
index dd7cbd6a62c..dadf711ffd4 100644
--- a/gas/testsuite/gas/i386/x86-64-avx-intel.d
+++ b/gas/testsuite/gas/i386/x86-64-avx-intel.d
@@ -2855,10 +2855,8 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c4 e1 fb 2c 09 vcvttsd2si rcx,QWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c4 e1 db 2a f1 vcvtsi2sd xmm6,xmm4,rcx
[ ]*[a-f0-9]+: c4 e1 db 2a 31 vcvtsi2sd xmm6,xmm4,QWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e1 db 2a 31 vcvtsi2sd xmm6,xmm4,QWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c4 e1 da 2a f1 vcvtsi2ss xmm6,xmm4,rcx
[ ]*[a-f0-9]+: c4 e1 da 2a 31 vcvtsi2ss xmm6,xmm4,QWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e1 da 2a 31 vcvtsi2ss xmm6,xmm4,QWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c4 e3 d9 22 f1 07 vpinsrq xmm6,xmm4,rcx,0x7
[ ]*[a-f0-9]+: c4 e3 d9 22 31 07 vpinsrq xmm6,xmm4,QWORD PTR \[rcx\],0x7
[ ]*[a-f0-9]+: c4 e3 d9 22 31 07 vpinsrq xmm6,xmm4,QWORD PTR \[rcx\],0x7
diff --git a/gas/testsuite/gas/i386/x86-64-avx-scalar-intel.d b/gas/testsuite/gas/i386/x86-64-avx-scalar-intel.d
index c87dd52dc04..54944ac66e9 100644
--- a/gas/testsuite/gas/i386/x86-64-avx-scalar-intel.d
+++ b/gas/testsuite/gas/i386/x86-64-avx-scalar-intel.d
@@ -263,10 +263,8 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c4 e1 ff 2c 09 vcvttsd2si rcx,QWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c4 e1 df 2a f1 vcvtsi2sd xmm6,xmm4,rcx
[ ]*[a-f0-9]+: c4 e1 df 2a 31 vcvtsi2sd xmm6,xmm4,QWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e1 df 2a 31 vcvtsi2sd xmm6,xmm4,QWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c4 e1 de 2a f1 vcvtsi2ss xmm6,xmm4,rcx
[ ]*[a-f0-9]+: c4 e1 de 2a 31 vcvtsi2ss xmm6,xmm4,QWORD PTR \[rcx\]
-[ ]*[a-f0-9]+: c4 e1 de 2a 31 vcvtsi2ss xmm6,xmm4,QWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c5 cf c2 d4 07 vcmpordsd xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c5 cf c2 11 07 vcmpordsd xmm2,xmm6,QWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c5 cf c2 11 07 vcmpordsd xmm2,xmm6,QWORD PTR \[rcx\]
diff --git a/gas/testsuite/gas/i386/x86-64-avx-scalar.d b/gas/testsuite/gas/i386/x86-64-avx-scalar.d
index 5b2244d796f..5ed10d6dcf7 100644
--- a/gas/testsuite/gas/i386/x86-64-avx-scalar.d
+++ b/gas/testsuite/gas/i386/x86-64-avx-scalar.d
@@ -262,10 +262,8 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c4 e1 ff 2c 09 vcvttsd2si \(%rcx\),%rcx
[ ]*[a-f0-9]+: c4 e1 df 2a f1 vcvtsi2sd %rcx,%xmm4,%xmm6
[ ]*[a-f0-9]+: c4 e1 df 2a 31 vcvtsi2sdq \(%rcx\),%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e1 df 2a 31 vcvtsi2sdq \(%rcx\),%xmm4,%xmm6
[ ]*[a-f0-9]+: c4 e1 de 2a f1 vcvtsi2ss %rcx,%xmm4,%xmm6
[ ]*[a-f0-9]+: c4 e1 de 2a 31 vcvtsi2ssq \(%rcx\),%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e1 de 2a 31 vcvtsi2ssq \(%rcx\),%xmm4,%xmm6
[ ]*[a-f0-9]+: c5 cf c2 d4 07 vcmpordsd %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cf c2 11 07 vcmpordsd \(%rcx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cf c2 11 07 vcmpordsd \(%rcx\),%xmm6,%xmm2
diff --git a/gas/testsuite/gas/i386/x86-64-avx-scalar.s b/gas/testsuite/gas/i386/x86-64-avx-scalar.s
index aa3f2773b2d..36efd459c05 100644
--- a/gas/testsuite/gas/i386/x86-64-avx-scalar.s
+++ b/gas/testsuite/gas/i386/x86-64-avx-scalar.s
@@ -307,12 +307,10 @@ _start:
vcvttsd2si rcx,[rcx]
# Tests for op regq/mem64, xmm, xmm
- vcvtsi2sdq xmm6,xmm4,rcx
- vcvtsi2sdq xmm6,xmm4,QWORD PTR [rcx]
- vcvtsi2sdq xmm6,xmm4,[rcx]
- vcvtsi2ssq xmm6,xmm4,rcx
- vcvtsi2ssq xmm6,xmm4,QWORD PTR [rcx]
- vcvtsi2ssq xmm6,xmm4,[rcx]
+ vcvtsi2sd xmm6,xmm4,rcx
+ vcvtsi2sd xmm6,xmm4,QWORD PTR [rcx]
+ vcvtsi2ss xmm6,xmm4,rcx
+ vcvtsi2ss xmm6,xmm4,QWORD PTR [rcx]
# Tests for op imm8, xmm/mem64, xmm, xmm
vcmpsd xmm2,xmm6,xmm4,7
diff --git a/gas/testsuite/gas/i386/x86-64-avx.d b/gas/testsuite/gas/i386/x86-64-avx.d
index 336f87957a8..80984cd80d3 100644
--- a/gas/testsuite/gas/i386/x86-64-avx.d
+++ b/gas/testsuite/gas/i386/x86-64-avx.d
@@ -2854,10 +2854,8 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c4 e1 fb 2c 09 vcvttsd2si \(%rcx\),%rcx
[ ]*[a-f0-9]+: c4 e1 db 2a f1 vcvtsi2sd %rcx,%xmm4,%xmm6
[ ]*[a-f0-9]+: c4 e1 db 2a 31 vcvtsi2sdq \(%rcx\),%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e1 db 2a 31 vcvtsi2sdq \(%rcx\),%xmm4,%xmm6
[ ]*[a-f0-9]+: c4 e1 da 2a f1 vcvtsi2ss %rcx,%xmm4,%xmm6
[ ]*[a-f0-9]+: c4 e1 da 2a 31 vcvtsi2ssq \(%rcx\),%xmm4,%xmm6
-[ ]*[a-f0-9]+: c4 e1 da 2a 31 vcvtsi2ssq \(%rcx\),%xmm4,%xmm6
[ ]*[a-f0-9]+: c4 e3 d9 22 f1 07 vpinsrq \$0x7,%rcx,%xmm4,%xmm6
[ ]*[a-f0-9]+: c4 e3 d9 22 31 07 vpinsrq \$0x7,\(%rcx\),%xmm4,%xmm6
[ ]*[a-f0-9]+: c4 e3 d9 22 31 07 vpinsrq \$0x7,\(%rcx\),%xmm4,%xmm6
diff --git a/gas/testsuite/gas/i386/x86-64-avx.s b/gas/testsuite/gas/i386/x86-64-avx.s
index c7355dcaa8b..d84482e6897 100644
--- a/gas/testsuite/gas/i386/x86-64-avx.s
+++ b/gas/testsuite/gas/i386/x86-64-avx.s
@@ -3069,12 +3069,10 @@ _start:
vcvttsd2si rcx,[rcx]
# Tests for op regq/mem64, xmm, xmm
- vcvtsi2sdq xmm6,xmm4,rcx
- vcvtsi2sdq xmm6,xmm4,QWORD PTR [rcx]
- vcvtsi2sdq xmm6,xmm4,[rcx]
- vcvtsi2ssq xmm6,xmm4,rcx
- vcvtsi2ssq xmm6,xmm4,QWORD PTR [rcx]
- vcvtsi2ssq xmm6,xmm4,[rcx]
+ vcvtsi2sd xmm6,xmm4,rcx
+ vcvtsi2sd xmm6,xmm4,QWORD PTR [rcx]
+ vcvtsi2ss xmm6,xmm4,rcx
+ vcvtsi2ss xmm6,xmm4,QWORD PTR [rcx]
# Tests for op imm8, regq/mem64, xmm, xmm
vpinsrq xmm6,xmm4,rcx,7
diff --git a/gas/testsuite/gas/i386/x86-64-branch.d b/gas/testsuite/gas/i386/x86-64-branch.d
index aee4bf83b42..4ef48acd4ca 100644
--- a/gas/testsuite/gas/i386/x86-64-branch.d
+++ b/gas/testsuite/gas/i386/x86-64-branch.d
@@ -28,13 +28,9 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 2e 74 00[ ]+je,pn +[0-9a-fx]+ <.*>
[0-9a-f]+ <label>:
[ ]*[a-f0-9]+: ff d0 call \*%rax
-[ ]*[a-f0-9]+: ff d0 call \*%rax
-[ ]*[a-f0-9]+: 66 ff d0 data16 call \*%rax
[ ]*[a-f0-9]+: 66 ff d0 data16 call \*%rax
[ ]*[a-f0-9]+: 66 ff 10 data16 call \*\(%rax\)
[ ]*[a-f0-9]+: ff e0 jmp \*%rax
-[ ]*[a-f0-9]+: ff e0 jmp \*%rax
-[ ]*[a-f0-9]+: 66 ff e0 data16 jmp \*%rax
[ ]*[a-f0-9]+: 66 ff e0 data16 jmp \*%rax
[ ]*[a-f0-9]+: 66 ff 20 data16 jmp \*\(%rax\)
[ ]*[a-f0-9]+: e8 .. 00 (00|10) 00 call [0-9a-fx]* <.*>
diff --git a/gas/testsuite/gas/i386/x86-64-branch.s b/gas/testsuite/gas/i386/x86-64-branch.s
index 75db8f59994..3df0cd56f62 100644
--- a/gas/testsuite/gas/i386/x86-64-branch.s
+++ b/gas/testsuite/gas/i386/x86-64-branch.s
@@ -28,15 +28,11 @@ label:
.intel_syntax noprefix
call rax
- callq rax
call ax
- callw ax
- callw [rax]
+ call word ptr [rax]
jmp rax
- jmpq rax
jmp ax
- jmpw ax
- jmpw [rax]
+ jmp word ptr [rax]
call 0x100040
jmp 0x100040
retw
diff --git a/gas/testsuite/gas/i386/x86-64-gottpoff.s b/gas/testsuite/gas/i386/x86-64-gottpoff.s
index 0335ec5debf..e39010afc69 100644
--- a/gas/testsuite/gas/i386/x86-64-gottpoff.s
+++ b/gas/testsuite/gas/i386/x86-64-gottpoff.s
@@ -8,11 +8,11 @@ _start:
.intel_syntax noprefix
- addq rax, QWORD PTR [rip + foo@GOTTPOFF]
- movq rax, QWORD PTR [rip + foo@GOTTPOFF]
+ add rax, QWORD PTR [rip + foo@GOTTPOFF]
+ mov rax, QWORD PTR [rip + foo@GOTTPOFF]
- addq r16, QWORD PTR [rip + foo@GOTTPOFF]
- movq r20, QWORD PTR [rip + foo@GOTTPOFF]
+ add r16, QWORD PTR [rip + foo@GOTTPOFF]
+ mov r20, QWORD PTR [rip + foo@GOTTPOFF]
.att_syntax prefix
@@ -21,5 +21,5 @@ _start:
.intel_syntax noprefix
- addq r16, QWORD PTR [rip + foo@GOTTPOFF], r8
- addq r12, rax, QWORD PTR [rip + foo@GOTTPOFF]
+ add r16, QWORD PTR [rip + foo@GOTTPOFF], r8
+ add r12, rax, QWORD PTR [rip + foo@GOTTPOFF]
diff --git a/gas/testsuite/gas/i386/x86-64-lkgs-intel.d b/gas/testsuite/gas/i386/x86-64-lkgs-intel.d
index 58965777c6c..a01472bfeeb 100644
--- a/gas/testsuite/gas/i386/x86-64-lkgs-intel.d
+++ b/gas/testsuite/gas/i386/x86-64-lkgs-intel.d
@@ -16,7 +16,6 @@ Disassembly of section \.text:
\s*[a-f0-9]+:\s*f2 0f 00 b2 00 ff ff ff\s+lkgs WORD PTR \[rdx-0x100\]
\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs r12d
\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs r12d
-\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs r12d
\s*[a-f0-9]+:\s*f2 42 0f 00 b4 f5 00 00 00 10\s+lkgs WORD PTR \[rbp\+r14\*8\+0x10000000\]
\s*[a-f0-9]+:\s*f2 41 0f 00 31\s+lkgs WORD PTR \[r9\]
\s*[a-f0-9]+:\s*f2 0f 00 b1 fe 00 00 00\s+lkgs WORD PTR \[rcx\+0xfe\]
diff --git a/gas/testsuite/gas/i386/x86-64-lkgs.d b/gas/testsuite/gas/i386/x86-64-lkgs.d
index dad3453cc9e..dadcaa6bc4f 100644
--- a/gas/testsuite/gas/i386/x86-64-lkgs.d
+++ b/gas/testsuite/gas/i386/x86-64-lkgs.d
@@ -16,7 +16,6 @@ Disassembly of section \.text:
\s*[a-f0-9]+:\s*f2 0f 00 b2 00 ff ff ff\s+lkgs -0x100\(%rdx\)
\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs %r12d
\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs %r12d
-\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs %r12d
\s*[a-f0-9]+:\s*f2 42 0f 00 b4 f5 00 00 00 10\s+lkgs 0x10000000\(%rbp,%r14,8\)
\s*[a-f0-9]+:\s*f2 41 0f 00 31\s+lkgs \(%r9\)
\s*[a-f0-9]+:\s*f2 0f 00 b1 fe 00 00 00\s+lkgs 0xfe\(%rcx\)
diff --git a/gas/testsuite/gas/i386/x86-64-lkgs.s b/gas/testsuite/gas/i386/x86-64-lkgs.s
index a02d3a7446a..de20ef9aef0 100644
--- a/gas/testsuite/gas/i386/x86-64-lkgs.s
+++ b/gas/testsuite/gas/i386/x86-64-lkgs.s
@@ -13,7 +13,6 @@ _start:
.intel_syntax noprefix
lkgs r12 #LKGS
lkgs r12w #LKGS
- lkgsw r12w #LKGS
lkgs WORD PTR [rbp+r14*8+0x10000000] #LKGS
lkgs WORD PTR [r9] #LKGS
lkgs WORD PTR [rcx+254] #LKGS Disp32(fe000000)
diff --git a/gas/testsuite/gas/i386/x86-64-simd-intel.d b/gas/testsuite/gas/i386/x86-64-simd-intel.d
index 9ec34ed4620..ea7b6ef3249 100644
--- a/gas/testsuite/gas/i386/x86-64-simd-intel.d
+++ b/gas/testsuite/gas/i386/x86-64-simd-intel.d
@@ -132,18 +132,10 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: f3 0f 5b 0d 78 56 34 12 cvttps2dq xmm1,XMMWORD PTR \[rip\+0x12345678\] # [0-9a-f]+ <_start\+0x[0-9a-f]+>
[ ]*[a-f0-9]+: f3 0f 2a c8 cvtsi2ss xmm1,eax
[ ]*[a-f0-9]+: f2 0f 2a c8 cvtsi2sd xmm1,eax
-[ ]*[a-f0-9]+: f3 0f 2a c8 cvtsi2ss xmm1,eax
-[ ]*[a-f0-9]+: f2 0f 2a c8 cvtsi2sd xmm1,eax
-[ ]*[a-f0-9]+: f3 48 0f 2a c8 cvtsi2ss xmm1,rax
-[ ]*[a-f0-9]+: f2 48 0f 2a c8 cvtsi2sd xmm1,rax
[ ]*[a-f0-9]+: f3 48 0f 2a c8 cvtsi2ss xmm1,rax
[ ]*[a-f0-9]+: f2 48 0f 2a c8 cvtsi2sd xmm1,rax
[ ]*[a-f0-9]+: f3 0f 2a 08 cvtsi2ss xmm1,DWORD PTR \[rax\]
[ ]*[a-f0-9]+: f2 0f 2a 08 cvtsi2sd xmm1,DWORD PTR \[rax\]
-[ ]*[a-f0-9]+: f3 0f 2a 08 cvtsi2ss xmm1,DWORD PTR \[rax\]
-[ ]*[a-f0-9]+: f2 0f 2a 08 cvtsi2sd xmm1,DWORD PTR \[rax\]
-[ ]*[a-f0-9]+: f3 48 0f 2a 08 cvtsi2ss xmm1,QWORD PTR \[rax\]
-[ ]*[a-f0-9]+: f2 48 0f 2a 08 cvtsi2sd xmm1,QWORD PTR \[rax\]
[ ]*[a-f0-9]+: f3 48 0f 2a 08 cvtsi2ss xmm1,QWORD PTR \[rax\]
[ ]*[a-f0-9]+: f2 48 0f 2a 08 cvtsi2sd xmm1,QWORD PTR \[rax\]
[ ]*[a-f0-9]+: f2 0f 7c 0d 78 56 34 12 haddps xmm1,XMMWORD PTR \[rip\+0x12345678\] # [0-9a-f]+ <_start\+0x[0-9a-f]+>
diff --git a/gas/testsuite/gas/i386/x86-64-simd-suffix.d b/gas/testsuite/gas/i386/x86-64-simd-suffix.d
index e52de1be595..9fb6572a469 100644
--- a/gas/testsuite/gas/i386/x86-64-simd-suffix.d
+++ b/gas/testsuite/gas/i386/x86-64-simd-suffix.d
@@ -132,18 +132,10 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: f3 0f 5b 0d 78 56 34 12 cvttps2dq 0x12345678\(%rip\),%xmm1 # [0-9a-f]+ <_start\+0x[0-9a-f]+>
[ ]*[a-f0-9]+: f3 0f 2a c8 cvtsi2ssl %eax,%xmm1
[ ]*[a-f0-9]+: f2 0f 2a c8 cvtsi2sdl %eax,%xmm1
-[ ]*[a-f0-9]+: f3 0f 2a c8 cvtsi2ssl %eax,%xmm1
-[ ]*[a-f0-9]+: f2 0f 2a c8 cvtsi2sdl %eax,%xmm1
-[ ]*[a-f0-9]+: f3 48 0f 2a c8 cvtsi2ssq %rax,%xmm1
-[ ]*[a-f0-9]+: f2 48 0f 2a c8 cvtsi2sdq %rax,%xmm1
[ ]*[a-f0-9]+: f3 48 0f 2a c8 cvtsi2ssq %rax,%xmm1
[ ]*[a-f0-9]+: f2 48 0f 2a c8 cvtsi2sdq %rax,%xmm1
[ ]*[a-f0-9]+: f3 0f 2a 08 cvtsi2ssl \(%rax\),%xmm1
[ ]*[a-f0-9]+: f2 0f 2a 08 cvtsi2sdl \(%rax\),%xmm1
-[ ]*[a-f0-9]+: f3 0f 2a 08 cvtsi2ssl \(%rax\),%xmm1
-[ ]*[a-f0-9]+: f2 0f 2a 08 cvtsi2sdl \(%rax\),%xmm1
-[ ]*[a-f0-9]+: f3 48 0f 2a 08 cvtsi2ssq \(%rax\),%xmm1
-[ ]*[a-f0-9]+: f2 48 0f 2a 08 cvtsi2sdq \(%rax\),%xmm1
[ ]*[a-f0-9]+: f3 48 0f 2a 08 cvtsi2ssq \(%rax\),%xmm1
[ ]*[a-f0-9]+: f2 48 0f 2a 08 cvtsi2sdq \(%rax\),%xmm1
[ ]*[a-f0-9]+: f2 0f 7c 0d 78 56 34 12 haddps 0x12345678\(%rip\),%xmm1 # [0-9a-f]+ <_start\+0x[0-9a-f]+>
diff --git a/gas/testsuite/gas/i386/x86-64-simd.d b/gas/testsuite/gas/i386/x86-64-simd.d
index e93950a7d73..22aa38e6aea 100644
--- a/gas/testsuite/gas/i386/x86-64-simd.d
+++ b/gas/testsuite/gas/i386/x86-64-simd.d
@@ -131,18 +131,10 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: f3 0f 5b 0d 78 56 34 12 cvttps2dq 0x12345678\(%rip\),%xmm1 # [0-9a-f]+ <_start\+0x[0-9a-f]+>
[ ]*[a-f0-9]+: f3 0f 2a c8 cvtsi2ss %eax,%xmm1
[ ]*[a-f0-9]+: f2 0f 2a c8 cvtsi2sd %eax,%xmm1
-[ ]*[a-f0-9]+: f3 0f 2a c8 cvtsi2ss %eax,%xmm1
-[ ]*[a-f0-9]+: f2 0f 2a c8 cvtsi2sd %eax,%xmm1
-[ ]*[a-f0-9]+: f3 48 0f 2a c8 cvtsi2ss %rax,%xmm1
-[ ]*[a-f0-9]+: f2 48 0f 2a c8 cvtsi2sd %rax,%xmm1
[ ]*[a-f0-9]+: f3 48 0f 2a c8 cvtsi2ss %rax,%xmm1
[ ]*[a-f0-9]+: f2 48 0f 2a c8 cvtsi2sd %rax,%xmm1
[ ]*[a-f0-9]+: f3 0f 2a 08 cvtsi2ssl \(%rax\),%xmm1
[ ]*[a-f0-9]+: f2 0f 2a 08 cvtsi2sdl \(%rax\),%xmm1
-[ ]*[a-f0-9]+: f3 0f 2a 08 cvtsi2ssl \(%rax\),%xmm1
-[ ]*[a-f0-9]+: f2 0f 2a 08 cvtsi2sdl \(%rax\),%xmm1
-[ ]*[a-f0-9]+: f3 48 0f 2a 08 cvtsi2ssq \(%rax\),%xmm1
-[ ]*[a-f0-9]+: f2 48 0f 2a 08 cvtsi2sdq \(%rax\),%xmm1
[ ]*[a-f0-9]+: f3 48 0f 2a 08 cvtsi2ssq \(%rax\),%xmm1
[ ]*[a-f0-9]+: f2 48 0f 2a 08 cvtsi2sdq \(%rax\),%xmm1
[ ]*[a-f0-9]+: f2 0f 7c 0d 78 56 34 12 haddps 0x12345678\(%rip\),%xmm1 # [0-9a-f]+ <_start\+0x[0-9a-f]+>
diff --git a/gas/testsuite/gas/i386/x86-64-simd.s b/gas/testsuite/gas/i386/x86-64-simd.s
index d74cb119ae9..928b28f8e41 100644
--- a/gas/testsuite/gas/i386/x86-64-simd.s
+++ b/gas/testsuite/gas/i386/x86-64-simd.s
@@ -134,20 +134,12 @@ cvtps2pd xmm1,QWORD PTR [rip+0x12345678]
cvttps2dq xmm1,XMMWORD PTR [rip+0x12345678]
cvtsi2ss xmm1,eax
cvtsi2sd xmm1,eax
-cvtsi2ssd xmm1,eax
-cvtsi2sdd xmm1,eax
cvtsi2ss xmm1,rax
cvtsi2sd xmm1,rax
-cvtsi2ssq xmm1,rax
-cvtsi2sdq xmm1,rax
cvtsi2ss xmm1,DWORD PTR [rax]
cvtsi2sd xmm1,DWORD PTR [rax]
-cvtsi2ssd xmm1,DWORD PTR [rax]
-cvtsi2sdd xmm1,DWORD PTR [rax]
cvtsi2ss xmm1,QWORD PTR [rax]
cvtsi2sd xmm1,QWORD PTR [rax]
-cvtsi2ssq xmm1,QWORD PTR [rax]
-cvtsi2sdq xmm1,QWORD PTR [rax]
haddps xmm1,XMMWORD PTR [rip+0x12345678]
movdqu XMMWORD PTR [rip+0x12345678],xmm1
movdqu xmm1,XMMWORD PTR [rip+0x12345678]
diff --git a/gas/testsuite/gas/i386/x86-64-sse2avx.s b/gas/testsuite/gas/i386/x86-64-sse2avx.s
index f08115ab742..1349594874e 100644
--- a/gas/testsuite/gas/i386/x86-64-sse2avx.s
+++ b/gas/testsuite/gas/i386/x86-64-sse2avx.s
@@ -1340,10 +1340,10 @@ _start:
cvttsd2si rcx,QWORD PTR [rcx]
# Tests for op regq/mem64, xmm[, xmm]
- cvtsi2sdq xmm4,rcx
- cvtsi2sdq xmm4,QWORD PTR [rcx]
- cvtsi2ssq xmm4,rcx
- cvtsi2ssq xmm4,QWORD PTR [rcx]
+ cvtsi2sd xmm4,rcx
+ cvtsi2sd xmm4,QWORD PTR [rcx]
+ cvtsi2ss xmm4,rcx
+ cvtsi2ss xmm4,QWORD PTR [rcx]
# Tests for op imm8, regq/mem64, xmm[, xmm]
pinsrq xmm4,rcx,100
diff --git a/gas/testsuite/gas/i386/x86-64-tlsdesc.s b/gas/testsuite/gas/i386/x86-64-tlsdesc.s
index 91f8d23dca4..17091df912a 100644
--- a/gas/testsuite/gas/i386/x86-64-tlsdesc.s
+++ b/gas/testsuite/gas/i386/x86-64-tlsdesc.s
@@ -7,7 +7,7 @@ _start:
.intel_syntax noprefix
- leaq rax, QWORD PTR [rip + foo@TLSDESC]
+ lea rax, QWORD PTR [rip + foo@TLSDESC]
- leaq r16, QWORD PTR [rip + foo@TLSDESC]
- leaq r20, QWORD PTR [rip + foo@TLSDESC]
+ lea r16, QWORD PTR [rip + foo@TLSDESC]
+ lea r20, QWORD PTR [rip + foo@TLSDESC]
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index fb4e78df3a2..f41b2a5ed36 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -487,6 +487,7 @@ static bitfield opcode_modifiers[] =
BITFIELD (Disp8MemShift),
BITFIELD (Optimize),
BITFIELD (Dialect),
+ BITFIELD (IntelSuffix),
BITFIELD (ISA64),
BITFIELD (NoEgpr),
BITFIELD (NF),
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index b63ad7c13f5..295ae4ceedf 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -733,6 +733,9 @@ enum
#define ATT_MNEMONIC 3
Dialect,
+ /* Mnemonic suffix permitted in Intel syntax. */
+ IntelSuffix,
+
/* ISA64: Don't change the order without other code adjustments.
0: Common to AMD64 and Intel64.
1: AMD64.
@@ -800,6 +803,7 @@ typedef struct i386_opcode_modifier
unsigned int disp8memshift:3;
unsigned int optimize:1;
unsigned int dialect:2;
+ unsigned int intelsuffix:1;
unsigned int isa64:2;
unsigned int noegpr:1;
unsigned int nf:1;
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index b2c50752bd5..144a7f40c73 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -235,30 +235,30 @@ movzx, 0xfb6, i386, W|Modrm|No_lSuf|No_sSuf|No_qSuf, { Reg8|Reg16|Unspecified|Ba
// Push instructions.
push, 0x50, No64, ImplicitStackOp|No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32 }
push, 0xff/6, No64, Modrm|ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32|Unspecified|BaseIndex }
-push, 0x6a, i186&No64, ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Imm8S }
-push, 0x68, i186&No64, ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Imm16|Imm32 }
-push, 0x6, No64, ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { SReg }
+push, 0x6a, i186&No64, ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf|IntelSuffix, { Imm8S }
+push, 0x68, i186&No64, ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf|IntelSuffix, { Imm16|Imm32 }
+push, 0x6, No64, ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf|IntelSuffix, { SReg }
// In 64bit mode, the operand size is implicitly 64bit.
push, 0x50, x64, ImplicitStackOp|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Reg16|Reg64 }
pushp, 0x50, APX_F, ImplicitStackOp|No_bSuf|No_wSuf|No_lSuf|No_sSuf|Rex2, { Reg64 }
push, 0xff/6, x64, Modrm|ImplicitStackOp|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Reg16|Reg64|Unspecified|BaseIndex }
-push, 0x6a, x64, ImplicitStackOp|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Imm8S }
-push, 0x68, x64, ImplicitStackOp|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Imm16|Imm32S }
-push, 0xfa0, x64, ImplicitStackOp|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { SReg }
+push, 0x6a, x64, ImplicitStackOp|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64|IntelSuffix, { Imm8S }
+push, 0x68, x64, ImplicitStackOp|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64|IntelSuffix, { Imm16|Imm32S }
+push, 0xfa0, x64, ImplicitStackOp|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64|IntelSuffix, { SReg }
-pusha, 0x60, i186&No64, ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf, {}
+pusha, 0x60, i186&No64, ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf|IntelSuffix, {}
// Pop instructions.
pop, 0x58, No64, ImplicitStackOp|No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32 }
pop, 0x8f/0, No64, Modrm|ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32|Unspecified|BaseIndex }
-pop, 0x7, No64, ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { SReg }
+pop, 0x7, No64, ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf|IntelSuffix, { SReg }
// In 64bit mode, the operand size is implicitly 64bit.
pop, 0x58, x64, ImplicitStackOp|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Reg16|Reg64 }
popp, 0x58, APX_F, ImplicitStackOp|No_bSuf|No_wSuf|No_lSuf|No_sSuf|Rex2, { Reg64 }
pop, 0x8f/0, x64, Modrm|ImplicitStackOp|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Reg16|Reg64|Unspecified|BaseIndex }
-pop, 0xfa1, x64, ImplicitStackOp|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { SReg }
+pop, 0xfa1, x64, ImplicitStackOp|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64|IntelSuffix, { SReg }
-popa, 0x61, i186&No64, ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf, {}
+popa, 0x61, i186&No64, ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf|IntelSuffix, {}
// Exchange instructions.
// xchg commutes: we allow both operand orders.
@@ -270,12 +270,12 @@ xchg, 0x86, 0, D|W|C|CheckOperandSize|Modrm|No_sSuf|HLEPrefixAny, { Reg8|Reg16|R
// In/out from ports.
in, 0xe4, 0, W|No_sSuf|No_qSuf, { Imm8, Acc|Byte|Word|Dword }
in, 0xec, 0, W|No_sSuf|No_qSuf, { InOutPortReg, Acc|Byte|Word|Dword }
-in, 0xe4, 0, W|No_sSuf|No_qSuf, { Imm8 }
-in, 0xec, 0, W|No_sSuf|No_qSuf, { InOutPortReg }
+in, 0xe4, 0, W|No_sSuf|No_qSuf|IntelSuffix, { Imm8 }
+in, 0xec, 0, W|No_sSuf|No_qSuf|IntelSuffix, { InOutPortReg }
out, 0xe6, 0, W|No_sSuf|No_qSuf, { Acc|Byte|Word|Dword, Imm8 }
out, 0xee, 0, W|No_sSuf|No_qSuf, { Acc|Byte|Word|Dword, InOutPortReg }
-out, 0xe6, 0, W|No_sSuf|No_qSuf, { Imm8 }
-out, 0xee, 0, W|No_sSuf|No_qSuf, { InOutPortReg }
+out, 0xe6, 0, W|No_sSuf|No_qSuf|IntelSuffix, { Imm8 }
+out, 0xee, 0, W|No_sSuf|No_qSuf|IntelSuffix, { InOutPortReg }
// Load effective address.
lea, 0x8d, 0, Modrm|Anysize|No_bSuf|No_sSuf|Optimize, { BaseIndex, Reg16|Reg32|Reg64 }
@@ -300,10 +300,10 @@ lahf, 0x9f, No64, NoSuf, {}
lahf, 0x9f, LAHF_SAHF, NoSuf, {}
sahf, 0x9e, No64, NoSuf, {}
sahf, 0x9e, LAHF_SAHF, NoSuf, {}
-pushf, 0x9c, No64, ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf, {}
-pushf, 0x9c, x64, ImplicitStackOp|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, {}
-popf, 0x9d, No64, ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf, {}
-popf, 0x9d, x64, ImplicitStackOp|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, {}
+pushf, 0x9c, No64, ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf|IntelSuffix, {}
+pushf, 0x9c, x64, ImplicitStackOp|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64|IntelSuffix, {}
+popf, 0x9d, No64, ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf|IntelSuffix, {}
+popf, 0x9d, x64, ImplicitStackOp|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64|IntelSuffix, {}
stc, 0xf9, 0, NoSuf, {}
std, 0xfd, 0, NoSuf, {}
sti, 0xfb, 0, NoSuf, {}
@@ -461,14 +461,14 @@ sh<shd>d, 0x0fa5 | <shd:opc>, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Re
<shd>
// Control transfer instructions.
-call, 0xe8, No64, JumpDword|ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf|BNDPrefixOk, { Disp16|Disp32 }
-call, 0xe8, x64, Amd64|JumpDword|ImplicitStackOp|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk, { Disp16|Disp32 }
+call, 0xe8, No64, JumpDword|ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf|BNDPrefixOk|IntelSuffix, { Disp16|Disp32 }
+call, 0xe8, x64, Amd64|JumpDword|ImplicitStackOp|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk|IntelSuffix, { Disp16|Disp32 }
call, 0xe8, x64, Intel64|JumpDword|ImplicitStackOp|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk, { Disp32 }
call, 0xff/2, No64, Modrm|JumpAbsolute|ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg32|Unspecified|BaseIndex }
call, 0xff/2, x64, Amd64|Modrm|JumpAbsolute|ImplicitStackOp|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg64|Unspecified|BaseIndex }
call, 0xff/2, x64, Intel64|Modrm|JumpAbsolute|ImplicitStackOp|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg64|Unspecified|BaseIndex }
// Intel Syntax remaining call instances.
-call, 0x9a, No64, JumpInterSegment|ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Imm16, Imm16|Imm32 }
+call, 0x9a, No64, JumpInterSegment|ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf|IntelSuffix, { Imm16, Imm16|Imm32 }
call, 0xff/3, 0, Amd64|Modrm|JumpAbsolute|ImplicitStackOp|DefaultSize|NoSuf, { Dword|Fword|BaseIndex }
call, 0xff/3, x64, Intel64|Modrm|JumpAbsolute|ImplicitStackOp|NoSuf, { Dword|Fword|Tbyte|BaseIndex }
lcall, 0x9a, No64, JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Imm16, Imm16|Imm32 }
@@ -481,29 +481,29 @@ jmp, 0xff/4, No64, Modrm|JumpAbsolute|No_bSuf|No_sSuf|No_qSuf|BNDPrefixOk|NoTrac
jmp, 0xff/4, x64, Amd64|Modrm|JumpAbsolute|No_bSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg64|Unspecified|BaseIndex }
jmp, 0xff/4, x64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg64|Unspecified|BaseIndex }
// Intel Syntax remaining jmp instances.
-jmp, 0xea, No64, JumpInterSegment|No_bSuf|No_sSuf|No_qSuf, { Imm16, Imm16|Imm32 }
+jmp, 0xea, No64, JumpInterSegment|No_bSuf|No_sSuf|No_qSuf|IntelSuffix, { Imm16, Imm16|Imm32 }
jmp, 0xff/5, 0, Amd64|Modrm|JumpAbsolute|NoSuf, { Dword|Fword|BaseIndex }
jmp, 0xff/5, x64, Intel64|Modrm|JumpAbsolute|NoSuf, { Dword|Fword|Tbyte|BaseIndex }
ljmp, 0xea, No64, JumpInterSegment|No_bSuf|No_sSuf|No_qSuf, { Imm16, Imm16|Imm32 }
ljmp, 0xff/5, 0, Amd64|Modrm|JumpAbsolute|No_bSuf|No_sSuf|No_qSuf, { Unspecified|BaseIndex }
ljmp, 0xff/5, x64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_sSuf, { Unspecified|BaseIndex }
-ret, 0xc3, No64, ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf|RepPrefixOk|BNDPrefixOk, {}
-ret, 0xc2, No64, ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf|RepPrefixOk|BNDPrefixOk, { Imm16 }
-ret, 0xc3, x64, Amd64|ImplicitStackOp|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64|RepPrefixOk|BNDPrefixOk, {}
-ret, 0xc2, x64, Amd64|ImplicitStackOp|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64|RepPrefixOk|BNDPrefixOk, { Imm16 }
-ret, 0xc3, x64, Intel64|ImplicitStackOp|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|RepPrefixOk|BNDPrefixOk, {}
-ret, 0xc2, x64, Intel64|ImplicitStackOp|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|RepPrefixOk|BNDPrefixOk, { Imm16 }
+ret, 0xc3, No64, ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf|RepPrefixOk|BNDPrefixOk|IntelSuffix, {}
+ret, 0xc2, No64, ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf|RepPrefixOk|BNDPrefixOk|IntelSuffix, { Imm16 }
+ret, 0xc3, x64, Amd64|ImplicitStackOp|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64|RepPrefixOk|BNDPrefixOk|IntelSuffix, {}
+ret, 0xc2, x64, Amd64|ImplicitStackOp|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64|RepPrefixOk|BNDPrefixOk|IntelSuffix, { Imm16 }
+ret, 0xc3, x64, Intel64|ImplicitStackOp|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|RepPrefixOk|BNDPrefixOk|IntelSuffix, {}
+ret, 0xc2, x64, Intel64|ImplicitStackOp|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|RepPrefixOk|BNDPrefixOk|IntelSuffix, { Imm16 }
lret, 0xcb, 0, DefaultSize|No_bSuf|No_sSuf, {}
lret, 0xca, 0, DefaultSize|No_bSuf|No_sSuf, { Imm16 }
// Intel Syntax.
-retf, 0xcb, 0, DefaultSize|No_bSuf|No_sSuf, {}
-retf, 0xca, 0, DefaultSize|No_bSuf|No_sSuf, { Imm16 }
+retf, 0xcb, 0, DefaultSize|No_bSuf|No_sSuf|IntelSuffix, {}
+retf, 0xca, 0, DefaultSize|No_bSuf|No_sSuf|IntelSuffix, { Imm16 }
-enter, 0xc8, i186&No64, ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Imm16, Imm8 }
-enter, 0xc8, x64, ImplicitStackOp|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Imm16, Imm8 }
-leave, 0xc9, i186&No64, ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf, {}
-leave, 0xc9, x64, ImplicitStackOp|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, {}
+enter, 0xc8, i186&No64, ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf|IntelSuffix, { Imm16, Imm8 }
+enter, 0xc8, x64, ImplicitStackOp|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64|IntelSuffix, { Imm16, Imm8 }
+leave, 0xc9, i186&No64, ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|No_qSuf|IntelSuffix, {}
+leave, 0xc9, x64, ImplicitStackOp|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64|IntelSuffix, {}
<cc:opc, o:0, no:1, b:2, c:2, nae:2, nb:3, nc:3, ae:3, e:4, z:4, ne:5, nz:5, be:6, na:6, nbe:7, a:7, +
s:8, ns:9, p:a, pe:a, np:b, po:b, l:c, nge:c, nl:d, ge:d, le:e, ng:e, nle:f, g:f>
@@ -520,16 +520,16 @@ jrcxz, 0xe3, x64, JumpByte|Size64|NoSuf|NoRex64, { Disp8 }
// %cx rather than %ecx for the loop count, so the `w' form of these
// instructions emit an address size prefix rather than a data size
// prefix.
-loop, 0xe2, No64, JumpByte|No_bSuf|No_sSuf|No_qSuf, { Disp8 }
-loop, 0xe2, x64, JumpByte|No_bSuf|No_wSuf|No_sSuf|NoRex64, { Disp8 }
-loopz, 0xe1, No64, JumpByte|No_bSuf|No_sSuf|No_qSuf, { Disp8 }
-loopz, 0xe1, x64, JumpByte|No_bSuf|No_wSuf|No_sSuf|NoRex64, { Disp8 }
-loope, 0xe1, No64, JumpByte|No_bSuf|No_sSuf|No_qSuf, { Disp8 }
-loope, 0xe1, x64, JumpByte|No_bSuf|No_wSuf|No_sSuf|NoRex64, { Disp8 }
-loopnz, 0xe0, No64, JumpByte|No_bSuf|No_sSuf|No_qSuf, { Disp8 }
-loopnz, 0xe0, x64, JumpByte|No_bSuf|No_wSuf|No_sSuf|NoRex64, { Disp8 }
-loopne, 0xe0, No64, JumpByte|No_bSuf|No_sSuf|No_qSuf, { Disp8 }
-loopne, 0xe0, x64, JumpByte|No_bSuf|No_wSuf|No_sSuf|NoRex64, { Disp8 }
+loop, 0xe2, No64, JumpByte|No_bSuf|No_sSuf|No_qSuf|IntelSuffix, { Disp8 }
+loop, 0xe2, x64, JumpByte|No_bSuf|No_wSuf|No_sSuf|NoRex64|IntelSuffix, { Disp8 }
+loopz, 0xe1, No64, JumpByte|No_bSuf|No_sSuf|No_qSuf|IntelSuffix, { Disp8 }
+loopz, 0xe1, x64, JumpByte|No_bSuf|No_wSuf|No_sSuf|NoRex64|IntelSuffix, { Disp8 }
+loope, 0xe1, No64, JumpByte|No_bSuf|No_sSuf|No_qSuf|IntelSuffix, { Disp8 }
+loope, 0xe1, x64, JumpByte|No_bSuf|No_wSuf|No_sSuf|NoRex64|IntelSuffix, { Disp8 }
+loopnz, 0xe0, No64, JumpByte|No_bSuf|No_sSuf|No_qSuf|IntelSuffix, { Disp8 }
+loopnz, 0xe0, x64, JumpByte|No_bSuf|No_wSuf|No_sSuf|NoRex64|IntelSuffix, { Disp8 }
+loopne, 0xe0, No64, JumpByte|No_bSuf|No_sSuf|No_qSuf|IntelSuffix, { Disp8 }
+loopne, 0xe0, x64, JumpByte|No_bSuf|No_wSuf|No_sSuf|NoRex64|IntelSuffix, { Disp8 }
// Set byte on flag instructions.
set<cc>, 0xf9<cc:opc>/0, i386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { Reg8|Unspecified|BaseIndex }
@@ -537,38 +537,38 @@ set<cc>, 0xf24<cc:opc>/0, APX_F, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|VexWIG|EV
setzu<cc>, 0xf24<cc:opc>/0, APX_F, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|VexWIG|EVexMap4|ZU, { Reg8 }
// String manipulation.
-cmps, 0xa6, 0, W|No_sSuf|RepPrefixOk, {}
-cmps, 0xa6, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+cmps, 0xa6, 0, W|No_sSuf|RepPrefixOk|IntelSuffix, {}
+cmps, 0xa6, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk|IntelSuffix, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Byte|Word|Dword|Qword|Unspecified|BaseIndex }
scmp, 0xa6, 0, W|No_sSuf|RepPrefixOk, {}
scmp, 0xa6, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-ins, 0x6c, i186, W|No_sSuf|No_qSuf|RepPrefixOk, {}
-ins, 0x6c, i186, W|No_sSuf|No_qSuf|IsStringEsOp1|RepPrefixOk, { InOutPortReg, Byte|Word|Dword|Unspecified|BaseIndex }
-outs, 0x6e, i186, W|No_sSuf|No_qSuf|RepPrefixOk, {}
-outs, 0x6e, i186, W|No_sSuf|No_qSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Unspecified|BaseIndex, InOutPortReg }
-lods, 0xac, 0, W|No_sSuf|RepPrefixOk, {}
-lods, 0xac, 0, W|No_sSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-lods, 0xac, 0, W|No_sSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword }
+ins, 0x6c, i186, W|No_sSuf|No_qSuf|RepPrefixOk|IntelSuffix, {}
+ins, 0x6c, i186, W|No_sSuf|No_qSuf|IsStringEsOp1|RepPrefixOk|IntelSuffix, { InOutPortReg, Byte|Word|Dword|Unspecified|BaseIndex }
+outs, 0x6e, i186, W|No_sSuf|No_qSuf|RepPrefixOk|IntelSuffix, {}
+outs, 0x6e, i186, W|No_sSuf|No_qSuf|IsString|RepPrefixOk|IntelSuffix, { Byte|Word|Dword|Unspecified|BaseIndex, InOutPortReg }
+lods, 0xac, 0, W|No_sSuf|RepPrefixOk|IntelSuffix, {}
+lods, 0xac, 0, W|No_sSuf|IsString|RepPrefixOk|IntelSuffix, { Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+lods, 0xac, 0, W|No_sSuf|IsString|RepPrefixOk|IntelSuffix, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword }
slod, 0xac, 0, W|No_sSuf|RepPrefixOk, {}
slod, 0xac, 0, W|No_sSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex }
slod, 0xac, 0, W|No_sSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword }
-movs, 0xa4, 0, W|No_sSuf|RepPrefixOk, {}
-movs, 0xa4, 0, W|No_sSuf|IsStringEsOp1|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+movs, 0xa4, 0, W|No_sSuf|RepPrefixOk|IntelSuffix, {}
+movs, 0xa4, 0, W|No_sSuf|IsStringEsOp1|RepPrefixOk|IntelSuffix, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Byte|Word|Dword|Qword|Unspecified|BaseIndex }
smov, 0xa4, 0, W|No_sSuf|RepPrefixOk, {}
smov, 0xa4, 0, W|No_sSuf|IsStringEsOp1|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-scas, 0xae, 0, W|No_sSuf|RepPrefixOk, {}
-scas, 0xae, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-scas, 0xae, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword }
+scas, 0xae, 0, W|No_sSuf|RepPrefixOk|IntelSuffix, {}
+scas, 0xae, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk|IntelSuffix, { Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+scas, 0xae, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk|IntelSuffix, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword }
ssca, 0xae, 0, W|No_sSuf|RepPrefixOk, {}
ssca, 0xae, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex }
ssca, 0xae, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword }
-stos, 0xaa, 0, W|No_sSuf|RepPrefixOk, {}
-stos, 0xaa, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-stos, 0xaa, 0, W|No_sSuf|IsStringEsOp1|RepPrefixOk, { Acc|Byte|Word|Dword|Qword, Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+stos, 0xaa, 0, W|No_sSuf|RepPrefixOk|IntelSuffix, {}
+stos, 0xaa, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk|IntelSuffix, { Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+stos, 0xaa, 0, W|No_sSuf|IsStringEsOp1|RepPrefixOk|IntelSuffix, { Acc|Byte|Word|Dword|Qword, Byte|Word|Dword|Qword|Unspecified|BaseIndex }
ssto, 0xaa, 0, W|No_sSuf|RepPrefixOk, {}
ssto, 0xaa, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex }
ssto, 0xaa, 0, W|No_sSuf|IsStringEsOp1|RepPrefixOk, { Acc|Byte|Word|Dword|Qword, Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-xlat, 0xd7, 0, No_wSuf|No_lSuf|No_sSuf|No_qSuf, {}
-xlat, 0xd7, 0, No_wSuf|No_lSuf|No_sSuf|No_qSuf|IsString, { Byte|Unspecified|BaseIndex }
+xlat, 0xd7, 0, No_wSuf|No_lSuf|No_sSuf|No_qSuf|IntelSuffix, {}
+xlat, 0xd7, 0, No_wSuf|No_lSuf|No_sSuf|No_qSuf|IsString|IntelSuffix, { Byte|Unspecified|BaseIndex }
// Bit manipulation.
bsf, 0xfbc, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf|RepPrefixOk, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
@@ -589,7 +589,7 @@ int, 0xcd, 0, ImplicitStackOp|NoSuf, { Imm8 }
int1, 0xf1, 0, ImplicitStackOp|NoSuf, {}
int3, 0xcc, 0, ImplicitStackOp|NoSuf, {}
into, 0xce, No64, ImplicitStackOp|NoSuf, {}
-iret, 0xcf, 0, ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf, {}
+iret, 0xcf, 0, ImplicitStackOp|DefaultSize|No_bSuf|No_sSuf|IntelSuffix, {}
// i386sl, i486sl, later 486, and Pentium.
rsm, 0xfaa, i386, NoSuf, {}
@@ -608,9 +608,9 @@ arpl, 0x63, i286&No64, RegMem|CheckOperandSize|IgnoreSize|No_bSuf|No_sSuf|No_qSu
arpl, 0x63, i286&No64, Modrm|IgnoreSize|No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32, Word|Unspecified|BaseIndex }
lar, 0xf02, i286, Modrm|CheckOperandSize|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64 }
lar, 0xf02, i286, Modrm|No_bSuf|No_sSuf|NoRex64, { Reg16|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
-lgdt, 0xf01/2, i286&No64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex }
+lgdt, 0xf01/2, i286&No64, Modrm|No_bSuf|No_sSuf|No_qSuf|IntelSuffix, { Fword|Unspecified|BaseIndex }
lgdt, 0xf01/2, x64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Tbyte|Unspecified|BaseIndex }
-lidt, 0xf01/3, i286&No64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex }
+lidt, 0xf01/3, i286&No64, Modrm|No_bSuf|No_sSuf|No_qSuf|IntelSuffix, { Fword|Unspecified|BaseIndex }
lidt, 0xf01/3, x64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Tbyte|Unspecified|BaseIndex }
lldt, 0xf00/2, i286, Modrm|IgnoreSize|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64 }
lldt, 0xf00/2, i286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex }
@@ -620,9 +620,9 @@ lsl, 0xf03, i286, Modrm|No_bSuf|No_sSuf|NoRex64, { Reg16|Unspecified|BaseIndex,
ltr, 0xf00/3, i286, Modrm|IgnoreSize|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64 }
ltr, 0xf00/3, i286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex }
-sgdt, 0xf01/0, i286&No64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex }
+sgdt, 0xf01/0, i286&No64, Modrm|No_bSuf|No_sSuf|No_qSuf|IntelSuffix, { Fword|Unspecified|BaseIndex }
sgdt, 0xf01/0, x64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Tbyte|Unspecified|BaseIndex }
-sidt, 0xf01/1, i286&No64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex }
+sidt, 0xf01/1, i286&No64, Modrm|No_bSuf|No_sSuf|No_qSuf|IntelSuffix, { Fword|Unspecified|BaseIndex }
sidt, 0xf01/1, x64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Tbyte|Unspecified|BaseIndex }
sldt, 0xf00/0, i286, Modrm|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64 }
sldt, 0xf00/0, i286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex }
@@ -834,12 +834,12 @@ fstsw, 0xdfe0, i287|i387, NoSuf|FWait, {}
fnclex, 0xdbe2, FP, NoSuf, {}
fclex, 0xdbe2, FP, NoSuf|FWait, {}
// Short forms of fldenv, fstenv, fsave, and frstor use data size prefix.
-fnstenv, 0xd9/6, FP, Modrm|No_bSuf|No_wSuf|No_qSuf, { Unspecified|BaseIndex }
-fstenv, 0xd9/6, FP, Modrm|No_bSuf|No_wSuf|No_qSuf|FWait, { Unspecified|BaseIndex }
-fldenv, 0xd9/4, FP, Modrm|No_bSuf|No_wSuf|No_qSuf, { Unspecified|BaseIndex }
-fnsave, 0xdd/6, FP, Modrm|No_bSuf|No_wSuf|No_qSuf, { Unspecified|BaseIndex }
-fsave, 0xdd/6, FP, Modrm|No_bSuf|No_wSuf|No_qSuf|FWait, { Unspecified|BaseIndex }
-frstor, 0xdd/4, FP, Modrm|No_bSuf|No_wSuf|No_qSuf, { Unspecified|BaseIndex }
+fnstenv, 0xd9/6, FP, Modrm|No_bSuf|No_wSuf|No_qSuf|IntelSuffix, { Unspecified|BaseIndex }
+fstenv, 0xd9/6, FP, Modrm|No_bSuf|No_wSuf|No_qSuf|FWait|IntelSuffix, { Unspecified|BaseIndex }
+fldenv, 0xd9/4, FP, Modrm|No_bSuf|No_wSuf|No_qSuf|IntelSuffix, { Unspecified|BaseIndex }
+fnsave, 0xdd/6, FP, Modrm|No_bSuf|No_wSuf|No_qSuf|IntelSuffix, { Unspecified|BaseIndex }
+fsave, 0xdd/6, FP, Modrm|No_bSuf|No_wSuf|No_qSuf|FWait|IntelSuffix, { Unspecified|BaseIndex }
+frstor, 0xdd/4, FP, Modrm|No_bSuf|No_wSuf|No_qSuf|IntelSuffix, { Unspecified|BaseIndex }
// 8087 only
fneni, 0xdbe0, i8087, NoSuf, {}
feni, 0xdbe0, i8087, NoSuf|FWait, {}
@@ -943,11 +943,11 @@ cmpxchg8b, 0xfc7/1, i586, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|HLEPrefi
// Pentium II/Pentium Pro extensions.
sysenter, 0xf34, x64, Intel64Only|NoSuf, {}
sysenter, 0xf34, i686&No64, NoSuf, {}
-sysexit, 0xf35, x64, Intel64Only|No_bSuf|No_wSuf|No_sSuf, {}
+sysexit, 0xf35, x64, Intel64Only|No_bSuf|No_wSuf|No_sSuf|IntelSuffix, {}
sysexit, 0xf35, i686&No64, NoSuf, {}
-fxsave, 0xfae/0, FXSR, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Unspecified|BaseIndex }
+fxsave, 0xfae/0, FXSR, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|IntelSuffix, { Unspecified|BaseIndex }
fxsave64, 0xfae/0, FXSR&x64, Modrm|NoSuf|Size64, { Unspecified|BaseIndex }
-fxrstor, 0xfae/1, FXSR, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Unspecified|BaseIndex }
+fxrstor, 0xfae/1, FXSR, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|IntelSuffix, { Unspecified|BaseIndex }
fxrstor64, 0xfae/1, FXSR&x64, Modrm|NoSuf|Size64, { Unspecified|BaseIndex }
rdpmc, 0xf33, i686, NoSuf, {}
// official undefined instr.
@@ -1539,11 +1539,11 @@ roundss<SSE41D>, 0x660f3a0a, <SSE41D:cpu>, Modrm|<SSE41D:scal>|<SSE41D:vvvv>|NoS
pcmpgtq<sse42>, 0x660f3837, <sse42:cpu>, Modrm|<sse42:attr>|<sse42:vvvv>|NoSuf|Optimize, { RegXMM|Unspecified|BaseIndex, RegXMM }
pcmpestri<sse42>, 0x660f3a61, <sse42:cpu>&No64, Modrm|<sse42:attr>|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
-pcmpestri, 0x6661, AVX&x64, Modrm|Vex|Space0F3A|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|SSE2AVX, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
-pcmpestri, 0x660f3a61, SSE4_2&x64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
+pcmpestri, 0x6661, AVX&x64, Modrm|Vex|Space0F3A|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|SSE2AVX|IntelSuffix, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
+pcmpestri, 0x660f3a61, SSE4_2&x64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|IntelSuffix, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
pcmpestrm<sse42>, 0x660f3a60, <sse42:cpu>&No64, Modrm|<sse42:attr>|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
-pcmpestrm, 0x6660, AVX&x64, Modrm|Vex|Space0F3A|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|SSE2AVX, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
-pcmpestrm, 0x660f3a60, SSE4_2&x64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
+pcmpestrm, 0x6660, AVX&x64, Modrm|Vex|Space0F3A|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|SSE2AVX|IntelSuffix, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
+pcmpestrm, 0x660f3a60, SSE4_2&x64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|IntelSuffix, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
pcmpistri<sse42>, 0x660f3a63, <sse42:cpu>, Modrm|<sse42:attr>|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
pcmpistrm<sse42>, 0x660f3a62, <sse42:cpu>, Modrm|<sse42:attr>|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
crc32, 0xf20f38f0, SSE4_2, W|Modrm|No_sSuf|No_qSuf, { Reg8|Reg16|Reg32|Unspecified|BaseIndex, Reg32 }
@@ -1553,16 +1553,16 @@ crc32, 0xf0, APX_F, W|Modrm|No_wSuf|No_lSuf|No_sSuf|EVexMap4, { Reg8|Reg64|Unspe
// xsave/xrstor New Instructions.
-xsave, 0xfae/4, Xsave, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoEgpr, { Unspecified|BaseIndex }
+xsave, 0xfae/4, Xsave, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|IntelSuffix|NoEgpr, { Unspecified|BaseIndex }
xsave64, 0xfae/4, Xsave&x64, Modrm|NoSuf|Size64|NoEgpr, { Unspecified|BaseIndex }
-xrstor, 0xfae/5, Xsave, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoEgpr, { Unspecified|BaseIndex }
+xrstor, 0xfae/5, Xsave, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|IntelSuffix|NoEgpr, { Unspecified|BaseIndex }
xrstor64, 0xfae/5, Xsave&x64, Modrm|NoSuf|Size64|NoEgpr, { Unspecified|BaseIndex }
xgetbv, 0xf01d0, Xsave, NoSuf, {}
xsetbv, 0xf01d1, Xsave, NoSuf, {}
// xsaveopt
-xsaveopt, 0xfae/6, Xsaveopt, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoEgpr, { Unspecified|BaseIndex }
+xsaveopt, 0xfae/6, Xsaveopt, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|IntelSuffix|NoEgpr, { Unspecified|BaseIndex }
xsaveopt64, 0xfae/6, Xsaveopt&x64, Modrm|NoSuf|Size64|NoEgpr, { Unspecified|BaseIndex }
// AES instructions.
@@ -1738,9 +1738,9 @@ vpcmpeq<bw>, 0x6674 | <bw:opc>, AVX|AVX2, Modrm|C|Vex|Space0F|Src1VVVV|VexWIG|Ch
vpcmpeqd, 0x6676, AVX|AVX2, Modrm|C|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vpcmpeqq, 0x6629, AVX|AVX2, Modrm|Vex|Space0F38|Src1VVVV|VexWIG|CheckOperandSize|NoSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vpcmpestri, 0x6661, AVX&No64, Modrm|Vex|Space0F3A|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM }
-vpcmpestri, 0x6661, AVX&x64, Modrm|Vex|Space0F3A|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM }
+vpcmpestri, 0x6661, AVX&x64, Modrm|Vex|Space0F3A|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|IntelSuffix, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM }
vpcmpestrm, 0x6660, AVX&No64, Modrm|Vex|Space0F3A|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM }
-vpcmpestrm, 0x6660, AVX&x64, Modrm|Vex|Space0F3A|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM }
+vpcmpestrm, 0x6660, AVX&x64, Modrm|Vex|Space0F3A|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|IntelSuffix, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM }
vpcmpgt<bw>, 0x6664 | <bw:opc>, AVX|AVX2, Modrm|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vpcmpgtd, 0x6666, AVX|AVX2, Modrm|Vex|Space0F|Src1VVVV|VexWIG|CheckOperandSize|NoSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vpcmpgtq, 0x6637, AVX|AVX2, Modrm|Vex|Space0F38|Src1VVVV|VexWIG|CheckOperandSize|NoSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
@@ -2117,7 +2117,7 @@ pswapd, 0xf0f/0xbb, 3dnowA, Modrm|NoSuf|ImmExt, { Qword|Unspecified|BaseIndex|Re
// AMD extensions.
syscall, 0xf05, SYSCALL, NoSuf, {}
-sysret, 0xf07, SYSCALL, No_bSuf|No_wSuf|No_sSuf, {}
+sysret, 0xf07, SYSCALL, No_bSuf|No_wSuf|No_sSuf|IntelSuffix, {}
swapgs, 0xf01f8, x64, NoSuf, {}
rdtscp, 0xf01f9, Rdtscp, NoSuf, {}
diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index e9a5d69a18f..6df7a712cc5 100644
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -26,8 +26,8 @@ static const insn_template i386_optab[] =
{
{ MN_mov, 0xa0, 2, SPACE_BASE, None,
{ 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
- 0, 0 },
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
+ 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 1, 1, 0, 0, 0,
@@ -36,8 +36,8 @@ static const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0 } } } },
{ MN_mov, 0xa0, 2, SPACE_BASE, None,
{ 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
- 0, 0 },
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
+ 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 0,
@@ -47,7 +47,7 @@ static const insn_template i386_optab[] =
{ MN_mov, 0x88, 2, SPACE_BASE, None,
{ 1, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 2,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0 },
+ 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0,
@@ -57,7 +57,7 @@ static const insn_template i386_optab[] =
{ MN_mov, 0xb0, 2, SPACE_BASE, None,
{ 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0 },
+ 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 0, 0, 0, 1, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -67,7 +67,7 @@ static const insn_template i386_optab[] =
{ MN_mov, 0xc6, 2, SPACE_BASE, 0,
{ 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 2,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,
- 0, 0 },
+ 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 0, 0, 0, 1, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -77,7 +77,7 @@ static const insn_template i386_optab[] =
{ MN_mov, 0xb8, 2, SPACE_BASE, None,
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,
- 0, 0 },
+ 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -87,7 +87,7 @@ static const insn_template i386_optab[] =
{ MN_mov, 0x8c, 2, SPACE_BASE, None,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 1, 0, 0,
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0 },
+ 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -97,7 +97,7 @@ static const insn_template i386_optab[] =
{ MN_mov, 0x8c, 2, SPACE_BASE, None,
{ 1, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0 },
+ 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -107,7 +107,7 @@ static const insn_template i386_optab[] =
{ MN_mov, 0x8e, 2, SPACE_BASE, None,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0,
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0 },
+ 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0,
@@ -117,7 +117,7 @@ static const insn_template i386_optab[] =
{ MN_mov, 0x20, 2, SPACE_0F, None,
{ 1, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 1, 0, 0, 1, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0 },
+ 0, 0, 0 },
{ { 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -127,7 +127,7 @@ static const insn_template i386_optab[] =
{ MN_mov, 0x20, 2, SPACE_0F, None,
{ 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0,
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0 },
+ 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -137,7 +137,7 @@ static const insn_template i386_optab[] =
{ MN_mov, 0x21, 2, SPACE_0F, None,
{ 1, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 1, 0, 0, 1, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0 },
+ 0, 0, 0 },
{ { 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -147,7 +147,7 @@ static const insn_template i386_optab[] =
{ MN_mov, 0x21, 2, SPACE_0F, None,
{ 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0,
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0 },
+ 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -157,7 +157,7 @@ static const insn_template i386_optab[] =
{ MN_mov, 0x24, 2, SPACE_0F, None,
{ 1, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 1, 0, 0, 1, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0 },
+ 0, 0, 0 },
{ { 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -166,8 +166,8 @@ static const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0 } } } },
{ MN_movabs, 0xa0, 2, SPACE_BASE, None,
{ 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
- 0, 0 },
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
+ 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 0,
@@ -177,7 +177,7 @@ static const insn_template i386_optab[] =
{ MN_movabs, 0xb8, 2, SPACE_BASE, None,
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0 },
+ 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -186,8 +186,8 @@ static const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0 } } } },
{ MN_movbe, 0xf0, 2, SPACE_0F38, None,
{ 1, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
- 0, 0 },
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
+ 0, 0, 0 },
{ { 47, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 1, 1, 0, 1, 0,
@@ -197,7 +197,7 @@ static const insn_template i386_optab[] =
{ MN_movbe, 0x60, 2, SPACE_EVEXMAP4, None,
{ 1, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0 },
+ 0, 0, 0 },
{ { 47, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 1, 1, 0, 1, 0,
@@ -207,7 +207,7 @@ static const insn_template i386_optab[] =
{ MN_bswap, 0xc8, 1, SPACE_0F, None,
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0 },
+ 0, 0, 0 },
{ { 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0,
@@ -215,7 +215,7 @@ static const insn_template i386_optab[] =
{ MN_movsb, 0xbe, 2, SPACE_0F, None,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0 },
+ 0, 0, 0 },
{ { 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 1, 0, 0, 0, 0, 0,
@@ -225,7 +225,7 @@ static const insn_template i386_optab[] =
{ MN_movsw, 0xbf, 2, SPACE_0F, None,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0 },
+ 0, 0, 0 },
{ { 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 1, 0, 0, 0, 0,
@@ -235,7 +235,7 @@ static const insn_template i386_optab[] =
{ MN_movsl, 0x63, 2, SPACE_BASE, None,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0 },
+ 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 0, 0,
@@ -245,7 +245,7 @@ static const insn_template i386_optab[] =
{ MN_movsx, 0xbe, 2, SPACE_0F, None,
{ 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0 },
+ 0, 0, 0 },
{ { 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 1, 1, 0, 0, 0, 0,
@@ -255,7 +255,7 @@ static const insn_template i386_optab[] =
{ MN_movsx, 0x63, 2, SPACE_BASE, None,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0 },
+ 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 0, 0,
@@ -265,7 +265,7 @@ static const insn_template i386_optab[] =
{ MN_movsxd, 0x63, 2, SPACE_BASE, None,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0 },
+ 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 0, 0,
@@ -274,8 +274,8 @@ static const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0 } } } },
{ MN_movsxd, 0x63, 2, SPACE_BASE, None,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
- 0, 0 },
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
+ 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, 0, 0,
@@ -284,8 +284,8 @@ static const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0 } } } },
{ MN_movsxd, 0x63, 2, SPACE_BASE, None,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0,
- 0, 0 },
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0,
+ 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0,
@@ -295,7 +295,7 @@ static const insn_template i386_optab[] =
{ MN_movzb, 0xb6, 2, SPACE_0F, None,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0 },
+ 0, 0, 0 },
{ { 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 1, 0, 0, 0, 0, 0,
@@ -305,7 +305,7 @@ static const insn_template i386_optab[] =
{ MN_movzw, 0xb7, 2, SPACE_0F, None,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0 },
+ 0, 0, 0 },
{ { 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 1, 0, 0, 0, 0,
@@ -315,7 +315,7 @@ static const insn_template i386_optab[] =
{ MN_movzx, 0xb6, 2, SPACE_0F, None,
{ 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0 },
+ 0, 0, 0 },
{ { 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 1, 1, 0, 0, 0, 0,
@@ -325,7 +325,7 @@ static const insn_template i386_optab[] =
{ MN_push, 0x50, 1, SPACE_BASE, None,
{ 0, 0, 0, 0, 0, 0, 0, 0, 9, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0 },
+ 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0,
@@ -333,31 +333,31 @@ static const insn_template i386_optab[] =
{ MN_push, 0xff, 1, SPACE_BASE, 6,
{ 0, 0, 0, 1, 0, 0, 0, 0, 9, 2, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0 },
+ 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 1, 1, 0, 0, 0,
0, 0, 0, 0, 1, 0 } } } },
{ MN_push, 0x6a, 1, SPACE_BASE, None,
{ 0, 0, 0, 0, 0, 0, 0, 0, 9, 2, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0 },
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
+ 0, 0, 0 },
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } } } },
{ MN_push, 0x68, 1, SPACE_BASE, None,
{ 0, 0, 0, 0, 0, 0, 0, 0, 9, 2, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0 },
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
+ 0, 0, 0 },
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } } } },
{ MN_push, 0x06, 1, SPACE_BASE, None,
{ 0, 0, 0, 0, 0, 0, 0, 0, 9, 2, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0 },
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
+ 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -365,7 +365,7 @@ static const insn_template i386_optab[] =
{ MN_push, 0x50, 1, SPACE_BASE, None,
{ 0, 0, 0, 0, 0, 0, 0, 0, 9, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0,
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0 },
+ 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0,
@@ -373,31 +373,31 @@ static const insn_template i386_optab[] =
{ MN_push, 0xff, 1, SPACE_BASE, 6,
{ 0, 0, 0, 1, 0, 0, 0, 0, 9, 2, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0,
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0 },
+ 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0,
0, 0, 0, 0, 1, 0 } } } },
{ MN_push, 0x6a, 1, SPACE_BASE, None,
{ 0, 0, 0, 0, 0, 0, 0, 0, 9, 2, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0,
- 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0 },
+ 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
+ 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } } } },
{ MN_push, 0x68, 1, SPACE_BASE, None,
{ 0, 0, 0, 0, 0, 0, 0, 0, 9, 2, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0,
- 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0 },
+ 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
+ 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } } } },
{ MN_push, 0xa0, 1, SPACE_0F, None,
{ 0, 0, 0, 0, 0, 0, 0, 0, 9, 2, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0,
- 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0 },
+ 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
+ 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -405,15 +405,15 @@ static const insn_template i386_optab[] =
{ MN_pushp, 0x50, 1, SPACE_BASE, None,
{ 0, 0, 0, 0, 0, 0, 0, 0, 9, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 1, 0 },
+ 0, 1, 0 },
{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
0, 0, 0, 0, 0, 0 } } } },
{ MN_pusha, 0x60, 0, SPACE_BASE, None,
{ 0, 0, 0, 0, 0, 0, 0, 0, 9, 2, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0 },
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
+ 0, 0, 0 },
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -421,7 +421,7 @@ static const insn_template i386_optab[] =
{ MN_pop, 0x58, 1, SPACE_BASE, None,
{ 0, 0, 0, 0, 0, 0, 0, 0, 9, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0 },
+ 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0,
@@ -429,15 +429,15 @@ static const insn_template i386_optab[] =
{ MN_pop, 0x8f, 1, SPACE_BASE, 0,
{ 0, 0, 0, 1, 0, 0, 0, 0, 9, 2, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0 },
+ 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 1, 1, 0, 0, 0,
0, 0, 0, 0, 1, 0 } } } },
{ MN_pop, 0x07, 1, SPACE_BASE, None,
{ 0, 0, 0, 0, 0, 0, 0, 0, 9, 2, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0 },
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
+ 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -445,7 +445,7 @@ static const insn_template i386_optab[] =
{ MN_pop, 0x58, 1, SPACE_BASE, None,
{ 0, 0, 0, 0, 0, 0, 0, 0, 9, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0,
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0 },
+ 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0,
@@ -453,15 +453,15 @@ static const insn_template i386_optab[] =
{ MN_pop, 0x8f, 1, SPACE_BASE, 0,
{ 0, 0, 0, 1, 0, 0, 0, 0, 9, 2, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0,
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0 },
+ 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0,
0, 0, 0, 0, 1, 0 } } } },
{ MN_pop, 0xa1, 1, SPACE_0F, None,
{ 0, 0, 0, 0, 0, 0, 0, 0, 9, 2, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0,
- 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0 },
+ 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
+ 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -469,15 +469,15 @@ static const insn_template i386_optab[] =
{ MN_popp, 0x58, 1, SPACE_BASE, None,
{ 0, 0, 0, 0, 0, 0, 0, 0, 9, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 1, 0 },
+ 0, 1, 0 },
{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
0, 0, 0, 0, 0, 0 } } } },
{ MN_popa, 0x61, 0, SPACE_BASE, None,
{ 0, 0, 0, 0, 0, 0, 0, 0, 9, 2, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0 },
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
+ 0, 0, 0 },
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -485,7 +485,7 @@ static const insn_template i386_optab[] =
{ MN_xchg, 0x90, 2, SPACE_BASE, None,
{ 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0,
- 0, 0 },
+ 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0,
@@ -495,7 +495,7 @@ static const insn_template i386_optab[] =
{ MN_xchg, 0x86, 2, SPACE_BASE, None,
{ 1, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 6,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0,
- 0, 0 },
+ 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0,
@@ -504,8 +504,8 @@ static const insn_template i386_optab[] =
0, 0, 0, 0, 1, 0 } } } },
{ MN_in, 0xe4, 2, SPACE_BASE, None,
{ 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
- 0, 0 },
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
+ 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -514,8 +514,8 @@ static const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0 } } } },
{ MN_in, 0xec, 2, SPACE_BASE, None,
{ 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
- 0, 0 },
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
+ 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,
@@ -524,24 +524,24 @@ static const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0 } } } },
{ MN_in, 0xe4, 1, SPACE_BASE, None,
{ 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
- 0, 0 },
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1,
+ 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } } } },
{ MN_in, 0xec, 1, SPACE_BASE, None,
{ 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
- 0, 0 },
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1,
+ 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } } } },
{ MN_out, 0xe6, 2, SPACE_BASE, None,
{ 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
- 0, 0 },
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
+ 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
@@ -550,8 +550,8 @@ static const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0 } } } },
{ MN_out, 0xee, 2, SPACE_BASE, None,
{ 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
- 0, 0 },
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1,
+ 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0,
@@ -560,16 +560,16 @@ static const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0 } } } },
{ MN_out, 0xe6, 1, SPACE_BASE, None,
{ 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
- 0, 0 },
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1,
+ 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } } } },
{ MN_out, 0xee, 1, SPACE_BASE, None,
{ 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
- 0, 0 },
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1,
+ 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,
@@ -577,7 +577,7 @@ static const insn_template i386_optab[] =
{ MN_lea, 0x8d, 2, SPACE_BASE, None,
{ 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,
- 0, 0 },
+ 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0,
@@ -587,7 +587,7 @@ static const insn_template i386_optab[] =
{ MN_lds, 0xc5, 2, SPACE_BASE, None,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0 },
+ 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0,
@@ -597,7 +597,7 @@ static const insn_template i386_optab[] =
{ MN_les, 0xc4, 2, SPACE_BASE, None,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0 },
+ 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0,
@@ -606,8 +606,8 @@ static const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0 } } } },
{ MN_lfs, 0xb4, 2, SPACE_0F, None,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
- 0, 0 },
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
+ 0, 0, 0 },
{ { 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0,
@@ -616,8 +616,8 @@ static const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0 } } } },
{ MN_lfs, 0xb4, 2, SPACE_0F, None,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0,
- 0, 0 },
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0,
+ 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 1, 0, 1,
@@ -626,8 +626,8 @@ static const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0 } } } },
{ MN_lgs, 0xb5, 2, SPACE_0F, None,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
- 0, 0 },
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
+ 0, 0, 0 },
{ { 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0,
@@ -636,8 +636,8 @@ static const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0 } } } },
{ MN_lgs, 0xb5, 2, SPACE_0F, None,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0,
- 0, 0 },
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0,
+ 0, 0, 0 },
{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 1, 0, 1,
@@ -646,8 +646,8 @@ static const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0 } } } },
{ MN_lss, 0xb2, 2, SPACE_0F, None,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0[...]
[diff truncated at 100000 bytes]
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