[binutils-gdb] Add check for 8-bit old registers in EVEX format

Lili Cui cuilili@sourceware.org
Wed May 22 02:17:52 GMT 2024


https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=9f8b42c871ac1b75a4270378e33fd1b1fba95f84

commit 9f8b42c871ac1b75a4270378e33fd1b1fba95f84
Author: Cui, Lili <lili.cui@intel.com>
Date:   Wed May 22 09:33:10 2024 +0800

    Add check for 8-bit old registers in EVEX format
    
    Since APX supports EVEX from legacy instructions, we need to check
    the 8-bit old registers in EVEX format. And add test cases for it.
    
    gas/ChangeLog:
    
            * config/tc-i386.c (md_assemble): Add invalid check for old byte
            registers in EVEX format.
            * testsuite/gas/i386/x86-64-apx-inval.l: Add new test.
            * testsuite/gas/i386/x86-64-apx-inval.s: Ditto.

Diff:
---
 gas/config/tc-i386.c                      | 7 ++++---
 gas/testsuite/gas/i386/x86-64-apx-inval.l | 3 +++
 gas/testsuite/gas/i386/x86-64-apx-inval.s | 2 ++
 3 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 12af7ceec08..dc6d8bb9398 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -4314,7 +4314,7 @@ static void establish_rex (void)
   /* For REX/REX2/EVEX prefix instructions, we need to convert old registers
      (AL, CL, DL and BL) to new ones (AXL, CXL, DXL and BXL) and reject AH,
      CH, DH and BH.  */
-  if (i.rex || i.rex2)
+  if (i.rex || i.rex2 || i.tm.opcode_modifier.evex)
     {
       for (unsigned int x = first; x <= last; x++)
 	{
@@ -4326,8 +4326,9 @@ static void establish_rex (void)
 	      /* In case it is "hi" register, give up.  */
 	      if (i.op[x].regs->reg_num > 3)
 		as_bad (_("can't encode register '%s%s' in an "
-			  "instruction requiring REX/REX2 prefix"),
-			register_prefix, i.op[x].regs->reg_name);
+			  "instruction requiring %s prefix"),
+			register_prefix, i.op[x].regs->reg_name,
+			i.tm.opcode_modifier.evex ? "EVEX" : "REX/REX2");
 
 	      /* Otherwise it is equivalent to the extended register.
 		 Since the encoding doesn't change this is merely
diff --git a/gas/testsuite/gas/i386/x86-64-apx-inval.l b/gas/testsuite/gas/i386/x86-64-apx-inval.l
index 7a870b27b72..a15f6b87cac 100644
--- a/gas/testsuite/gas/i386/x86-64-apx-inval.l
+++ b/gas/testsuite/gas/i386/x86-64-apx-inval.l
@@ -12,3 +12,6 @@
 .*:13: Error: \{nf\} unsupported for `mulx'
 .*:14: Error: \{nf\} cannot be combined with \{vex\}/\{vex3\}
 .*:15: Error: \{nf\} cannot be combined with \{vex\}/\{vex3\}
+.*:16: Error: can't encode register '%ah' in an instruction requiring EVEX prefix
+.*:17: Error: can't encode register '%ah' in an instruction requiring EVEX prefix
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-apx-inval.s b/gas/testsuite/gas/i386/x86-64-apx-inval.s
index 0487b885ec8..3d69deabe4d 100644
--- a/gas/testsuite/gas/i386/x86-64-apx-inval.s
+++ b/gas/testsuite/gas/i386/x86-64-apx-inval.s
@@ -13,3 +13,5 @@
 	{nf} mulx %r15,%r15,%r11
 	{nf} {vex} bextr %ecx, %edx, %r10d
 	{vex} {nf} bextr %ecx, %edx, %r10d
+	{nf} add %dl,%ah
+	{evex} adc %dl,%ah


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