[binutils-gdb] RISC-V: Add Zabha extension CAS instructions.
Nelson Chu
nelsonc1225@sourceware.org
Fri Jun 28 02:09:42 GMT 2024
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=805df5e4a8de619aec6d6a808158c302307478e7
commit 805df5e4a8de619aec6d6a808158c302307478e7
Author: Jiawei <jiawei@iscas.ac.cn>
Date: Fri Jun 28 00:13:54 2024 +0800
RISC-V: Add Zabha extension CAS instructions.
This patch update the cas instruction in Zabha extension [1],
when both Zabha and Zacas extension enabled.
[1] https://github.com/riscv/riscv-zabha/tags
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): New extension case.
gas/ChangeLog:
* testsuite/gas/riscv/zabha-32.d: New instructions.
* testsuite/gas/riscv/zabha.d: Ditto.
* testsuite/gas/riscv/zabha.s: Ditto.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_AMOCAS_B): New opcodes.
(MASK_AMOCAS_B): Ditto.
(MATCH_AMOCAS_H): Ditto.
(MASK_AMOCAS_H): Ditto.
(DECLARE_INSN): New instructions.
* opcode/riscv.h (enum riscv_insn_class): New class case.
opcodes/ChangeLog:
* riscv-opc.c: New instructions.
Diff:
---
bfd/elfxx-riscv.c | 3 +++
gas/testsuite/gas/riscv/zabha-32.d | 10 +++++++++-
gas/testsuite/gas/riscv/zabha.d | 10 +++++++++-
gas/testsuite/gas/riscv/zabha.s | 8 ++++++++
include/opcode/riscv-opc.h | 6 ++++++
include/opcode/riscv.h | 1 +
opcodes/riscv-opc.c | 8 ++++++++
7 files changed, 44 insertions(+), 2 deletions(-)
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 49c644bafd1..4066ac3198f 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -2549,6 +2549,9 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
return riscv_subset_supports (rps, "zabha");
case INSN_CLASS_ZACAS:
return riscv_subset_supports (rps, "zacas");
+ case INSN_CLASS_ZABHA_AND_ZACAS:
+ return (riscv_subset_supports (rps, "zabha")
+ && riscv_subset_supports (rps, "zacas"));
case INSN_CLASS_ZALRSC:
return riscv_subset_supports (rps, "zalrsc");
case INSN_CLASS_ZAWRS:
diff --git a/gas/testsuite/gas/riscv/zabha-32.d b/gas/testsuite/gas/riscv/zabha-32.d
index 1e6427ea752..7836ae9acc6 100644
--- a/gas/testsuite/gas/riscv/zabha-32.d
+++ b/gas/testsuite/gas/riscv/zabha-32.d
@@ -1,4 +1,4 @@
-#as: -march=rv32i_zabha
+#as: -march=rv32i_zabha_zacas
#source: zabha.s
#objdump: -d -Mno-aliases
@@ -16,6 +16,7 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+e0a5052f[ ]+amomaxu.b[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+80a5052f[ ]+amomin.b[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+c0a5052f[ ]+amominu.b[ ]+a0,a0,\(a0\)
+[ ]+[0-9a-f]+:[ ]+28a5052f[ ]+amocas.b[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+04a5052f[ ]+amoadd.b.aq[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+0ca5052f[ ]+amoswap.b.aq[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+64a5052f[ ]+amoand.b.aq[ ]+a0,a0,\(a0\)
@@ -25,6 +26,7 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+e4a5052f[ ]+amomaxu.b.aq[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+84a5052f[ ]+amomin.b.aq[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+c4a5052f[ ]+amominu.b.aq[ ]+a0,a0,\(a0\)
+[ ]+[0-9a-f]+:[ ]+2ca5052f[ ]+amocas.b.aq[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+02a5052f[ ]+amoadd.b.rl[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+0aa5052f[ ]+amoswap.b.rl[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+62a5052f[ ]+amoand.b.rl[ ]+a0,a0,\(a0\)
@@ -34,6 +36,7 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+e2a5052f[ ]+amomaxu.b.rl[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+82a5052f[ ]+amomin.b.rl[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+c2a5052f[ ]+amominu.b.rl[ ]+a0,a0,\(a0\)
+[ ]+[0-9a-f]+:[ ]+2aa5052f[ ]+amocas.b.rl[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+06a5052f[ ]+amoadd.b.aqrl[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+0ea5052f[ ]+amoswap.b.aqrl[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+66a5052f[ ]+amoand.b.aqrl[ ]+a0,a0,\(a0\)
@@ -43,6 +46,7 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+e6a5052f[ ]+amomaxu.b.aqrl[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+86a5052f[ ]+amomin.b.aqrl[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+c6a5052f[ ]+amominu.b.aqrl[ ]+a0,a0,\(a0\)
+[ ]+[0-9a-f]+:[ ]+2ea5052f[ ]+amocas.b.aqrl[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+00a5152f[ ]+amoadd.h[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+08a5152f[ ]+amoswap.h[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+60a5152f[ ]+amoand.h[ ]+a0,a0,\(a0\)
@@ -52,6 +56,7 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+e0a5152f[ ]+amomaxu.h[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+80a5152f[ ]+amomin.h[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+c0a5152f[ ]+amominu.h[ ]+a0,a0,\(a0\)
+[ ]+[0-9a-f]+:[ ]+28a5152f[ ]+amocas.h[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+04a5152f[ ]+amoadd.h.aq[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+0ca5152f[ ]+amoswap.h.aq[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+64a5152f[ ]+amoand.h.aq[ ]+a0,a0,\(a0\)
@@ -61,6 +66,7 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+e4a5152f[ ]+amomaxu.h.aq[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+84a5152f[ ]+amomin.h.aq[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+c4a5152f[ ]+amominu.h.aq[ ]+a0,a0,\(a0\)
+[ ]+[0-9a-f]+:[ ]+2ca5152f[ ]+amocas.h.aq[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+02a5152f[ ]+amoadd.h.rl[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+0aa5152f[ ]+amoswap.h.rl[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+62a5152f[ ]+amoand.h.rl[ ]+a0,a0,\(a0\)
@@ -70,6 +76,7 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+e2a5152f[ ]+amomaxu.h.rl[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+82a5152f[ ]+amomin.h.rl[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+c2a5152f[ ]+amominu.h.rl[ ]+a0,a0,\(a0\)
+[ ]+[0-9a-f]+:[ ]+2aa5152f[ ]+amocas.h.rl[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+06a5152f[ ]+amoadd.h.aqrl[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+0ea5152f[ ]+amoswap.h.aqrl[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+66a5152f[ ]+amoand.h.aqrl[ ]+a0,a0,\(a0\)
@@ -79,3 +86,4 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+e6a5152f[ ]+amomaxu.h.aqrl[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+86a5152f[ ]+amomin.h.aqrl[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+c6a5152f[ ]+amominu.h.aqrl[ ]+a0,a0,\(a0\)
+[ ]+[0-9a-f]+:[ ]+2ea5152f[ ]+amocas.h.aqrl[ ]+a0,a0,\(a0\)
diff --git a/gas/testsuite/gas/riscv/zabha.d b/gas/testsuite/gas/riscv/zabha.d
index 7000452b6d1..86e2eb29f34 100644
--- a/gas/testsuite/gas/riscv/zabha.d
+++ b/gas/testsuite/gas/riscv/zabha.d
@@ -1,4 +1,4 @@
-#as: -march=rv64i_zabha
+#as: -march=rv64i_zabha_zacas
#source: zabha.s
#objdump: -d -Mno-aliases
@@ -16,6 +16,7 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+e0a5052f[ ]+amomaxu.b[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+80a5052f[ ]+amomin.b[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+c0a5052f[ ]+amominu.b[ ]+a0,a0,\(a0\)
+[ ]+[0-9a-f]+:[ ]+28a5052f[ ]+amocas.b[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+04a5052f[ ]+amoadd.b.aq[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+0ca5052f[ ]+amoswap.b.aq[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+64a5052f[ ]+amoand.b.aq[ ]+a0,a0,\(a0\)
@@ -25,6 +26,7 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+e4a5052f[ ]+amomaxu.b.aq[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+84a5052f[ ]+amomin.b.aq[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+c4a5052f[ ]+amominu.b.aq[ ]+a0,a0,\(a0\)
+[ ]+[0-9a-f]+:[ ]+2ca5052f[ ]+amocas.b.aq[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+02a5052f[ ]+amoadd.b.rl[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+0aa5052f[ ]+amoswap.b.rl[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+62a5052f[ ]+amoand.b.rl[ ]+a0,a0,\(a0\)
@@ -34,6 +36,7 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+e2a5052f[ ]+amomaxu.b.rl[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+82a5052f[ ]+amomin.b.rl[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+c2a5052f[ ]+amominu.b.rl[ ]+a0,a0,\(a0\)
+[ ]+[0-9a-f]+:[ ]+2aa5052f[ ]+amocas.b.rl[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+06a5052f[ ]+amoadd.b.aqrl[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+0ea5052f[ ]+amoswap.b.aqrl[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+66a5052f[ ]+amoand.b.aqrl[ ]+a0,a0,\(a0\)
@@ -43,6 +46,7 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+e6a5052f[ ]+amomaxu.b.aqrl[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+86a5052f[ ]+amomin.b.aqrl[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+c6a5052f[ ]+amominu.b.aqrl[ ]+a0,a0,\(a0\)
+[ ]+[0-9a-f]+:[ ]+2ea5052f[ ]+amocas.b.aqrl[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+00a5152f[ ]+amoadd.h[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+08a5152f[ ]+amoswap.h[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+60a5152f[ ]+amoand.h[ ]+a0,a0,\(a0\)
@@ -52,6 +56,7 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+e0a5152f[ ]+amomaxu.h[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+80a5152f[ ]+amomin.h[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+c0a5152f[ ]+amominu.h[ ]+a0,a0,\(a0\)
+[ ]+[0-9a-f]+:[ ]+28a5152f[ ]+amocas.h[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+04a5152f[ ]+amoadd.h.aq[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+0ca5152f[ ]+amoswap.h.aq[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+64a5152f[ ]+amoand.h.aq[ ]+a0,a0,\(a0\)
@@ -61,6 +66,7 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+e4a5152f[ ]+amomaxu.h.aq[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+84a5152f[ ]+amomin.h.aq[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+c4a5152f[ ]+amominu.h.aq[ ]+a0,a0,\(a0\)
+[ ]+[0-9a-f]+:[ ]+2ca5152f[ ]+amocas.h.aq[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+02a5152f[ ]+amoadd.h.rl[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+0aa5152f[ ]+amoswap.h.rl[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+62a5152f[ ]+amoand.h.rl[ ]+a0,a0,\(a0\)
@@ -70,6 +76,7 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+e2a5152f[ ]+amomaxu.h.rl[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+82a5152f[ ]+amomin.h.rl[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+c2a5152f[ ]+amominu.h.rl[ ]+a0,a0,\(a0\)
+[ ]+[0-9a-f]+:[ ]+2aa5152f[ ]+amocas.h.rl[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+06a5152f[ ]+amoadd.h.aqrl[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+0ea5152f[ ]+amoswap.h.aqrl[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+66a5152f[ ]+amoand.h.aqrl[ ]+a0,a0,\(a0\)
@@ -79,3 +86,4 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+e6a5152f[ ]+amomaxu.h.aqrl[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+86a5152f[ ]+amomin.h.aqrl[ ]+a0,a0,\(a0\)
[ ]+[0-9a-f]+:[ ]+c6a5152f[ ]+amominu.h.aqrl[ ]+a0,a0,\(a0\)
+[ ]+[0-9a-f]+:[ ]+2ea5152f[ ]+amocas.h.aqrl[ ]+a0,a0,\(a0\)
diff --git a/gas/testsuite/gas/riscv/zabha.s b/gas/testsuite/gas/riscv/zabha.s
index 82b811a44e7..4c4fd17cf5d 100644
--- a/gas/testsuite/gas/riscv/zabha.s
+++ b/gas/testsuite/gas/riscv/zabha.s
@@ -8,6 +8,7 @@ target:
amomaxu.b a0, a0, 0(a0)
amomin.b a0, a0, 0(a0)
amominu.b a0, a0, 0(a0)
+ amocas.b a0, a0, 0(a0)
amoadd.b.aq a0, a0, 0(a0)
amoswap.b.aq a0, a0, 0(a0)
amoand.b.aq a0, a0, 0(a0)
@@ -17,6 +18,7 @@ target:
amomaxu.b.aq a0, a0, 0(a0)
amomin.b.aq a0, a0, 0(a0)
amominu.b.aq a0, a0, 0(a0)
+ amocas.b.aq a0, a0, 0(a0)
amoadd.b.rl a0, a0, 0(a0)
amoswap.b.rl a0, a0, 0(a0)
amoand.b.rl a0, a0, 0(a0)
@@ -26,6 +28,7 @@ target:
amomaxu.b.rl a0, a0, 0(a0)
amomin.b.rl a0, a0, 0(a0)
amominu.b.rl a0, a0, 0(a0)
+ amocas.b.rl a0, a0, 0(a0)
amoadd.b.aqrl a0, a0, 0(a0)
amoswap.b.aqrl a0, a0, 0(a0)
amoand.b.aqrl a0, a0, 0(a0)
@@ -35,6 +38,7 @@ target:
amomaxu.b.aqrl a0, a0, 0(a0)
amomin.b.aqrl a0, a0, 0(a0)
amominu.b.aqrl a0, a0, 0(a0)
+ amocas.b.aqrl a0, a0, 0(a0)
amoadd.h a0, a0, 0(a0)
amoswap.h a0, a0, 0(a0)
amoand.h a0, a0, 0(a0)
@@ -44,6 +48,7 @@ target:
amomaxu.h a0, a0, 0(a0)
amomin.h a0, a0, 0(a0)
amominu.h a0, a0, 0(a0)
+ amocas.h a0, a0, 0(a0)
amoadd.h.aq a0, a0, 0(a0)
amoswap.h.aq a0, a0, 0(a0)
amoand.h.aq a0, a0, 0(a0)
@@ -53,6 +58,7 @@ target:
amomaxu.h.aq a0, a0, 0(a0)
amomin.h.aq a0, a0, 0(a0)
amominu.h.aq a0, a0, 0(a0)
+ amocas.h.aq a0, a0, 0(a0)
amoadd.h.rl a0, a0, 0(a0)
amoswap.h.rl a0, a0, 0(a0)
amoand.h.rl a0, a0, 0(a0)
@@ -62,6 +68,7 @@ target:
amomaxu.h.rl a0, a0, 0(a0)
amomin.h.rl a0, a0, 0(a0)
amominu.h.rl a0, a0, 0(a0)
+ amocas.h.rl a0, a0, 0(a0)
amoadd.h.aqrl a0, a0, 0(a0)
amoswap.h.aqrl a0, a0, 0(a0)
amoand.h.aqrl a0, a0, 0(a0)
@@ -71,3 +78,4 @@ target:
amomaxu.h.aqrl a0, a0, 0(a0)
amomin.h.aqrl a0, a0, 0(a0)
amominu.h.aqrl a0, a0, 0(a0)
+ amocas.h.aqrl a0, a0, 0(a0)
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 8763cdf3543..f0e1d99a5a9 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -253,6 +253,8 @@
#define MASK_AMOMAXU_B 0xf800707f
#define MATCH_AMOSWAP_B 0x800002f
#define MASK_AMOSWAP_B 0xf800707f
+#define MATCH_AMOCAS_B 0x2800002f
+#define MASK_AMOCAS_B 0xf800707f
#define MATCH_AMOADD_H 0x102f
#define MASK_AMOADD_H 0xf800707f
#define MATCH_AMOXOR_H 0x2000102f
@@ -271,6 +273,8 @@
#define MASK_AMOMAXU_H 0xf800707f
#define MATCH_AMOSWAP_H 0x800102f
#define MASK_AMOSWAP_H 0xf800707f
+#define MATCH_AMOCAS_H 0x2800102f
+#define MASK_AMOCAS_H 0xf800707f
#define MATCH_ECALL 0x73
#define MASK_ECALL 0xffffffff
#define MATCH_EBREAK 0x100073
@@ -3728,6 +3732,7 @@ DECLARE_INSN(amomax_b, MATCH_AMOMAX_B, MASK_AMOMAX_B)
DECLARE_INSN(amominu_b, MATCH_AMOMINU_B, MASK_AMOMINU_B)
DECLARE_INSN(amomaxu_b, MATCH_AMOMAXU_B, MASK_AMOMAXU_B)
DECLARE_INSN(amoswap_b, MATCH_AMOSWAP_B, MASK_AMOSWAP_B)
+DECLARE_INSN(amocas_b, MATCH_AMOCAS_B, MASK_AMOCAS_B)
DECLARE_INSN(amoadd_h, MATCH_AMOADD_H, MASK_AMOADD_H)
DECLARE_INSN(amoxor_h, MATCH_AMOXOR_H, MASK_AMOXOR_H)
DECLARE_INSN(amoor_h, MATCH_AMOOR_H, MASK_AMOOR_H)
@@ -3737,6 +3742,7 @@ DECLARE_INSN(amomax_h, MATCH_AMOMAX_H, MASK_AMOMAX_H)
DECLARE_INSN(amominu_h, MATCH_AMOMINU_H, MASK_AMOMINU_H)
DECLARE_INSN(amomaxu_h, MATCH_AMOMAXU_H, MASK_AMOMAXU_H)
DECLARE_INSN(amoswap_h, MATCH_AMOSWAP_H, MASK_AMOSWAP_H)
+DECLARE_INSN(amocas_h, MATCH_AMOCAS_H, MASK_AMOCAS_H)
DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL)
DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK)
DECLARE_INSN(uret, MATCH_URET, MASK_URET)
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index ece2963d531..fedd47837e4 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -493,6 +493,7 @@ enum riscv_insn_class
INSN_CLASS_ZICBOZ,
INSN_CLASS_ZABHA,
INSN_CLASS_ZACAS,
+ INSN_CLASS_ZABHA_AND_ZACAS,
INSN_CLASS_H,
INSN_CLASS_XCVMAC,
INSN_CLASS_XCVALU,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index f7c0f5c7c83..fb098fac4c0 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -692,6 +692,7 @@ const struct riscv_opcode riscv_opcodes[] =
{"amomaxu.b", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAXU_B, MASK_AMOMAXU_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE },
{"amomin.b", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMIN_B, MASK_AMOMIN_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE },
{"amominu.b", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMINU_B, MASK_AMOMINU_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE },
+{"amocas.b", 0, INSN_CLASS_ZABHA_AND_ZACAS, "d,t,0(s)", MATCH_AMOCAS_B, MASK_AMOCAS_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE },
{"amoadd.b.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOADD_B|MASK_AQ, MASK_AMOADD_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE },
{"amoswap.b.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOSWAP_B|MASK_AQ, MASK_AMOSWAP_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE },
{"amoand.b.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOAND_B|MASK_AQ, MASK_AMOAND_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE },
@@ -701,6 +702,7 @@ const struct riscv_opcode riscv_opcodes[] =
{"amomaxu.b.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAXU_B|MASK_AQ, MASK_AMOMAXU_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE },
{"amomin.b.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMIN_B|MASK_AQ, MASK_AMOMIN_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE },
{"amominu.b.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMINU_B|MASK_AQ, MASK_AMOMINU_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE },
+{"amocas.b.aq", 0, INSN_CLASS_ZABHA_AND_ZACAS, "d,t,0(s)", MATCH_AMOCAS_B|MASK_AQ, MASK_AMOCAS_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE },
{"amoadd.b.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOADD_B|MASK_RL, MASK_AMOADD_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE },
{"amoswap.b.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOSWAP_B|MASK_RL, MASK_AMOSWAP_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE },
{"amoand.b.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOAND_B|MASK_RL, MASK_AMOAND_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE },
@@ -710,6 +712,7 @@ const struct riscv_opcode riscv_opcodes[] =
{"amomaxu.b.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAXU_B|MASK_RL, MASK_AMOMAXU_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE },
{"amomin.b.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMIN_B|MASK_RL, MASK_AMOMIN_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE },
{"amominu.b.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMINU_B|MASK_RL, MASK_AMOMINU_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE },
+{"amocas.b.rl", 0, INSN_CLASS_ZABHA_AND_ZACAS, "d,t,0(s)", MATCH_AMOCAS_B|MASK_RL, MASK_AMOCAS_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE },
{"amoadd.b.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOADD_B|MASK_AQRL, MASK_AMOADD_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE },
{"amoswap.b.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOSWAP_B|MASK_AQRL, MASK_AMOSWAP_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE },
{"amoand.b.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOAND_B|MASK_AQRL, MASK_AMOAND_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE },
@@ -719,6 +722,7 @@ const struct riscv_opcode riscv_opcodes[] =
{"amomaxu.b.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAXU_B|MASK_AQRL, MASK_AMOMAXU_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE },
{"amomin.b.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMIN_B|MASK_AQRL, MASK_AMOMIN_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE },
{"amominu.b.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMINU_B|MASK_AQRL, MASK_AMOMINU_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE },
+{"amocas.b.aqrl", 0, INSN_CLASS_ZABHA_AND_ZACAS, "d,t,0(s)", MATCH_AMOCAS_B|MASK_AQRL, MASK_AMOCAS_B|MASK_AQRL, match_opcode, INSN_DREF|INSN_1_BYTE },
{"amoadd.h", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOADD_H, MASK_AMOADD_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE },
{"amoswap.h", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOSWAP_H, MASK_AMOSWAP_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE },
{"amoand.h", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOAND_H, MASK_AMOAND_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE },
@@ -728,6 +732,7 @@ const struct riscv_opcode riscv_opcodes[] =
{"amomaxu.h", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAXU_H, MASK_AMOMAXU_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE },
{"amomin.h", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMIN_H, MASK_AMOMIN_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE },
{"amominu.h", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMINU_H, MASK_AMOMINU_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE },
+{"amocas.h", 0, INSN_CLASS_ZABHA_AND_ZACAS, "d,t,0(s)", MATCH_AMOCAS_H, MASK_AMOCAS_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE },
{"amoadd.h.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOADD_H|MASK_AQ, MASK_AMOADD_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE },
{"amoswap.h.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOSWAP_H|MASK_AQ, MASK_AMOSWAP_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE },
{"amoand.h.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOAND_H|MASK_AQ, MASK_AMOAND_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE },
@@ -737,6 +742,7 @@ const struct riscv_opcode riscv_opcodes[] =
{"amomaxu.h.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAXU_H|MASK_AQ, MASK_AMOMAXU_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE },
{"amomin.h.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMIN_H|MASK_AQ, MASK_AMOMIN_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE },
{"amominu.h.aq", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMINU_H|MASK_AQ, MASK_AMOMINU_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE },
+{"amocas.h.aq", 0, INSN_CLASS_ZABHA_AND_ZACAS, "d,t,0(s)", MATCH_AMOCAS_H|MASK_AQ, MASK_AMOCAS_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE },
{"amoadd.h.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOADD_H|MASK_RL, MASK_AMOADD_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE },
{"amoswap.h.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOSWAP_H|MASK_RL, MASK_AMOSWAP_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE },
{"amoand.h.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOAND_H|MASK_RL, MASK_AMOAND_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE },
@@ -746,6 +752,7 @@ const struct riscv_opcode riscv_opcodes[] =
{"amomaxu.h.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAXU_H|MASK_RL, MASK_AMOMAXU_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE },
{"amomin.h.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMIN_H|MASK_RL, MASK_AMOMIN_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE },
{"amominu.h.rl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMINU_H|MASK_RL, MASK_AMOMINU_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE },
+{"amocas.h.rl", 0, INSN_CLASS_ZABHA_AND_ZACAS, "d,t,0(s)", MATCH_AMOCAS_H|MASK_RL, MASK_AMOCAS_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE },
{"amoadd.h.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOADD_H|MASK_AQRL, MASK_AMOADD_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE },
{"amoswap.h.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOSWAP_H|MASK_AQRL, MASK_AMOSWAP_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE },
{"amoand.h.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOAND_H|MASK_AQRL, MASK_AMOAND_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE },
@@ -755,6 +762,7 @@ const struct riscv_opcode riscv_opcodes[] =
{"amomaxu.h.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMAXU_H|MASK_AQRL, MASK_AMOMAXU_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE },
{"amomin.h.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMIN_H|MASK_AQRL, MASK_AMOMIN_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE },
{"amominu.h.aqrl", 0, INSN_CLASS_ZABHA, "d,t,0(s)", MATCH_AMOMINU_H|MASK_AQRL, MASK_AMOMINU_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE },
+{"amocas.h.aqrl", 0, INSN_CLASS_ZABHA_AND_ZACAS, "d,t,0(s)", MATCH_AMOCAS_H|MASK_AQRL, MASK_AMOCAS_H|MASK_AQRL, match_opcode, INSN_DREF|INSN_2_BYTE },
/* Zacas instruction subset. */
{"amocas.w", 0, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_AMOCAS_W, MASK_AMOCAS_W|MASK_AQRL, match_opcode, INSN_DREF|INSN_4_BYTE },
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