[binutils-gdb] aarch64: Add FP8 Neon and SVE multiplication instructions
Richard Earnshaw
rearnsha@sourceware.org
Mon Jun 24 15:51:10 GMT 2024
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=59b78ab1c16356c2b5a9a1cba40c4029f84ed409
commit 59b78ab1c16356c2b5a9a1cba40c4029f84ed409
Author: Andrew Carlotti <andrew.carlotti@arm.com>
Date: Fri Jun 21 19:31:34 2024 +0100
aarch64: Add FP8 Neon and SVE multiplication instructions
This includes all the instructions under the following features:
- FEAT_FP8FMA (+fp8fma)
- FEAT_FP8DOT4 (+fp8dot4)
- FEAT_FP8DOT2 (+fp8dot2)
- FEAT_SSVE_FP8FMA (+ssve-fp8fma)
- FEAT_SSVE_FP8DOT4 (+ssve-fp8dot4)
- FEAT_SSVE_FP8DOT2 (+ssve-fp8dot2)
Diff:
---
gas/config/tc-aarch64.c | 26 +-
gas/doc/c-aarch64.texi | 12 +
gas/testsuite/gas/aarch64/fp8-mul-illegal.d | 2 +
gas/testsuite/gas/aarch64/fp8-mul-illegal.l | 24 +
gas/testsuite/gas/aarch64/fp8-mul-illegal.s | 24 +
gas/testsuite/gas/aarch64/fp8-simd-dot2.d | 25 +
gas/testsuite/gas/aarch64/fp8-simd-dot2.s | 19 +
gas/testsuite/gas/aarch64/fp8-simd-dot4.d | 21 +
gas/testsuite/gas/aarch64/fp8-simd-dot4.s | 15 +
gas/testsuite/gas/aarch64/fp8-simd-fma.d | 51 ++
gas/testsuite/gas/aarch64/fp8-simd-fma.s | 53 ++
gas/testsuite/gas/aarch64/fp8-sve-dot2.d | 18 +
gas/testsuite/gas/aarch64/fp8-sve-dot2.s | 9 +
gas/testsuite/gas/aarch64/fp8-sve-dot4.d | 18 +
gas/testsuite/gas/aarch64/fp8-sve-dot4.s | 9 +
gas/testsuite/gas/aarch64/fp8-sve-fma.d | 64 ++
gas/testsuite/gas/aarch64/fp8-sve-fma.s | 65 ++
gas/testsuite/gas/aarch64/fp8-sve-mul-illegal.d | 2 +
gas/testsuite/gas/aarch64/fp8-sve-mul-illegal.l | 21 +
gas/testsuite/gas/aarch64/fp8-sve-mul-illegal.s | 35 +
gas/testsuite/gas/aarch64/illegal-sve2.l | 8 +-
include/opcode/aarch64.h | 37 +-
opcodes/aarch64-asm-2.c | 254 +++----
opcodes/aarch64-asm.c | 12 +-
opcodes/aarch64-dis-2.c | 848 +++++++++++++++++-------
opcodes/aarch64-dis.c | 15 +
opcodes/aarch64-opc-2.c | 2 +
opcodes/aarch64-opc.c | 16 +-
opcodes/aarch64-opc.h | 2 +
opcodes/aarch64-tbl.h | 112 ++++
30 files changed, 1432 insertions(+), 387 deletions(-)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 2bd87d149b8..88e0e6e1926 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -820,6 +820,10 @@ vectype_to_qualifier (const struct vector_type_el *vectype)
if (vectype->defined & (NTA_HASINDEX | NTA_HASVARWIDTH))
{
+ /* Special case S_2B. */
+ if (vectype->type == NT_b && vectype->width == 2)
+ return AARCH64_OPND_QLF_S_2B;
+
/* Special case S_4B. */
if (vectype->type == NT_b && vectype->width == 4)
return AARCH64_OPND_QLF_S_4B;
@@ -1010,7 +1014,7 @@ aarch64_reg_parse_32_64 (char **ccp, aarch64_opnd_qualifier_t *qualifier)
succeeds; otherwise return FALSE.
Accept only one occurrence of:
- 4b 8b 16b 2h 4h 8h 2s 4s 1d 2d
+ 2b 4b 8b 16b 2h 4h 8h 2s 4s 1d 2d
b h s d q */
static bool
parse_vector_type_for_operand (aarch64_reg_type reg_type,
@@ -1074,6 +1078,7 @@ parse_vector_type_for_operand (aarch64_reg_type reg_type,
if (width != 0 && width * element_size != 64
&& width * element_size != 128
&& !(width == 2 && element_size == 16)
+ && !(width == 2 && element_size == 8)
&& !(width == 4 && element_size == 8))
{
first_error_fmt (_
@@ -6334,6 +6339,7 @@ process_omitted_operand (enum aarch64_opnd type, const aarch64_opcode *opcode,
case AARCH64_OPND_En:
case AARCH64_OPND_Em:
case AARCH64_OPND_Em16:
+ case AARCH64_OPND_Em8:
case AARCH64_OPND_SM3_IMM2:
operand->reglane.regno = default_value;
break;
@@ -6855,6 +6861,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
case AARCH64_OPND_SVE_Zm3_22_INDEX:
case AARCH64_OPND_SVE_Zm3_19_INDEX:
case AARCH64_OPND_SVE_Zm3_11_INDEX:
+ case AARCH64_OPND_SVE_Zm3_10_INDEX:
case AARCH64_OPND_SVE_Zm4_11_INDEX:
case AARCH64_OPND_SVE_Zm4_INDEX:
case AARCH64_OPND_SVE_Zn_INDEX:
@@ -6880,6 +6887,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
case AARCH64_OPND_En:
case AARCH64_OPND_Em:
case AARCH64_OPND_Em16:
+ case AARCH64_OPND_Em8:
case AARCH64_OPND_SM3_IMM2:
reg_type = REG_TYPE_V;
vector_reg_index:
@@ -10681,6 +10689,15 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
{"lut", AARCH64_FEATURE (LUT), AARCH64_FEATURE (SIMD)},
{"brbe", AARCH64_FEATURE (BRBE), AARCH64_NO_FEATURES},
{"sme-lutv2", AARCH64_FEATURE (SME_LUTv2), AARCH64_FEATURE (SME2)},
+ {"fp8fma", AARCH64_FEATURE (FP8FMA), AARCH64_FEATURE (FP8)},
+ {"fp8dot4", AARCH64_FEATURE (FP8DOT4), AARCH64_FEATURE (FP8FMA)},
+ {"fp8dot2", AARCH64_FEATURE (FP8DOT2), AARCH64_FEATURE (FP8DOT4)},
+ {"ssve-fp8fma", AARCH64_FEATURE (SSVE_FP8FMA),
+ AARCH64_FEATURES (2, FP8, SME2)},
+ {"ssve-fp8dot4", AARCH64_FEATURE (SSVE_FP8DOT4),
+ AARCH64_FEATURE (SSVE_FP8FMA)},
+ {"ssve-fp8dot2", AARCH64_FEATURE (SSVE_FP8DOT2),
+ AARCH64_FEATURE (SSVE_FP8DOT4)},
{NULL, AARCH64_NO_FEATURES, AARCH64_NO_FEATURES},
};
@@ -10693,7 +10710,12 @@ struct aarch64_virtual_dependency_table
};
static const struct aarch64_virtual_dependency_table aarch64_dependencies[] = {
- {AARCH64_NO_FEATURES, AARCH64_NO_FEATURES}
+ {AARCH64_FEATURES (2, FP8FMA, SVE2), AARCH64_FEATURE (FP8FMA_SVE)},
+ {AARCH64_FEATURE (SSVE_FP8FMA), AARCH64_FEATURE (FP8FMA_SVE)},
+ {AARCH64_FEATURES (2, FP8DOT4, SVE2), AARCH64_FEATURE (FP8DOT4_SVE)},
+ {AARCH64_FEATURE (SSVE_FP8DOT4), AARCH64_FEATURE (FP8DOT4_SVE)},
+ {AARCH64_FEATURES (2, FP8DOT2, SVE2), AARCH64_FEATURE (FP8DOT2_SVE)},
+ {AARCH64_FEATURE (SSVE_FP8DOT2), AARCH64_FEATURE (FP8DOT2_SVE)},
};
static aarch64_feature_set
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 41a8d7e4a44..a73b6c336a7 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -197,6 +197,12 @@ automatically cause those extensions to be disabled.
@tab Enable floating-point extensions.
@item @code{fp8} @tab
@tab Enable the Floating Point 8 (FP8) extension.
+@item @code{fp8dot2} @tab @code{fp8dot4}
+ @tab Enable the FP8 2-way dot product instructions.
+@item @code{fp8dot4} @tab @code{fp8fma}
+ @tab Enable the FP8 4-way dot product instructions.
+@item @code{fp8fma} @tab @code{fp8}
+ @tab Enable the FP8 FMA instructions.
@item @code{fp16fml} @tab @code{fp16}
@tab Enable Armv8.2 16-bit floating-point multiplication variant support.
@item @code{fp16} @tab @code{fp}
@@ -277,6 +283,12 @@ automatically cause those extensions to be disabled.
@tab Enable SME2.1.
@item @code{ssbs} @tab
@tab Enable Speculative Store Bypassing Safe state read and write.
+@item @code{ssve-fp8dot2} @tab @code{ssve-fp8dot4}
+ @tab Enable the Streaming SVE FP8 2-way dot product instructions. These can also be enabled using @code{+fp8dot2+sme2}.
+@item @code{ssve-fp8dot4} @tab @code{ssve-fp8fma}
+ @tab Enable the Streaming SVE FP8 4-way dot product instructions. These can also be enabled using @code{+fp8dot4+sme2}.
+@item @code{ssve-fp8fma} @tab @code{sme2}, @code{fp8}
+ @tab Enable the Streaming SVE FP8 FMA instructions. These can also be enabled using @code{+fp8fma+sme2}.
@item @code{sve} @tab @code{fcma}
@tab Enable the Scalable Vector Extension.
@item @code{sve2} @tab @code{sve}
diff --git a/gas/testsuite/gas/aarch64/fp8-mul-illegal.d b/gas/testsuite/gas/aarch64/fp8-mul-illegal.d
new file mode 100644
index 00000000000..1dac59a5d82
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fp8-mul-illegal.d
@@ -0,0 +1,2 @@
+#as: -march=armv8-a+fp8dot2
+#error_output: fp8-mul-illegal.l
diff --git a/gas/testsuite/gas/aarch64/fp8-mul-illegal.l b/gas/testsuite/gas/aarch64/fp8-mul-illegal.l
new file mode 100644
index 00000000000..155c24b035c
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fp8-mul-illegal.l
@@ -0,0 +1,24 @@
+[^:]*: Assembler messages:
+[^:]*:1: Error: register number out of range 0 to 15 at operand 3 -- `fdot v0\.4h,v0\.8b,v16\.2b\[0\]'
+[^:]*:2: Error: register element index out of range 0 to 7 at operand 3 -- `fdot v0\.4h,v0\.8b,v0\.2b\[8\]'
+[^:]*:3: Error: register number out of range 0 to 15 at operand 3 -- `fdot v0\.8h,v0\.16b,v16\.2b\[0\]'
+[^:]*:4: Error: register element index out of range 0 to 7 at operand 3 -- `fdot v0\.8h,v0\.16b,v0\.2b\[8\]'
+[^:]*:6: Error: operand mismatch -- `fmlalb v0\.4h,v0\.8b,v0\.8b'
+[^:]*:6: Info: did you mean this\?
+[^:]*:6: Info: \tfmlalb v0\.8h, v0\.16b, v0\.16b
+[^:]*:8: Error: register number out of range 0 to 7 at operand 3 -- `fmlalb v0\.8h,v0\.16b,v8\.b\[0\]'
+[^:]*:9: Error: register element index out of range 0 to 15 at operand 3 -- `fmlalb v0\.8h,v0\.16b,v0\.b\[16\]'
+[^:]*:10: Error: register number out of range 0 to 7 at operand 3 -- `fmlalt v0\.8h,v0\.16b,v8\.b\[0\]'
+[^:]*:11: Error: register element index out of range 0 to 15 at operand 3 -- `fmlalt v0\.8h,v0\.16b,v0\.b\[16\]'
+[^:]*:13: Error: operand mismatch -- `fmlallbb v0\.2s,v0\.8b,v0\.8b'
+[^:]*:13: Info: did you mean this\?
+[^:]*:13: Info: \tfmlallbb v0\.4s, v0\.16b, v0\.16b
+[^:]*:15: Error: register number out of range 0 to 7 at operand 3 -- `fmlallbb v0\.4s,v0\.16b,v8\.b\[0\]'
+[^:]*:16: Error: register element index out of range 0 to 15 at operand 3 -- `fmlallbb v0\.4s,v0\.16b,v0\.b\[16\]'
+[^:]*:17: Error: register number out of range 0 to 7 at operand 3 -- `fmlallbt v0\.4s,v0\.16b,v8\.b\[0\]'
+[^:]*:18: Error: register element index out of range 0 to 15 at operand 3 -- `fmlallbt v0\.4s,v0\.16b,v0\.b\[16\]'
+[^:]*:19: Error: register number out of range 0 to 7 at operand 3 -- `fmlalltb v0\.4s,v0\.16b,v8\.b\[0\]'
+[^:]*:20: Error: register element index out of range 0 to 15 at operand 3 -- `fmlalltb v0\.4s,v0\.16b,v0\.b\[16\]'
+[^:]*:21: Error: register number out of range 0 to 7 at operand 3 -- `fmlalltt v0\.4s,v0\.16b,v8\.b\[0\]'
+[^:]*:22: Error: register element index out of range 0 to 15 at operand 3 -- `fmlalltt v0\.4s,v0\.16b,v0\.b\[16\]'
+
diff --git a/gas/testsuite/gas/aarch64/fp8-mul-illegal.s b/gas/testsuite/gas/aarch64/fp8-mul-illegal.s
new file mode 100644
index 00000000000..1b75cb68a1d
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fp8-mul-illegal.s
@@ -0,0 +1,24 @@
+fdot v0.4h, v0.8b, v16.2b[0]
+fdot v0.4h, v0.8b, v0.2b[8]
+fdot v0.8h, v0.16b, v16.2b[0]
+fdot v0.8h, v0.16b, v0.2b[8]
+
+fmlalb v0.4h, v0.8b, v0.8b
+
+fmlalb v0.8h, v0.16b, v8.b[0]
+fmlalb v0.8h, v0.16b, v0.b[16]
+fmlalt v0.8h, v0.16b, v8.b[0]
+fmlalt v0.8h, v0.16b, v0.b[16]
+
+fmlallbb v0.2s, v0.8b, v0.8b
+
+fmlallbb v0.4s, v0.16b, v8.b[0]
+fmlallbb v0.4s, v0.16b, v0.b[16]
+fmlallbt v0.4s, v0.16b, v8.b[0]
+fmlallbt v0.4s, v0.16b, v0.b[16]
+fmlalltb v0.4s, v0.16b, v8.b[0]
+fmlalltb v0.4s, v0.16b, v0.b[16]
+fmlalltt v0.4s, v0.16b, v8.b[0]
+fmlalltt v0.4s, v0.16b, v0.b[16]
+
+
diff --git a/gas/testsuite/gas/aarch64/fp8-simd-dot2.d b/gas/testsuite/gas/aarch64/fp8-simd-dot2.d
new file mode 100644
index 00000000000..7d740b711d2
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fp8-simd-dot2.d
@@ -0,0 +1,25 @@
+#as: -march=armv8-a+fp8dot2
+#objdump: -dr
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+
+0+ <\.text>:
+ *[0-9a-f]+: 0e40fc00 fdot v0\.4h, v0\.8b, v0\.8b
+ *[0-9a-f]+: 0e5dff77 fdot v23\.4h, v27\.8b, v29\.8b
+ *[0-9a-f]+: 0e53feb9 fdot v25\.4h, v21\.8b, v19\.8b
+ *[0-9a-f]+: 4e40fc00 fdot v0\.8h, v0\.16b, v0\.16b
+ *[0-9a-f]+: 4e5dff77 fdot v23\.8h, v27\.16b, v29\.16b
+ *[0-9a-f]+: 4e53feb9 fdot v25\.8h, v21\.16b, v19\.16b
+ *[0-9a-f]+: 0f400000 fdot v0\.4h, v0\.8b, v0\.2b\[0\]
+ *[0-9a-f]+: 0f500000 fdot v0\.4h, v0\.8b, v0\.2b\[1\]
+ *[0-9a-f]+: 0f6e0377 fdot v23\.4h, v27\.8b, v14\.2b\[2\]
+ *[0-9a-f]+: 0f4d0ab9 fdot v25\.4h, v21\.8b, v13\.2b\[4\]
+ *[0-9a-f]+: 0f7d0ab9 fdot v25\.4h, v21\.8b, v13\.2b\[7\]
+ *[0-9a-f]+: 4f400000 fdot v0\.8h, v0\.16b, v0\.2b\[0\]
+ *[0-9a-f]+: 4f500000 fdot v0\.8h, v0\.16b, v0\.2b\[1\]
+ *[0-9a-f]+: 4f6e0377 fdot v23\.8h, v27\.16b, v14\.2b\[2\]
+ *[0-9a-f]+: 4f4d0ab9 fdot v25\.8h, v21\.16b, v13\.2b\[4\]
+ *[0-9a-f]+: 4f7d0ab9 fdot v25\.8h, v21\.16b, v13\.2b\[7\]
diff --git a/gas/testsuite/gas/aarch64/fp8-simd-dot2.s b/gas/testsuite/gas/aarch64/fp8-simd-dot2.s
new file mode 100644
index 00000000000..3fff78afbc9
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fp8-simd-dot2.s
@@ -0,0 +1,19 @@
+fdot v0.4h, v0.8b, v0.8b
+fdot v23.4h, v27.8b, v29.8b
+fdot v25.4h, v21.8b, v19.8b
+
+fdot v0.8h, v0.16b, v0.16b
+fdot v23.8h, v27.16b, v29.16b
+fdot v25.8h, v21.16b, v19.16b
+
+fdot v0.4h, v0.8b, v0.2b[0]
+fdot v0.4h, v0.8b, v0.2b[1]
+fdot v23.4h, v27.8b, v14.2b[2]
+fdot v25.4h, v21.8b, v13.2b[4]
+fdot v25.4h, v21.8b, v13.2b[7]
+
+fdot v0.8h, v0.16b, v0.2b[0]
+fdot v0.8h, v0.16b, v0.2b[1]
+fdot v23.8h, v27.16b, v14.2b[2]
+fdot v25.8h, v21.16b, v13.2b[4]
+fdot v25.8h, v21.16b, v13.2b[7]
diff --git a/gas/testsuite/gas/aarch64/fp8-simd-dot4.d b/gas/testsuite/gas/aarch64/fp8-simd-dot4.d
new file mode 100644
index 00000000000..bf4632c30dd
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fp8-simd-dot4.d
@@ -0,0 +1,21 @@
+#as: -march=armv8-a+fp8dot4
+#objdump: -dr
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+
+0+ <\.text>:
+ *[0-9a-f]+: 0e00fc00 fdot v0\.2s, v0\.8b, v0\.8b
+ *[0-9a-f]+: 0e1dff77 fdot v23\.2s, v27\.8b, v29\.8b
+ *[0-9a-f]+: 0e13feb9 fdot v25\.2s, v21\.8b, v19\.8b
+ *[0-9a-f]+: 4e00fc00 fdot v0\.4s, v0\.16b, v0\.16b
+ *[0-9a-f]+: 4e1dff77 fdot v23\.4s, v27\.16b, v29\.16b
+ *[0-9a-f]+: 4e13feb9 fdot v25\.4s, v21\.16b, v19\.16b
+ *[0-9a-f]+: 0f000000 fdot v0\.2s, v0\.8b, v0\.4b\[0\]
+ *[0-9a-f]+: 0f3d0377 fdot v23\.2s, v27\.8b, v29\.4b\[1\]
+ *[0-9a-f]+: 0f330ab9 fdot v25\.2s, v21\.8b, v19\.4b\[3\]
+ *[0-9a-f]+: 4f000000 fdot v0\.4s, v0\.16b, v0\.4b\[0\]
+ *[0-9a-f]+: 4f3d0377 fdot v23\.4s, v27\.16b, v29\.4b\[1\]
+ *[0-9a-f]+: 4f330ab9 fdot v25\.4s, v21\.16b, v19\.4b\[3\]
diff --git a/gas/testsuite/gas/aarch64/fp8-simd-dot4.s b/gas/testsuite/gas/aarch64/fp8-simd-dot4.s
new file mode 100644
index 00000000000..cfd7283aed6
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fp8-simd-dot4.s
@@ -0,0 +1,15 @@
+fdot v0.2s, v0.8b, v0.8b
+fdot v23.2s, v27.8b, v29.8b
+fdot v25.2s, v21.8b, v19.8b
+
+fdot v0.4s, v0.16b, v0.16b
+fdot v23.4s, v27.16b, v29.16b
+fdot v25.4s, v21.16b, v19.16b
+
+fdot v0.2s, v0.8b, v0.4b[0]
+fdot v23.2s, v27.8b, v29.4b[1]
+fdot v25.2s, v21.8b, v19.4b[3]
+
+fdot v0.4s, v0.16b, v0.4b[0]
+fdot v23.4s, v27.16b, v29.4b[1]
+fdot v25.4s, v21.16b, v19.4b[3]
diff --git a/gas/testsuite/gas/aarch64/fp8-simd-fma.d b/gas/testsuite/gas/aarch64/fp8-simd-fma.d
new file mode 100644
index 00000000000..c9c8be6ef13
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fp8-simd-fma.d
@@ -0,0 +1,51 @@
+#as: -march=armv8-a+fp8fma
+#objdump: -dr
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+
+0+ <\.text>:
+ *[0-9a-f]+: 0ec0fc00 fmlalb v0\.8h, v0\.16b, v0\.16b
+ *[0-9a-f]+: 0eddff77 fmlalb v23\.8h, v27\.16b, v29\.16b
+ *[0-9a-f]+: 0ed3feb9 fmlalb v25\.8h, v21\.16b, v19\.16b
+ *[0-9a-f]+: 4ec0fc00 fmlalt v0\.8h, v0\.16b, v0\.16b
+ *[0-9a-f]+: 4eddff77 fmlalt v23\.8h, v27\.16b, v29\.16b
+ *[0-9a-f]+: 4ed3feb9 fmlalt v25\.8h, v21\.16b, v19\.16b
+ *[0-9a-f]+: 0fc00000 fmlalb v0\.8h, v0\.16b, v0\.b\[0\]
+ *[0-9a-f]+: 0fdd0377 fmlalb v23\.8h, v27\.16b, v5\.b\[3\]
+ *[0-9a-f]+: 0fe702b9 fmlalb v25\.8h, v21\.16b, v7\.b\[4\]
+ *[0-9a-f]+: 0fc70ab9 fmlalb v25\.8h, v21\.16b, v7\.b\[8\]
+ *[0-9a-f]+: 4fc00000 fmlalt v0\.8h, v0\.16b, v0\.b\[0\]
+ *[0-9a-f]+: 4fdd0377 fmlalt v23\.8h, v27\.16b, v5\.b\[3\]
+ *[0-9a-f]+: 4fe702b9 fmlalt v25\.8h, v21\.16b, v7\.b\[4\]
+ *[0-9a-f]+: 4fc70ab9 fmlalt v25\.8h, v21\.16b, v7\.b\[8\]
+ *[0-9a-f]+: 0e00c400 fmlallbb v0\.4s, v0\.16b, v0\.16b
+ *[0-9a-f]+: 0e1dc777 fmlallbb v23\.4s, v27\.16b, v29\.16b
+ *[0-9a-f]+: 0e13c6b9 fmlallbb v25\.4s, v21\.16b, v19\.16b
+ *[0-9a-f]+: 0e40c400 fmlallbt v0\.4s, v0\.16b, v0\.16b
+ *[0-9a-f]+: 0e5dc777 fmlallbt v23\.4s, v27\.16b, v29\.16b
+ *[0-9a-f]+: 0e53c6b9 fmlallbt v25\.4s, v21\.16b, v19\.16b
+ *[0-9a-f]+: 4e00c400 fmlalltb v0\.4s, v0\.16b, v0\.16b
+ *[0-9a-f]+: 4e1dc777 fmlalltb v23\.4s, v27\.16b, v29\.16b
+ *[0-9a-f]+: 4e13c6b9 fmlalltb v25\.4s, v21\.16b, v19\.16b
+ *[0-9a-f]+: 4e40c400 fmlalltt v0\.4s, v0\.16b, v0\.16b
+ *[0-9a-f]+: 4e5dc777 fmlalltt v23\.4s, v27\.16b, v29\.16b
+ *[0-9a-f]+: 4e53c6b9 fmlalltt v25\.4s, v21\.16b, v19\.16b
+ *[0-9a-f]+: 2f008000 fmlallbb v0\.4s, v0\.16b, v0\.b\[0\]
+ *[0-9a-f]+: 2f1d8377 fmlallbb v23\.4s, v27\.16b, v5\.b\[3\]
+ *[0-9a-f]+: 2f2782b9 fmlallbb v25\.4s, v21\.16b, v7\.b\[4\]
+ *[0-9a-f]+: 2f078ab9 fmlallbb v25\.4s, v21\.16b, v7\.b\[8\]
+ *[0-9a-f]+: 2f408000 fmlallbt v0\.4s, v0\.16b, v0\.b\[0\]
+ *[0-9a-f]+: 2f5d8377 fmlallbt v23\.4s, v27\.16b, v5\.b\[3\]
+ *[0-9a-f]+: 2f6782b9 fmlallbt v25\.4s, v21\.16b, v7\.b\[4\]
+ *[0-9a-f]+: 2f478ab9 fmlallbt v25\.4s, v21\.16b, v7\.b\[8\]
+ *[0-9a-f]+: 6f008000 fmlalltb v0\.4s, v0\.16b, v0\.b\[0\]
+ *[0-9a-f]+: 6f1d8377 fmlalltb v23\.4s, v27\.16b, v5\.b\[3\]
+ *[0-9a-f]+: 6f2782b9 fmlalltb v25\.4s, v21\.16b, v7\.b\[4\]
+ *[0-9a-f]+: 6f078ab9 fmlalltb v25\.4s, v21\.16b, v7\.b\[8\]
+ *[0-9a-f]+: 6f408000 fmlalltt v0\.4s, v0\.16b, v0\.b\[0\]
+ *[0-9a-f]+: 6f5d8377 fmlalltt v23\.4s, v27\.16b, v5\.b\[3\]
+ *[0-9a-f]+: 6f6782b9 fmlalltt v25\.4s, v21\.16b, v7\.b\[4\]
+ *[0-9a-f]+: 6f478ab9 fmlalltt v25\.4s, v21\.16b, v7\.b\[8\]
diff --git a/gas/testsuite/gas/aarch64/fp8-simd-fma.s b/gas/testsuite/gas/aarch64/fp8-simd-fma.s
new file mode 100644
index 00000000000..be7951465a0
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fp8-simd-fma.s
@@ -0,0 +1,53 @@
+fmlalb v0.8h, v0.16b, v0.16b
+fmlalb v23.8h, v27.16b, v29.16b
+fmlalb v25.8h, v21.16b, v19.16b
+
+fmlalt v0.8h, v0.16b, v0.16b
+fmlalt v23.8h, v27.16b, v29.16b
+fmlalt v25.8h, v21.16b, v19.16b
+
+fmlalb v0.8h, v0.16b, v0.b[0]
+fmlalb v23.8h, v27.16b, v5.b[3]
+fmlalb v25.8h, v21.16b, v7.b[4]
+fmlalb v25.8h, v21.16b, v7.b[8]
+
+fmlalt v0.8h, v0.16b, v0.b[0]
+fmlalt v23.8h, v27.16b, v5.b[3]
+fmlalt v25.8h, v21.16b, v7.b[4]
+fmlalt v25.8h, v21.16b, v7.b[8]
+
+fmlallbb v0.4s, v0.16b, v0.16b
+fmlallbb v23.4s, v27.16b, v29.16b
+fmlallbb v25.4s, v21.16b, v19.16b
+
+fmlallbt v0.4s, v0.16b, v0.16b
+fmlallbt v23.4s, v27.16b, v29.16b
+fmlallbt v25.4s, v21.16b, v19.16b
+
+fmlalltb v0.4s, v0.16b, v0.16b
+fmlalltb v23.4s, v27.16b, v29.16b
+fmlalltb v25.4s, v21.16b, v19.16b
+
+fmlalltt v0.4s, v0.16b, v0.16b
+fmlalltt v23.4s, v27.16b, v29.16b
+fmlalltt v25.4s, v21.16b, v19.16b
+
+fmlallbb v0.4s, v0.16b, v0.b[0]
+fmlallbb v23.4s, v27.16b, v5.b[3]
+fmlallbb v25.4s, v21.16b, v7.b[4]
+fmlallbb v25.4s, v21.16b, v7.b[8]
+
+fmlallbt v0.4s, v0.16b, v0.b[0]
+fmlallbt v23.4s, v27.16b, v5.b[3]
+fmlallbt v25.4s, v21.16b, v7.b[4]
+fmlallbt v25.4s, v21.16b, v7.b[8]
+
+fmlalltb v0.4s, v0.16b, v0.b[0]
+fmlalltb v23.4s, v27.16b, v5.b[3]
+fmlalltb v25.4s, v21.16b, v7.b[4]
+fmlalltb v25.4s, v21.16b, v7.b[8]
+
+fmlalltt v0.4s, v0.16b, v0.b[0]
+fmlalltt v23.4s, v27.16b, v5.b[3]
+fmlalltt v25.4s, v21.16b, v7.b[4]
+fmlalltt v25.4s, v21.16b, v7.b[8]
diff --git a/gas/testsuite/gas/aarch64/fp8-sve-dot2.d b/gas/testsuite/gas/aarch64/fp8-sve-dot2.d
new file mode 100644
index 00000000000..d2633aa8453
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fp8-sve-dot2.d
@@ -0,0 +1,18 @@
+#as: -march=armv8-a+sve2+fp8dot2
+#as: -march=armv8-a+ssve-fp8dot2
+#objdump: -dr
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+
+0+ <\.text>:
+ *[0-9a-f]+: 64208400 fdot z0\.h, z0\.b, z0\.b
+ *[0-9a-f]+: 643d8777 fdot z23\.h, z27\.b, z29\.b
+ *[0-9a-f]+: 0420bff9 movprfx z25, z31
+ *[0-9a-f]+: 643386b9 fdot z25\.h, z21\.b, z19\.b
+ *[0-9a-f]+: 64204400 fdot z0\.h, z0\.b, z0\.b\[0\]
+ *[0-9a-f]+: 642d4f77 fdot z23\.h, z27\.b, z5\.b\[3\]
+ *[0-9a-f]+: 0420bff9 movprfx z25, z31
+ *[0-9a-f]+: 643f4eb9 fdot z25\.h, z21\.b, z7\.b\[7\]
diff --git a/gas/testsuite/gas/aarch64/fp8-sve-dot2.s b/gas/testsuite/gas/aarch64/fp8-sve-dot2.s
new file mode 100644
index 00000000000..839222eb7ea
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fp8-sve-dot2.s
@@ -0,0 +1,9 @@
+fdot z0.h, z0.b, z0.b
+fdot z23.h, z27.b, z29.b
+movprfx z25, z31
+fdot z25.h, z21.b, z19.b
+
+fdot z0.h, z0.b, z0.b[0]
+fdot z23.h, z27.b, z5.b[3]
+movprfx z25, z31
+fdot z25.h, z21.b, z7.b[7]
diff --git a/gas/testsuite/gas/aarch64/fp8-sve-dot4.d b/gas/testsuite/gas/aarch64/fp8-sve-dot4.d
new file mode 100644
index 00000000000..ffb8d4ce18b
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fp8-sve-dot4.d
@@ -0,0 +1,18 @@
+#as: -march=armv8-a+sve2+fp8dot4
+#as: -march=armv8-a+ssve-fp8dot4
+#objdump: -dr
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+
+0+ <\.text>:
+ *[0-9a-f]+: 64608400 fdot z0\.s, z0\.b, z0\.b
+ *[0-9a-f]+: 647d8777 fdot z23\.s, z27\.b, z29\.b
+ *[0-9a-f]+: 0420bff9 movprfx z25, z31
+ *[0-9a-f]+: 647386b9 fdot z25\.s, z21\.b, z19\.b
+ *[0-9a-f]+: 64604400 fdot z0\.s, z0\.b, z0\.b\[0\]
+ *[0-9a-f]+: 646d4777 fdot z23\.s, z27\.b, z5\.b\[1\]
+ *[0-9a-f]+: 0420bff9 movprfx z25, z31
+ *[0-9a-f]+: 647f46b9 fdot z25\.s, z21\.b, z7\.b\[3\]
diff --git a/gas/testsuite/gas/aarch64/fp8-sve-dot4.s b/gas/testsuite/gas/aarch64/fp8-sve-dot4.s
new file mode 100644
index 00000000000..5cb8227f040
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fp8-sve-dot4.s
@@ -0,0 +1,9 @@
+fdot z0.s, z0.b, z0.b
+fdot z23.s, z27.b, z29.b
+movprfx z25, z31
+fdot z25.s, z21.b, z19.b
+
+fdot z0.s, z0.b, z0.b[0]
+fdot z23.s, z27.b, z5.b[1]
+movprfx z25, z31
+fdot z25.s, z21.b, z7.b[3]
diff --git a/gas/testsuite/gas/aarch64/fp8-sve-fma.d b/gas/testsuite/gas/aarch64/fp8-sve-fma.d
new file mode 100644
index 00000000000..97eae9e8c00
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fp8-sve-fma.d
@@ -0,0 +1,64 @@
+#as: -march=armv8-a+sve2+fp8fma
+#as: -march=armv8-a+ssve-fp8fma
+#objdump: -dr
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+
+0+ <\.text>:
+ *[0-9a-f]+: 64a08800 fmlalb z0\.h, z0\.b, z0\.b
+ *[0-9a-f]+: 64bd8b77 fmlalb z23\.h, z27\.b, z29\.b
+ *[0-9a-f]+: 0420bff9 movprfx z25, z31
+ *[0-9a-f]+: 64b38ab9 fmlalb z25\.h, z21\.b, z19\.b
+ *[0-9a-f]+: 64205000 fmlalb z0\.h, z0\.b, z0\.b\[0\]
+ *[0-9a-f]+: 64255777 fmlalb z23\.h, z27\.b, z5\.b\[1\]
+ *[0-9a-f]+: 0420bff9 movprfx z25, z31
+ *[0-9a-f]+: 642f5ab9 fmlalb z25\.h, z21\.b, z7\.b\[6\]
+ *[0-9a-f]+: 643f5eb9 fmlalb z25\.h, z21\.b, z7\.b\[15\]
+ *[0-9a-f]+: 64208800 fmlallbb z0\.s, z0\.b, z0\.b
+ *[0-9a-f]+: 643d8b77 fmlallbb z23\.s, z27\.b, z29\.b
+ *[0-9a-f]+: 0420bff9 movprfx z25, z31
+ *[0-9a-f]+: 64338ab9 fmlallbb z25\.s, z21\.b, z19\.b
+ *[0-9a-f]+: 6420c000 fmlallbb z0\.s, z0\.b, z0\.b\[0\]
+ *[0-9a-f]+: 6425c777 fmlallbb z23\.s, z27\.b, z5\.b\[1\]
+ *[0-9a-f]+: 0420bff9 movprfx z25, z31
+ *[0-9a-f]+: 642fcab9 fmlallbb z25\.s, z21\.b, z7\.b\[6\]
+ *[0-9a-f]+: 643fceb9 fmlallbb z25\.s, z21\.b, z7\.b\[15\]
+ *[0-9a-f]+: 64209800 fmlallbt z0\.s, z0\.b, z0\.b
+ *[0-9a-f]+: 643d9b77 fmlallbt z23\.s, z27\.b, z29\.b
+ *[0-9a-f]+: 0420bff9 movprfx z25, z31
+ *[0-9a-f]+: 64339ab9 fmlallbt z25\.s, z21\.b, z19\.b
+ *[0-9a-f]+: 6460c000 fmlallbt z0\.s, z0\.b, z0\.b\[0\]
+ *[0-9a-f]+: 6465c777 fmlallbt z23\.s, z27\.b, z5\.b\[1\]
+ *[0-9a-f]+: 0420bff9 movprfx z25, z31
+ *[0-9a-f]+: 646fcab9 fmlallbt z25\.s, z21\.b, z7\.b\[6\]
+ *[0-9a-f]+: 647fceb9 fmlallbt z25\.s, z21\.b, z7\.b\[15\]
+ *[0-9a-f]+: 6420a800 fmlalltb z0\.s, z0\.b, z0\.b
+ *[0-9a-f]+: 643dab77 fmlalltb z23\.s, z27\.b, z29\.b
+ *[0-9a-f]+: 0420bff9 movprfx z25, z31
+ *[0-9a-f]+: 6433aab9 fmlalltb z25\.s, z21\.b, z19\.b
+ *[0-9a-f]+: 64a0c000 fmlalltb z0\.s, z0\.b, z0\.b\[0\]
+ *[0-9a-f]+: 64a5c777 fmlalltb z23\.s, z27\.b, z5\.b\[1\]
+ *[0-9a-f]+: 0420bff9 movprfx z25, z31
+ *[0-9a-f]+: 64afcab9 fmlalltb z25\.s, z21\.b, z7\.b\[6\]
+ *[0-9a-f]+: 64bfceb9 fmlalltb z25\.s, z21\.b, z7\.b\[15\]
+ *[0-9a-f]+: 6420b800 fmlalltt z0\.s, z0\.b, z0\.b
+ *[0-9a-f]+: 643dbb77 fmlalltt z23\.s, z27\.b, z29\.b
+ *[0-9a-f]+: 0420bff9 movprfx z25, z31
+ *[0-9a-f]+: 6433bab9 fmlalltt z25\.s, z21\.b, z19\.b
+ *[0-9a-f]+: 64e0c000 fmlalltt z0\.s, z0\.b, z0\.b\[0\]
+ *[0-9a-f]+: 64e5c777 fmlalltt z23\.s, z27\.b, z5\.b\[1\]
+ *[0-9a-f]+: 0420bff9 movprfx z25, z31
+ *[0-9a-f]+: 64efcab9 fmlalltt z25\.s, z21\.b, z7\.b\[6\]
+ *[0-9a-f]+: 64ffceb9 fmlalltt z25\.s, z21\.b, z7\.b\[15\]
+ *[0-9a-f]+: 64a09800 fmlalt z0\.h, z0\.b, z0\.b
+ *[0-9a-f]+: 64bd9b77 fmlalt z23\.h, z27\.b, z29\.b
+ *[0-9a-f]+: 0420bff9 movprfx z25, z31
+ *[0-9a-f]+: 64b39ab9 fmlalt z25\.h, z21\.b, z19\.b
+ *[0-9a-f]+: 64a05000 fmlalt z0\.h, z0\.b, z0\.b\[0\]
+ *[0-9a-f]+: 64a55777 fmlalt z23\.h, z27\.b, z5\.b\[1\]
+ *[0-9a-f]+: 0420bff9 movprfx z25, z31
+ *[0-9a-f]+: 64af5ab9 fmlalt z25\.h, z21\.b, z7\.b\[6\]
+ *[0-9a-f]+: 64bf5eb9 fmlalt z25\.h, z21\.b, z7\.b\[15\]
diff --git a/gas/testsuite/gas/aarch64/fp8-sve-fma.s b/gas/testsuite/gas/aarch64/fp8-sve-fma.s
new file mode 100644
index 00000000000..368e8da3656
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fp8-sve-fma.s
@@ -0,0 +1,65 @@
+fmlalb z0.h, z0.b, z0.b
+fmlalb z23.h, z27.b, z29.b
+movprfx z25, z31
+fmlalb z25.h, z21.b, z19.b
+
+fmlalb z0.h, z0.b, z0.b[0]
+fmlalb z23.h, z27.b, z5.b[1]
+movprfx z25, z31
+fmlalb z25.h, z21.b, z7.b[6]
+fmlalb z25.h, z21.b, z7.b[15]
+
+fmlallbb z0.s, z0.b, z0.b
+fmlallbb z23.s, z27.b, z29.b
+movprfx z25, z31
+fmlallbb z25.s, z21.b, z19.b
+
+fmlallbb z0.s, z0.b, z0.b[0]
+fmlallbb z23.s, z27.b, z5.b[1]
+movprfx z25, z31
+fmlallbb z25.s, z21.b, z7.b[6]
+fmlallbb z25.s, z21.b, z7.b[15]
+
+fmlallbt z0.s, z0.b, z0.b
+fmlallbt z23.s, z27.b, z29.b
+movprfx z25, z31
+fmlallbt z25.s, z21.b, z19.b
+
+fmlallbt z0.s, z0.b, z0.b[0]
+fmlallbt z23.s, z27.b, z5.b[1]
+movprfx z25, z31
+fmlallbt z25.s, z21.b, z7.b[6]
+fmlallbt z25.s, z21.b, z7.b[15]
+
+fmlalltb z0.s, z0.b, z0.b
+fmlalltb z23.s, z27.b, z29.b
+movprfx z25, z31
+fmlalltb z25.s, z21.b, z19.b
+
+fmlalltb z0.s, z0.b, z0.b[0]
+fmlalltb z23.s, z27.b, z5.b[1]
+movprfx z25, z31
+fmlalltb z25.s, z21.b, z7.b[6]
+fmlalltb z25.s, z21.b, z7.b[15]
+
+fmlalltt z0.s, z0.b, z0.b
+fmlalltt z23.s, z27.b, z29.b
+movprfx z25, z31
+fmlalltt z25.s, z21.b, z19.b
+
+fmlalltt z0.s, z0.b, z0.b[0]
+fmlalltt z23.s, z27.b, z5.b[1]
+movprfx z25, z31
+fmlalltt z25.s, z21.b, z7.b[6]
+fmlalltt z25.s, z21.b, z7.b[15]
+
+fmlalt z0.h, z0.b, z0.b
+fmlalt z23.h, z27.b, z29.b
+movprfx z25, z31
+fmlalt z25.h, z21.b, z19.b
+
+fmlalt z0.h, z0.b, z0.b[0]
+fmlalt z23.h, z27.b, z5.b[1]
+movprfx z25, z31
+fmlalt z25.h, z21.b, z7.b[6]
+fmlalt z25.h, z21.b, z7.b[15]
diff --git a/gas/testsuite/gas/aarch64/fp8-sve-mul-illegal.d b/gas/testsuite/gas/aarch64/fp8-sve-mul-illegal.d
new file mode 100644
index 00000000000..f1d98eec161
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fp8-sve-mul-illegal.d
@@ -0,0 +1,2 @@
+#as: -march=armv8-a+sve2+fp8dot2
+#error_output: fp8-sve-mul-illegal.l
diff --git a/gas/testsuite/gas/aarch64/fp8-sve-mul-illegal.l b/gas/testsuite/gas/aarch64/fp8-sve-mul-illegal.l
new file mode 100644
index 00000000000..4f09c233de0
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fp8-sve-mul-illegal.l
@@ -0,0 +1,21 @@
+[^:]*: Assembler messages:
+[^:]*:1: Error: z0-z7 expected at operand 3 -- `fdot z0\.s,z0\.b,z8\.b\[0\]'
+[^:]*:2: Error: register element index out of range 0 to 3 at operand 3 -- `fdot z0\.s,z0\.b,z0\.b\[4\]'
+[^:]*:4: Error: z0-z7 expected at operand 3 -- `fdot z0\.h,z0\.b,z8\.b\[0\]'
+[^:]*:5: Error: register element index out of range 0 to 7 at operand 3 -- `fdot z0\.h,z0\.b,z0\.b\[8\]'
+[^:]*:7: Error: z0-z7 expected at operand 3 -- `fmlalb z0\.h,z0\.b,z8\.b\[0\]'
+[^:]*:8: Error: register element index out of range 0 to 15 at operand 3 -- `fmlalb z0\.h,z0\.b,z0\.b\[16\]'
+[^:]*:10: Error: z0-z7 expected at operand 3 -- `fmlallbb z0\.s,z0\.b,z8\.b\[0\]'
+[^:]*:11: Error: register element index out of range 0 to 15 at operand 3 -- `fmlallbb z0\.s,z0\.b,z0\.b\[16\]'
+[^:]*:13: Error: z0-z7 expected at operand 3 -- `fmlallbt z0\.s,z0\.b,z8\.b\[0\]'
+[^:]*:14: Error: register element index out of range 0 to 15 at operand 3 -- `fmlallbt z0\.s,z0\.b,z0\.b\[16\]'
+[^:]*:16: Error: z0-z7 expected at operand 3 -- `fmlalltb z0\.s,z0\.b,z8\.b\[0\]'
+[^:]*:17: Error: register element index out of range 0 to 15 at operand 3 -- `fmlalltb z0\.s,z0\.b,z0\.b\[16\]'
+[^:]*:19: Error: z0-z7 expected at operand 3 -- `fmlalltt z0\.s,z0\.b,z8\.b\[0\]'
+[^:]*:20: Error: register element index out of range 0 to 15 at operand 3 -- `fmlalltt z0\.s,z0\.b,z0\.b\[16\]'
+[^:]*:22: Error: z0-z7 expected at operand 3 -- `fmlalt z0\.h,z0\.b,z8\.b\[0\]'
+[^:]*:23: Error: register element index out of range 0 to 15 at operand 3 -- `fmlalt z0\.h,z0\.b,z0\.b\[16\]'
+[^:]*:26: Warning: predicated instruction expected after `movprfx' -- `fdot z25\.s,z0\.b,z0\.b\[0\]'
+[^:]*:29: Warning: predicated instruction expected after `movprfx' -- `fdot z25\.h,z0\.b,z0\.b\[0\]'
+[^:]*:32: Warning: predicated instruction expected after `movprfx' -- `fmlalb z25\.h,z0\.b,z0\.b\[0\]'
+[^:]*:35: Warning: predicated instruction expected after `movprfx' -- `fmlallbb z25\.s,z0\.b,z0\.b\[0\]'
diff --git a/gas/testsuite/gas/aarch64/fp8-sve-mul-illegal.s b/gas/testsuite/gas/aarch64/fp8-sve-mul-illegal.s
new file mode 100644
index 00000000000..c8e3f9dc840
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/fp8-sve-mul-illegal.s
@@ -0,0 +1,35 @@
+fdot z0.s, z0.b, z8.b[0]
+fdot z0.s, z0.b, z0.b[4]
+
+fdot z0.h, z0.b, z8.b[0]
+fdot z0.h, z0.b, z0.b[8]
+
+fmlalb z0.h, z0.b, z8.b[0]
+fmlalb z0.h, z0.b, z0.b[16]
+
+fmlallbb z0.s, z0.b, z8.b[0]
+fmlallbb z0.s, z0.b, z0.b[16]
+
+fmlallbt z0.s, z0.b, z8.b[0]
+fmlallbt z0.s, z0.b, z0.b[16]
+
+fmlalltb z0.s, z0.b, z8.b[0]
+fmlalltb z0.s, z0.b, z0.b[16]
+
+fmlalltt z0.s, z0.b, z8.b[0]
+fmlalltt z0.s, z0.b, z0.b[16]
+
+fmlalt z0.h, z0.b, z8.b[0]
+fmlalt z0.h, z0.b, z0.b[16]
+
+movprfx z25.s, p0/m, z31.s
+fdot z25.s, z0.b, z0.b[0]
+
+movprfx z25.h, p0/z, z31.h
+fdot z25.h, z0.b, z0.b[0]
+
+movprfx z25.h, p0/z, z31.h
+fmlalb z25.h, z0.b, z0.b[0]
+
+movprfx z25.s, p0/m, z31.s
+fmlallbb z25.s, z0.b, z0.b[0]
diff --git a/gas/testsuite/gas/aarch64/illegal-sve2.l b/gas/testsuite/gas/aarch64/illegal-sve2.l
index 20b7a5e1d4d..778c40d87a5 100644
--- a/gas/testsuite/gas/aarch64/illegal-sve2.l
+++ b/gas/testsuite/gas/aarch64/illegal-sve2.l
@@ -419,11 +419,11 @@
[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `fmlalb z0\.s,z0\.h,z0\.h\[8\]'
[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `fmlalb z0\.s,z0\.h,z8\.h\[0\]'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `fmlalb z0\.s,z32\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `fmlalb z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `fmlalb z32\.s,z0\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `fmlalb z0\.h,z0\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: fmlalb z0\.s, z0\.h, z0\.h\[0\]
-[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `fmlalb z32\.s,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `fmlalb z32\.s,z0\.h,z0\.h'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `fmlalb z0\.s,z32\.h,z0\.h'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `fmlalb z0\.s,z0\.h,z32\.h'
[^ :]+:[0-9]+: Error: operand mismatch -- `fmlalb z0\.s,z0\.h,z0\.d'
@@ -432,11 +432,11 @@
[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `fmlalt z0\.s,z0\.h,z0\.h\[8\]'
[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `fmlalt z0\.s,z0\.h,z8\.h\[0\]'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `fmlalt z0\.s,z32\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `fmlalt z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `fmlalt z32\.s,z0\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Error: operand mismatch -- `fmlalt z0\.h,z0\.h,z0\.h\[0\]'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: fmlalt z0\.s, z0\.h, z0\.h\[0\]
-[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `fmlalt z32\.s,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `fmlalt z32\.s,z0\.h,z0\.h'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `fmlalt z0\.s,z32\.h,z0\.h'
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `fmlalt z0\.s,z0\.h,z32\.h'
[^ :]+:[0-9]+: Error: operand mismatch -- `fmlalt z0\.s,z0\.h,z0\.d'
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 39d50675af6..4168082c7f7 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -242,6 +242,27 @@ enum aarch64_feature_bit {
AARCH64_FEATURE_BRBE,
/* SME LUTv2 instructions. */
AARCH64_FEATURE_SME_LUTv2,
+ /* FP8FMA instructions. */
+ AARCH64_FEATURE_FP8FMA,
+ /* FP8DOT4 instructions. */
+ AARCH64_FEATURE_FP8DOT4,
+ /* FP8DOT2 instructions. */
+ AARCH64_FEATURE_FP8DOT2,
+ /* SSVE FP8FMA instructions. */
+ AARCH64_FEATURE_SSVE_FP8FMA,
+ /* SSVE FP8DOT4 instructions. */
+ AARCH64_FEATURE_SSVE_FP8DOT4,
+ /* SSVE FP8DOT2 instructions. */
+ AARCH64_FEATURE_SSVE_FP8DOT2,
+
+ /* Virtual features. These are used to gate instructions that are enabled
+ by either of two (or more) sets of command line flags. */
+ /* +fp8fma+sve or +ssve-fp8fma */
+ AARCH64_FEATURE_FP8FMA_SVE,
+ /* +fp8dot4+sve or +ssve-fp8dot4 */
+ AARCH64_FEATURE_FP8DOT4_SVE,
+ /* +fp8dot2+sve or +ssve-fp8dot2 */
+ AARCH64_FEATURE_FP8DOT2_SVE,
AARCH64_NUM_FEATURES
};
@@ -529,7 +550,9 @@ enum aarch64_opnd
AARCH64_OPND_En, /* AdvSIMD Vector Element Vn. */
AARCH64_OPND_Em, /* AdvSIMD Vector Element Vm. */
AARCH64_OPND_Em16, /* AdvSIMD Vector Element Vm restricted to V0 - V15 when
- qualifier is S_H. */
+ qualifier is S_H or S_2B. */
+ AARCH64_OPND_Em8, /* AdvSIMD Vector Element Vm restricted to V0 - V7,
+ used only with qualifier S_B. */
AARCH64_OPND_Em_INDEX1_14, /* AdvSIMD 1-bit encoded index in Vm at [14] */
AARCH64_OPND_Em_INDEX2_13, /* AdvSIMD 2-bit encoded index in Vm at [14:13] */
AARCH64_OPND_Em_INDEX3_12, /* AdvSIMD 3-bit encoded index in Vm at [14:12] */
@@ -751,6 +774,7 @@ enum aarch64_opnd
AARCH64_OPND_SVE_Zm3_12_INDEX, /* SVE bit index in Zm, bits 12 plus bit [23,22]. */
AARCH64_OPND_SVE_Zm3_19_INDEX, /* z0-z7[0-3] in Zm3_INDEX plus bit 19. */
AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22. */
+ AARCH64_OPND_SVE_Zm3_10_INDEX, /* z0-z7[0-15] in Zm3_INDEX plus bit 11:10. */
AARCH64_OPND_SVE_Zm4_11_INDEX, /* z0-z15[0-3] in Zm plus bit 11. */
AARCH64_OPND_SVE_Zm_imm4, /* SVE vector register with 4bit index. */
AARCH64_OPND_SVE_Zm4_INDEX, /* z0-z15[0-1] in Zm, bits [20,16]. */
@@ -868,11 +892,12 @@ enum aarch64_opnd_qualifier
AARCH64_OPND_QLF_S_S,
AARCH64_OPND_QLF_S_D,
AARCH64_OPND_QLF_S_Q,
- /* These type qualifiers have a special meaning in that they mean 4 x 1 byte
- or 2 x 2 byte are selected by the instruction. Other than that they have
- no difference with AARCH64_OPND_QLF_S_B in encoding. They are here purely
- for syntactical reasons and is an exception from normal AArch64
- disassembly scheme. */
+ /* These type qualifiers have a special meaning in that they mean 2 x 1 byte,
+ 4 x 1 byte or 2 x 2 byte are selected by the instruction. Other than that
+ they have no difference with AARCH64_OPND_QLF_S_B in encoding. They are
+ here purely for syntactical reasons and is an exception from normal
+ AArch64 disassembly scheme. */
+ AARCH64_OPND_QLF_S_2B,
AARCH64_OPND_QLF_S_4B,
AARCH64_OPND_QLF_S_2H,
diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
index 8bd9816e96c..94e8218feda 100644
--- a/opcodes/aarch64-asm-2.c
+++ b/opcodes/aarch64-asm-2.c
@@ -651,10 +651,9 @@ aarch64_insert_operand (const aarch64_operand *self,
case 32:
case 33:
case 34:
- case 122:
case 123:
case 124:
- case 182:
+ case 125:
case 183:
case 184:
case 185:
@@ -668,30 +667,31 @@ aarch64_insert_operand (const aarch64_operand *self,
case 193:
case 194:
case 195:
- case 210:
+ case 196:
case 211:
case 212:
case 213:
- case 222:
+ case 214:
case 223:
case 224:
case 225:
case 226:
- case 237:
- case 241:
- case 246:
- case 254:
- case 255:
- case 262:
- case 263:
+ case 227:
+ case 239:
+ case 243:
+ case 248:
+ case 256:
+ case 257:
case 264:
case 265:
+ case 266:
+ case 267:
return aarch64_ins_regno (self, info, code, inst, errors);
case 6:
- case 118:
case 119:
- case 297:
- case 300:
+ case 120:
+ case 299:
+ case 302:
return aarch64_ins_none (self, info, code, inst, errors);
case 17:
return aarch64_ins_reg_extended (self, info, code, inst, errors);
@@ -705,18 +705,17 @@ aarch64_insert_operand (const aarch64_operand *self,
case 36:
case 37:
case 38:
- case 302:
- return aarch64_ins_reglane (self, info, code, inst, errors);
case 39:
+ case 304:
+ return aarch64_ins_reglane (self, info, code, inst, errors);
case 40:
case 41:
- case 227:
+ case 42:
case 228:
- case 231:
- case 266:
- case 267:
- case 282:
- case 283:
+ case 229:
+ case 232:
+ case 268:
+ case 269:
case 284:
case 285:
case 286:
@@ -728,22 +727,23 @@ aarch64_insert_operand (const aarch64_operand *self,
case 292:
case 293:
case 294:
+ case 295:
+ case 296:
return aarch64_ins_simple_index (self, info, code, inst, errors);
- case 42:
- return aarch64_ins_reglist (self, info, code, inst, errors);
case 43:
- return aarch64_ins_ldst_reglist (self, info, code, inst, errors);
+ return aarch64_ins_reglist (self, info, code, inst, errors);
case 44:
- return aarch64_ins_ldst_reglist_r (self, info, code, inst, errors);
+ return aarch64_ins_ldst_reglist (self, info, code, inst, errors);
case 45:
- return aarch64_ins_lut_reglist (self, info, code, inst, errors);
+ return aarch64_ins_ldst_reglist_r (self, info, code, inst, errors);
case 46:
- return aarch64_ins_ldst_elemlist (self, info, code, inst, errors);
+ return aarch64_ins_lut_reglist (self, info, code, inst, errors);
case 47:
+ return aarch64_ins_ldst_elemlist (self, info, code, inst, errors);
case 48:
case 49:
case 50:
- case 60:
+ case 51:
case 61:
case 62:
case 63:
@@ -760,15 +760,15 @@ aarch64_insert_operand (const aarch64_operand *self,
case 74:
case 75:
case 76:
- case 88:
+ case 77:
case 89:
case 90:
case 91:
- case 117:
- case 121:
- case 179:
- case 181:
- case 202:
+ case 92:
+ case 118:
+ case 122:
+ case 180:
+ case 182:
case 203:
case 204:
case 205:
@@ -776,103 +776,103 @@ aarch64_insert_operand (const aarch64_operand *self,
case 207:
case 208:
case 209:
- case 268:
- case 295:
- case 296:
+ case 210:
+ case 270:
+ case 297:
case 298:
- case 299:
+ case 300:
case 301:
- case 306:
- case 307:
+ case 303:
+ case 308:
+ case 309:
return aarch64_ins_imm (self, info, code, inst, errors);
- case 51:
case 52:
- return aarch64_ins_advsimd_imm_shift (self, info, code, inst, errors);
case 53:
+ return aarch64_ins_advsimd_imm_shift (self, info, code, inst, errors);
case 54:
case 55:
+ case 56:
return aarch64_ins_advsimd_imm_modified (self, info, code, inst, errors);
- case 59:
- case 169:
+ case 60:
+ case 170:
return aarch64_ins_fpimm (self, info, code, inst, errors);
- case 77:
- case 177:
- return aarch64_ins_limm (self, info, code, inst, errors);
case 78:
- return aarch64_ins_aimm (self, info, code, inst, errors);
+ case 178:
+ return aarch64_ins_limm (self, info, code, inst, errors);
case 79:
- return aarch64_ins_imm_half (self, info, code, inst, errors);
+ return aarch64_ins_aimm (self, info, code, inst, errors);
case 80:
+ return aarch64_ins_imm_half (self, info, code, inst, errors);
+ case 81:
return aarch64_ins_fbits (self, info, code, inst, errors);
- case 82:
case 83:
- case 174:
- return aarch64_ins_imm_rotate2 (self, info, code, inst, errors);
case 84:
- case 173:
case 175:
- return aarch64_ins_imm_rotate1 (self, info, code, inst, errors);
+ return aarch64_ins_imm_rotate2 (self, info, code, inst, errors);
case 85:
+ case 174:
+ case 176:
+ return aarch64_ins_imm_rotate1 (self, info, code, inst, errors);
case 86:
+ case 87:
return aarch64_ins_cond (self, info, code, inst, errors);
- case 92:
- case 101:
- return aarch64_ins_addr_simple (self, info, code, inst, errors);
case 93:
- return aarch64_ins_addr_regoff (self, info, code, inst, errors);
+ case 102:
+ return aarch64_ins_addr_simple (self, info, code, inst, errors);
case 94:
+ return aarch64_ins_addr_regoff (self, info, code, inst, errors);
case 95:
case 96:
- case 98:
- case 100:
- return aarch64_ins_addr_simm (self, info, code, inst, errors);
case 97:
- return aarch64_ins_addr_simm10 (self, info, code, inst, errors);
case 99:
+ case 101:
+ return aarch64_ins_addr_simm (self, info, code, inst, errors);
+ case 98:
+ return aarch64_ins_addr_simm10 (self, info, code, inst, errors);
+ case 100:
return aarch64_ins_addr_uimm12 (self, info, code, inst, errors);
- case 102:
- return aarch64_ins_addr_offset (self, info, code, inst, errors);
case 103:
- return aarch64_ins_simd_addr_post (self, info, code, inst, errors);
+ return aarch64_ins_addr_offset (self, info, code, inst, errors);
case 104:
+ return aarch64_ins_simd_addr_post (self, info, code, inst, errors);
case 105:
- return aarch64_ins_sysreg (self, info, code, inst, errors);
case 106:
- return aarch64_ins_pstatefield (self, info, code, inst, errors);
+ return aarch64_ins_sysreg (self, info, code, inst, errors);
case 107:
+ return aarch64_ins_pstatefield (self, info, code, inst, errors);
case 108:
case 109:
case 110:
case 111:
case 112:
- return aarch64_ins_sysins_op (self, info, code, inst, errors);
case 113:
- case 115:
- return aarch64_ins_barrier (self, info, code, inst, errors);
+ return aarch64_ins_sysins_op (self, info, code, inst, errors);
case 114:
- return aarch64_ins_barrier_dsb_nxs (self, info, code, inst, errors);
case 116:
+ return aarch64_ins_barrier (self, info, code, inst, errors);
+ case 115:
+ return aarch64_ins_barrier_dsb_nxs (self, info, code, inst, errors);
+ case 117:
return aarch64_ins_prfop (self, info, code, inst, errors);
- case 120:
+ case 121:
return aarch64_ins_hint (self, info, code, inst, errors);
- case 125:
case 126:
- return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors);
case 127:
+ return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors);
case 128:
case 129:
case 130:
- return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors);
case 131:
- return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors);
+ return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors);
case 132:
- return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors);
+ return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors);
case 133:
+ return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors);
case 134:
case 135:
case 136:
- return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors);
case 137:
+ return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors);
case 138:
case 139:
case 140:
@@ -887,8 +887,8 @@ aarch64_insert_operand (const aarch64_operand *self,
case 149:
case 150:
case 151:
- return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors);
case 152:
+ return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors);
case 153:
case 154:
case 155:
@@ -896,118 +896,120 @@ aarch64_insert_operand (const aarch64_operand *self,
case 157:
case 158:
case 159:
- return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors);
case 160:
+ return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors);
case 161:
case 162:
case 163:
- return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors);
case 164:
- return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors);
+ return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors);
case 165:
- return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors);
+ return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors);
case 166:
- return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors);
+ return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors);
case 167:
- return aarch64_ins_sve_aimm (self, info, code, inst, errors);
+ return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors);
case 168:
+ return aarch64_ins_sve_aimm (self, info, code, inst, errors);
+ case 169:
return aarch64_ins_sve_asimm (self, info, code, inst, errors);
- case 170:
- return aarch64_ins_sve_float_half_one (self, info, code, inst, errors);
case 171:
- return aarch64_ins_sve_float_half_two (self, info, code, inst, errors);
+ return aarch64_ins_sve_float_half_one (self, info, code, inst, errors);
case 172:
+ return aarch64_ins_sve_float_half_two (self, info, code, inst, errors);
+ case 173:
return aarch64_ins_sve_float_zero_one (self, info, code, inst, errors);
- case 176:
+ case 177:
return aarch64_ins_inv_limm (self, info, code, inst, errors);
- case 178:
+ case 179:
return aarch64_ins_sve_limm_mov (self, info, code, inst, errors);
- case 180:
+ case 181:
return aarch64_ins_sve_scale (self, info, code, inst, errors);
- case 196:
case 197:
case 198:
- return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
case 199:
+ return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
case 200:
case 201:
- case 281:
+ case 202:
+ case 283:
return aarch64_ins_sve_shrimm (self, info, code, inst, errors);
- case 214:
case 215:
case 216:
case 217:
- return aarch64_ins_sme_za_vrs1 (self, info, code, inst, errors);
case 218:
+ return aarch64_ins_sme_za_vrs1 (self, info, code, inst, errors);
case 219:
case 220:
case 221:
+ case 222:
return aarch64_ins_sme_za_vrs2 (self, info, code, inst, errors);
- case 229:
case 230:
- case 232:
+ case 231:
case 233:
case 234:
case 235:
case 236:
- return aarch64_ins_sve_quad_index (self, info, code, inst, errors);
+ case 237:
case 238:
+ return aarch64_ins_sve_quad_index (self, info, code, inst, errors);
+ case 240:
return aarch64_ins_sve_index_imm (self, info, code, inst, errors);
- case 239:
+ case 241:
return aarch64_ins_sve_index (self, info, code, inst, errors);
- case 240:
case 242:
- case 261:
- case 308:
- case 309:
+ case 244:
+ case 263:
case 310:
+ case 311:
+ case 312:
return aarch64_ins_sve_reglist (self, info, code, inst, errors);
- case 243:
- case 244:
- case 247:
- case 248:
+ case 245:
+ case 246:
case 249:
case 250:
case 251:
- case 260:
- return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors);
- case 245:
case 252:
case 253:
+ case 262:
+ return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors);
+ case 247:
+ case 254:
+ case 255:
return aarch64_ins_sve_strided_reglist (self, info, code, inst, errors);
- case 256:
case 258:
- case 269:
+ case 260:
+ case 271:
return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors);
- case 257:
case 259:
+ case 261:
return aarch64_ins_sme_za_hv_tiles_range (self, info, code, inst, errors);
- case 270:
- case 271:
case 272:
case 273:
case 274:
case 275:
case 276:
- return aarch64_ins_sme_za_array (self, info, code, inst, errors);
case 277:
- return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors);
case 278:
- return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
+ return aarch64_ins_sme_za_array (self, info, code, inst, errors);
case 279:
- return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
+ return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors);
case 280:
+ return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
+ case 281:
+ return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
+ case 282:
return aarch64_ins_plain_shrimm (self, info, code, inst, errors);
- case 303:
- case 304:
case 305:
+ case 306:
+ case 307:
return aarch64_ins_x0_to_x30 (self, info, code, inst, errors);
- case 311:
- case 312:
case 313:
case 314:
- return aarch64_ins_rcpc3_addr_opt_offset (self, info, code, inst, errors);
case 315:
+ case 316:
+ return aarch64_ins_rcpc3_addr_opt_offset (self, info, code, inst, errors);
+ case 317:
return aarch64_ins_rcpc3_addr_offset (self, info, code, inst, errors);
default: assert (0); abort ();
}
diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
index 57fb8614dd0..e738bb43125 100644
--- a/opcodes/aarch64-asm.c
+++ b/opcodes/aarch64-asm.c
@@ -153,10 +153,15 @@ aarch64_ins_reglane (const aarch64_operand *self, const aarch64_opnd_info *info,
{
case AARCH64_OPND_QLF_S_4B:
case AARCH64_OPND_QLF_S_2H:
- /* L:H */
+ /* H:L */
assert (reglane_index < 4);
insert_fields (code, reglane_index, 0, 2, FLD_L, FLD_H);
break;
+ case AARCH64_OPND_QLF_S_2B:
+ /* H:L:M */
+ assert (reglane_index < 8);
+ insert_fields (code, reglane_index, 0, 3, FLD_M, FLD_L, FLD_H);
+ break;
default:
return false;
}
@@ -180,6 +185,11 @@ aarch64_ins_reglane (const aarch64_operand *self, const aarch64_opnd_info *info,
switch (info->qualifier)
{
+ case AARCH64_OPND_QLF_S_B:
+ /* H:imm3 */
+ assert (reglane_index < 16);
+ insert_fields (code, reglane_index, 0, 2, FLD_imm3_19, FLD_H);
+ break;
case AARCH64_OPND_QLF_S_H:
/* H:L:M */
assert (reglane_index < 8);
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index fd19b2d3e78..d3274222e4c 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -17285,11 +17285,33 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 31) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 011001x0001xxxxx010xxxxxxxxxxxxx
- fdot. */
- return 2473;
+ if (((word >> 12) & 0x1) == 0)
+ {
+ if (((word >> 10) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x0001xxxxx0100x0xxxxxxxxxx
+ fdot. */
+ return 2473;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x0001xxxxx0100x1xxxxxxxxxx
+ fdot. */
+ return 3416;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x0001xxxxx0101xxxxxxxxxxxx
+ fmlalb. */
+ return 3418;
+ }
}
else
{
@@ -17304,21 +17326,32 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 31) & 0x1) == 0)
{
- if (((word >> 10) & 0x1) == 0)
+ if (((word >> 12) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 011001x0101xxxxx010xx0xxxxxxxxxx
- fmlalb. */
- return 2146;
+ if (((word >> 10) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x0101xxxxx0100x0xxxxxxxxxx
+ fmlalb. */
+ return 2146;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x0101xxxxx0100x1xxxxxxxxxx
+ fmlalt. */
+ return 2148;
+ }
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- 011001x0101xxxxx010xx1xxxxxxxxxx
+ 011001x0101xxxxx0101xxxxxxxxxxxx
fmlalt. */
- return 2148;
+ return 3428;
}
}
else
@@ -17337,11 +17370,22 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 31) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 011001x0011xxxxx010xxxxxxxxxxxxx
- bfdot. */
- return 3066;
+ if (((word >> 10) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x0011xxxxx010xx0xxxxxxxxxx
+ bfdot. */
+ return 3066;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x0011xxxxx010xx1xxxxxxxxxx
+ fdot. */
+ return 3414;
+ }
}
else
{
@@ -17391,31 +17435,108 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 23) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x11001x0001xxxxx1x0xxxxxxxxxxxxx
- fdot. */
- return 2474;
+ if (((word >> 12) & 0x1) == 0)
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ if (((word >> 10) & 0x1) == 0)
+ {
+ if (((word >> 11) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x11001x0001xxxxx100000xxxxxxxxxx
+ fdot. */
+ return 2474;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x11001x0001xxxxx100010xxxxxxxxxx
+ fmlallbb. */
+ return 3419;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x11001x0001xxxxx1000x1xxxxxxxxxx
+ fdot. */
+ return 3415;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x11001x0001xxxxx1100xxxxxxxxxxxx
+ fmlallbb. */
+ return 3420;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x11001x0001xxxxx1x01xxxxxxxxxxxx
+ fmlallbt. */
+ return 3421;
+ }
}
else
{
if (((word >> 31) & 0x1) == 0)
{
- if (((word >> 10) & 0x1) == 0)
+ if (((word >> 12) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 011001x0101xxxxx1x0xx0xxxxxxxxxx
- fmlalb. */
- return 2147;
+ if (((word >> 14) & 0x1) == 0)
+ {
+ if (((word >> 10) & 0x1) == 0)
+ {
+ if (((word >> 11) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x0101xxxxx100000xxxxxxxxxx
+ fmlalb. */
+ return 2147;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x0101xxxxx100010xxxxxxxxxx
+ fmlalb. */
+ return 3417;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x0101xxxxx1000x1xxxxxxxxxx
+ fmlalt. */
+ return 2149;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x0101xxxxx1100xxxxxxxxxxxx
+ fmlalltb. */
+ return 3424;
+ }
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- 011001x0101xxxxx1x0xx1xxxxxxxxxx
+ 011001x0101xxxxx1x01xxxxxxxxxxxx
fmlalt. */
- return 2149;
+ return 3427;
}
}
else
@@ -17432,31 +17553,64 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 23) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x11001x0011xxxxx1x0xxxxxxxxxxxxx
- bfdot. */
- return 3065;
+ if (((word >> 14) & 0x1) == 0)
+ {
+ if (((word >> 10) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x11001x0011xxxxx100xx0xxxxxxxxxx
+ bfdot. */
+ return 3065;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x11001x0011xxxxx100xx1xxxxxxxxxx
+ fdot. */
+ return 3413;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x11001x0011xxxxx110xxxxxxxxxxxxx
+ fmlallbt. */
+ return 3422;
+ }
}
else
{
if (((word >> 31) & 0x1) == 0)
{
- if (((word >> 10) & 0x1) == 0)
+ if (((word >> 14) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 011001x0111xxxxx1x0xx0xxxxxxxxxx
- bfmlalb. */
- return 3071;
+ if (((word >> 10) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x0111xxxxx100xx0xxxxxxxxxx
+ bfmlalb. */
+ return 3071;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x0111xxxxx100xx1xxxxxxxxxx
+ bfmlalt. */
+ return 3070;
+ }
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- 011001x0111xxxxx1x0xx1xxxxxxxxxx
- bfmlalt. */
- return 3070;
+ 011001x0111xxxxx110xxxxxxxxxxxxx
+ fmlalltt. */
+ return 3426;
}
}
else
@@ -17762,32 +17916,54 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 22) & 0x1) == 0)
{
- if (((word >> 31) & 0x1) == 0)
+ if (((word >> 23) & 0x1) == 0)
{
- if (((word >> 10) & 0x1) == 0)
+ if (((word >> 12) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- 011001x0x01xxxxx101xx0xxxxxxxxxx
- fmlslb. */
- return 2151;
+ x11001x0001xxxxx1010xxxxxxxxxxxx
+ fmlalltb. */
+ return 3423;
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- 011001x0x01xxxxx101xx1xxxxxxxxxx
- fmlslt. */
- return 2153;
+ x11001x0001xxxxx1011xxxxxxxxxxxx
+ fmlalltt. */
+ return 3425;
}
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 111001x0x01xxxxx101xxxxxxxxxxxxx
- st1h. */
- return 1954;
+ if (((word >> 31) & 0x1) == 0)
+ {
+ if (((word >> 10) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x0101xxxxx101xx0xxxxxxxxxx
+ fmlslb. */
+ return 2151;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x0101xxxxx101xx1xxxxxxxxxx
+ fmlslt. */
+ return 2153;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 111001x0101xxxxx101xxxxxxxxxxxxx
+ st1h. */
+ return 1954;
+ }
}
}
else
@@ -25976,31 +26152,75 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 13) & 0x1) == 0)
{
- if (((word >> 22) & 0x1) == 0)
+ if (((word >> 14) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 0x001110x00xxxxxxx0001xxxxxxxxxx
- dup. */
- return 149;
+ if (((word >> 22) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 0x001110x00xxxxxx00001xxxxxxxxxx
+ dup. */
+ return 149;
+ }
+ else
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 0x001110010xxxxxx00001xxxxxxxxxx
+ fmaxnm. */
+ return 292;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 0x001110110xxxxxx00001xxxxxxxxxx
+ fminnm. */
+ return 308;
+ }
+ }
}
else
{
- if (((word >> 23) & 0x1) == 0)
+ if (((word >> 22) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 0x001110010xxxxxxx0001xxxxxxxxxx
- fmaxnm. */
- return 292;
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 00001110x00xxxxxx10001xxxxxxxxxx
+ fmlallbb. */
+ return 3405;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 01001110x00xxxxxx10001xxxxxxxxxx
+ fmlalltb. */
+ return 3407;
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 0x001110110xxxxxxx0001xxxxxxxxxx
- fminnm. */
- return 308;
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 00001110x10xxxxxx10001xxxxxxxxxx
+ fmlallbt. */
+ return 3406;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 01001110x10xxxxxx10001xxxxxxxxxx
+ fmlalltt. */
+ return 3408;
+ }
}
}
}
@@ -26209,37 +26429,81 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- if (((word >> 22) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 0x001110x00xxxxxxx1111xxxxxxxxxx
- umov. */
- return 152;
- }
- else
+ if (((word >> 14) & 0x1) == 0)
{
- if (((word >> 23) & 0x1) == 0)
+ if (((word >> 22) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- 0x001110010xxxxxxx1111xxxxxxxxxx
- frecps. */
- return 304;
+ 0x001110x00xxxxxx01111xxxxxxxxxx
+ umov. */
+ return 152;
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 0x001110110xxxxxxx1111xxxxxxxxxx
- frsqrts. */
- return 316;
- }
- }
- }
- }
- }
- }
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 0x001110010xxxxxx01111xxxxxxxxxx
+ frecps. */
+ return 304;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 0x001110110xxxxxx01111xxxxxxxxxx
+ frsqrts. */
+ return 316;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 22) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 0x001110x00xxxxxx11111xxxxxxxxxx
+ fdot. */
+ return 3397;
+ }
+ else
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 0x001110010xxxxxx11111xxxxxxxxxx
+ fdot. */
+ return 3399;
+ }
+ else
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 00001110110xxxxxx11111xxxxxxxxxx
+ fmlalb. */
+ return 3401;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 01001110110xxxxxx11111xxxxxxxxxx
+ fmlalt. */
+ return 3402;
+ }
+ }
+ }
+ }
+ }
+ }
+ }
+ }
}
else
{
@@ -31672,21 +31936,65 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 29) & 0x1) == 0)
{
- if (((word >> 30) & 0x1) == 0)
+ if (((word >> 22) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x0001111xxxxxxxx0000x0xxxxxxxxxx
- fmlal. */
- return 3013;
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx00111100xxxxxx0000x0xxxxxxxxxx
+ fdot. */
+ return 3398;
+ }
+ else
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x000111110xxxxxx0000x0xxxxxxxxxx
+ fmlal. */
+ return 3013;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x100111110xxxxxx0000x0xxxxxxxxxx
+ fmlal. */
+ return 3017;
+ }
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1001111xxxxxxxx0000x0xxxxxxxxxx
- fmlal. */
- return 3017;
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx00111101xxxxxx0000x0xxxxxxxxxx
+ fdot. */
+ return 3400;
+ }
+ else
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x000111111xxxxxx0000x0xxxxxxxxxx
+ fmlalb. */
+ return 3403;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x100111111xxxxxx0000x0xxxxxxxxxx
+ fmlalt. */
+ return 3404;
+ }
+ }
}
}
else
@@ -32216,21 +32524,65 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- if (((word >> 30) & 0x1) == 0)
+ if (((word >> 22) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x0101111xxxxxxxx1000x0xxxxxxxxxx
- fmlal2. */
- return 3015;
+ [...]
[diff truncated at 100000 bytes]
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