https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=7bdb051fd62ca70aa2cf549441b7728d20a3a631
commit 7bdb051fd62ca70aa2cf549441b7728d20a3a631
Author: Srinath Parvathaneni <srinath.parvathaneni@arm.com>
Date: Mon Jul 8 16:36:44 2024 +0100
aarch64: Add support for sme2.1 zero instructions.
This patch adds support for following sme2.1 zero instructions and
the spec is available here [1].
1. ZERO (single-vector).
2. ZERO (double-vector).
3. ZERO (quad-vector).
The VECTOR GROUP symbols VGx2 and VGx4 are optional for the assembler
for most of the sme and sve instructions. But for few of the sme2.1
zero instruction variants VECTOR GROUP symbols VGx2 and VGx4 are mandatory.
To address this a bit "F_VG_REQ" is introduced in this patch, on setting
F_VG_REQ bit in flags of aarch64_opcode forces the assembler to accept
instruction operand only having VECTOR GROUP symbols.
[1]: https://developer.arm.com/documentation/ddi0602/2024-03/SME-Instructions?lang=en
Diff:
---
gas/testsuite/gas/aarch64/sme-4-illegal.l | 2 +-
gas/testsuite/gas/aarch64/sme2p1-5-bad.d | 4 +
gas/testsuite/gas/aarch64/sme2p1-5-bad.l | 103 +++++++
gas/testsuite/gas/aarch64/sme2p1-5-bad.s | 54 ++++
gas/testsuite/gas/aarch64/sme2p1-5.d | 54 ++++
gas/testsuite/gas/aarch64/sme2p1-5.s | 54 ++++
include/opcode/aarch64.h | 11 +-
opcodes/aarch64-dis-2.c | 460 ++++++++++++++++++------------
opcodes/aarch64-opc.c | 60 ++--
opcodes/aarch64-tbl.h | 18 ++
10 files changed, 610 insertions(+), 210 deletions(-)
diff --git a/gas/testsuite/gas/aarch64/sme-4-illegal.l b/gas/testsuite/gas/aarch64/sme-4-illegal.l
index a9e98524067..db52529e3e1 100644
--- a/gas/testsuite/gas/aarch64/sme-4-illegal.l
+++ b/gas/testsuite/gas/aarch64/sme-4-illegal.l
@@ -1,5 +1,5 @@
[^:]*: Assembler messages:
-[^:]*:[0-9]+: Error: expected '{' at operand 1 -- `zero za'
+[^:]*:[0-9]+: Error: expected '\[' at operand 1 -- `zero za'
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `zero {za8\.d}'
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `zero {za0\.d,za8.d}'
[^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `zero {za2\.h}'
diff --git a/gas/testsuite/gas/aarch64/sme2p1-5-bad.d b/gas/testsuite/gas/aarch64/sme2p1-5-bad.d
new file mode 100644
index 00000000000..86a6834546e
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2p1-5-bad.d
@@ -0,0 +1,4 @@
+#name: Negative test of SME2.1 ZERO instructions.
+#as: -march=armv9.4-a+sme2p1
+#source: sme2p1-5-bad.s
+#error_output: sme2p1-5-bad.l
diff --git a/gas/testsuite/gas/aarch64/sme2p1-5-bad.l b/gas/testsuite/gas/aarch64/sme2p1-5-bad.l
new file mode 100644
index 00000000000..959864a9809
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2p1-5-bad.l
@@ -0,0 +1,103 @@
+.*: Assembler messages:
+.*: Error: operand mismatch -- `zero za.s\[w8,0,vgx2\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w8, 0, vgx2\]
+.*: Error: operand mismatch -- `zero za.b\[w14,0,vgx2\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w14, 0, vgx2\]
+.*: Error: expected a selection register in the range w8-w11 at operand 1 -- `zero za.d\[w2,7,vgx2\]'
+.*: Error: immediate offset out of range 0 to 7 at operand 1 -- `zero za.d\[w11,17,vgx2\]'
+.*: Error: invalid vector group size at operand 1 -- `zero za.d\[w9,4,vgx3\]'
+.*: Error: operand mismatch -- `zero za.h\[w10,3\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w10, 3\]
+.*: Error: operand mismatch -- `zero za.s\[w18,0,vgx4\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w18, 0, vgx4\]
+.*: Error: operand mismatch -- `zero za.b\[w1,0,vgx4\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w1, 0, vgx4\]
+.*: Error: operand mismatch -- `zero za.q\[w8,17,vgx2\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w8, 17, vgx2\]
+.*: Error: invalid vector group size at operand 1 -- `zero za.h\[w11,7,vgx3\]'
+.*: Error: expected a constant immediate offset at operand 1 -- `zero za.s\[w9,vg\]'
+.*: Error: operand mismatch -- `zero za.b\[w10,3\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w10, 3\]
+.*: Error: operand mismatch -- `zero za.s\[w18,0:1\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w18, 0:1\]
+.*: Error: operand mismatch -- `zero za.s\[w1,0:1\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w1, 0:1\]
+.*: Error: operand mismatch -- `zero za.b\[w8,4:5\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w8, 4:5\]
+.*: Error: operand mismatch -- `zero za.b\[w11,1:5\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w11, 1:5\]
+.*: Error: operand mismatch -- `zero za.h\[w9,2:13\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w9, 2:13\]
+.*: Error: the last offset is less than the first offset at operand 1 -- `zero za.h\[w10,16:7\]'
+.*: Error: operand mismatch -- `zero za.s\[w18,0:3,vgx2\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w18, 0:3, vgx2\]
+.*: Error: operand mismatch -- `zero za.b\[w1,0:1,vgx4\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w1, 0:1, vgx4\]
+.*: Error: invalid vector group size at operand 1 -- `zero za.h\[w8,6:7,vg\]'
+.*: Error: invalid vector group size at operand 1 -- `zero za.q\[w9,12:13,vgx3\]'
+.*: Error: operand mismatch -- `zero za.s\[w18,0:1,vgx4\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w18, 0:1, vgx4\]
+.*: Error: invalid vector group size at operand 1 -- `zero za.h\[w1,0:1,vgx3\]'
+.*: Error: operand mismatch -- `zero za.b\[w8,16:17,vgx4\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w8, 16:17, vgx4\]
+.*: Error: operand mismatch -- `zero za.q\[w9,12:13\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w9, 12:13\]
+.*: Error: invalid vector group size at operand 1 -- `zero za.s\[w18,0:3,\]'
+.*: Error: operand mismatch -- `zero za.s\[w1,0:3\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w1, 0:3\]
+.*: Error: operand mismatch -- `zero za.b\[w8,8:11\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w8, 8:11\]
+.*: Error: the last offset is less than the first offset at operand 1 -- `zero za.b\[w11,18:1,vgx3\]'
+.*: Error: operand mismatch -- `zero za.h\[w9,4\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w9, 4\]
+.*: Error: operand mismatch -- `zero za.h\[w10,10:13\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w10, 10:13\]
+.*: Error: operand mismatch -- `zero za.s\[w18,0:3,vgx2\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w18, 0:3, vgx2\]
+.*: Error: operand mismatch -- `zero za.s\[w1,0:3,vgx2\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w1, 0:3, vgx2\]
+.*: Error: operand mismatch -- `zero za.b\[w8,14:17,vgx2\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w8, 14:17, vgx2\]
+.*: Error: invalid vector group size at operand 1 -- `zero za.b\[w11,4:7,vg\]'
+.*: Error: operand mismatch -- `zero za.h\[w9,0:3\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w9, 0:3\]
+.*: Error: expected a constant immediate offset at operand 1 -- `zero za.q\[w10,vgx2\]'
+.*: Error: operand mismatch -- `zero za.s\[w18,0:3,vgx4\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w18, 0:3, vgx4\]
+.*: Error: operand mismatch -- `zero za.s\[w1,0:3,vgx4\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w1, 0:3, vgx4\]
+.*: Error: operand mismatch -- `zero za.b\[w8,14:17,vgx4\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w8, 14:17, vgx4\]
+.*: Error: invalid vector group size at operand 1 -- `zero za.b\[w11,4:7,vg\]'
+.*: Error: invalid vector group size at operand 1 -- `zero za.h\[w9,0:3,vgx3\]'
+.*: Error: operand mismatch -- `zero za.q\[w10,4\]'
+.*: Info: did you mean this\?
+.*: Info: zero za.d\[w10, 4\]
diff --git a/gas/testsuite/gas/aarch64/sme2p1-5-bad.s b/gas/testsuite/gas/aarch64/sme2p1-5-bad.s
new file mode 100644
index 00000000000..5b69634e5b2
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2p1-5-bad.s
@@ -0,0 +1,54 @@
+/* ZERO (single-vector). */
+zero za.s[w8, 0, vgx2]
+zero za.b[w14, 0, vgx2]
+zero za.d[w2, 7, vgx2]
+zero za.d[w11, 17, vgx2]
+zero za.d[w9, 4, vgx3]
+zero za.h[w10, 3]
+
+zero za.s[w18, 0, vgx4]
+zero za.b[w1, 0, vgx4]
+zero za.q[w8, 17, vgx2]
+zero za.h[w11, 7, vgx3]
+zero za.s[w9, vg]
+zero za.b[w10, 3]
+
+/* ZERO (double-vector). */
+zero za.s[w18, 0:1]
+zero za.s[w1, 0:1]
+zero za.b[w8, 4:5]
+zero za.b[w11, 1:5]
+zero za.h[w9, 2:13]
+zero za.h[w10, 16:7]
+
+zero za.s[w18, 0:3, vgx2]
+zero za.b[w1, 0:1, vgx4]
+zero za.h[w8, 6:7, vg]
+zero za.q[w9, 12:13, vgx3]
+
+zero za.s[w18, 0:1, vgx4]
+zero za.h[w1, 0:1, vgx3]
+zero za.b[w8, 16:17, vgx4]
+zero za.q[w9, 12:13]
+
+/* ZERO (quad-vector). */
+zero za.s[w18, 0:3,]
+zero za.s[w1, 0:3]
+zero za.b[w8, 8:11]
+zero za.b[w11, 18:1, vgx3]
+zero za.h[w9, 4]
+zero za.h[w10, 10:13]
+
+zero za.s[w18, 0:3, vgx2]
+zero za.s[w1, 0:3, vgx2]
+zero za.b[w8, 14:17, vgx2]
+zero za.b[w11, 4:7, vg]
+zero za.h[w9, 0:3]
+zero za.q[w10, vgx2]
+
+zero za.s[w18, 0:3, vgx4]
+zero za.s[w1, 0:3, vgx4]
+zero za.b[w8, 14:17, vgx4]
+zero za.b[w11, 4:7, vg]
+zero za.h[w9, 0:3, vgx3]
+zero za.q[w10, 4]
diff --git a/gas/testsuite/gas/aarch64/sme2p1-5.d b/gas/testsuite/gas/aarch64/sme2p1-5.d
new file mode 100644
index 00000000000..f63a171d461
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2p1-5.d
@@ -0,0 +1,54 @@
+#name: Test of SME2.1 ZERO instructions.
+#as: -march=armv9.4-a+sme2p1
+#objdump: -dr
+
+[^:]+: file format .*
+
+
+[^:]+:
+
+[^:]+:
+.*: c00c0000 zero za.d\[w8, 0, vgx2\]
+.*: c00c6000 zero za.d\[w11, 0, vgx2\]
+.*: c00c0007 zero za.d\[w8, 7, vgx2\]
+.*: c00c6007 zero za.d\[w11, 7, vgx2\]
+.*: c00c2004 zero za.d\[w9, 4, vgx2\]
+.*: c00c4003 zero za.d\[w10, 3, vgx2\]
+.*: c00e0000 zero za.d\[w8, 0, vgx4\]
+.*: c00e6000 zero za.d\[w11, 0, vgx4\]
+.*: c00e0007 zero za.d\[w8, 7, vgx4\]
+.*: c00e6007 zero za.d\[w11, 7, vgx4\]
+.*: c00e2004 zero za.d\[w9, 4, vgx4\]
+.*: c00e4003 zero za.d\[w10, 3, vgx4\]
+.*: c00c8000 zero za.d\[w8, 0:1\]
+.*: c00ce000 zero za.d\[w11, 0:1\]
+.*: c00c8007 zero za.d\[w8, 14:15\]
+.*: c00ce007 zero za.d\[w11, 14:15\]
+.*: c00ca001 zero za.d\[w9, 2:3\]
+.*: c00cc003 zero za.d\[w10, 6:7\]
+.*: c00d0000 zero za.d\[w8, 0:1, vgx2\]
+.*: c00d6000 zero za.d\[w11, 0:1, vgx2\]
+.*: c00d0003 zero za.d\[w8, 6:7, vgx2\]
+.*: c00d2001 zero za.d\[w9, 2:3, vgx2\]
+.*: c00d8000 zero za.d\[w8, 0:1, vgx4\]
+.*: c00de000 zero za.d\[w11, 0:1, vgx4\]
+.*: c00d8003 zero za.d\[w8, 6:7, vgx4\]
+.*: c00da001 zero za.d\[w9, 2:3, vgx4\]
+.*: c00e8000 zero za.d\[w8, 0:3\]
+.*: c00ee000 zero za.d\[w11, 0:3\]
+.*: c00e8002 zero za.d\[w8, 8:11\]
+.*: c00ee002 zero za.d\[w11, 8:11\]
+.*: c00ea001 zero za.d\[w9, 4:7\]
+.*: c00ec000 zero za.d\[w10, 0:3\]
+.*: c00f0000 zero za.d\[w8, 0:3, vgx2\]
+.*: c00f6000 zero za.d\[w11, 0:3, vgx2\]
+.*: c00f0001 zero za.d\[w8, 4:7, vgx2\]
+.*: c00f6001 zero za.d\[w11, 4:7, vgx2\]
+.*: c00f2000 zero za.d\[w9, 0:3, vgx2\]
+.*: c00f4001 zero za.d\[w10, 4:7, vgx2\]
+.*: c00f8000 zero za.d\[w8, 0:3, vgx4\]
+.*: c00fe000 zero za.d\[w11, 0:3, vgx4\]
+.*: c00f8001 zero za.d\[w8, 4:7, vgx4\]
+.*: c00fe001 zero za.d\[w11, 4:7, vgx4\]
+.*: c00fa000 zero za.d\[w9, 0:3, vgx4\]
+.*: c00fc001 zero za.d\[w10, 4:7, vgx4\]
diff --git a/gas/testsuite/gas/aarch64/sme2p1-5.s b/gas/testsuite/gas/aarch64/sme2p1-5.s
new file mode 100644
index 00000000000..bd25682d2ef
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2p1-5.s
@@ -0,0 +1,54 @@
+/* ZERO (single-vector). */
+zero za.d[w8, 0, vgx2]
+zero za.d[w11, 0, vgx2]
+zero za.d[w8, 7, vgx2]
+zero za.d[w11, 7, vgx2]
+zero za.d[w9, 4, vgx2]
+zero za.d[w10, 3, vgx2]
+
+zero za.d[w8, 0, vgx4]
+zero za.d[w11, 0, vgx4]
+zero za.d[w8, 7, vgx4]
+zero za.d[w11, 7, vgx4]
+zero za.d[w9, 4, vgx4]
+zero za.d[w10, 3, vgx4]
+
+/* ZERO (double-vector). */
+zero za.d[w8, 0:1]
+zero za.d[w11, 0:1]
+zero za.d[w8, 14:15]
+zero za.d[w11, 14:15]
+zero za.d[w9, 2:3]
+zero za.d[w10, 6:7]
+
+zero za.d[w8, 0:1, vgx2]
+zero za.d[w11, 0:1, vgx2]
+zero za.d[w8, 6:7, vgx2]
+zero za.d[w9, 2:3, vgx2]
+
+zero za.d[w8, 0:1, vgx4]
+zero za.d[w11, 0:1, vgx4]
+zero za.d[w8, 6:7, vgx4]
+zero za.d[w9, 2:3, vgx4]
+
+/* ZERO (quad-vector). */
+zero za.d[w8, 0:3]
+zero za.d[w11, 0:3]
+zero za.d[w8, 8:11]
+zero za.d[w11, 8:11]
+zero za.d[w9, 4:7]
+zero za.d[w10, 0:3]
+
+zero za.d[w8, 0:3, vgx2]
+zero za.d[w11, 0:3, vgx2]
+zero za.d[w8, 4:7, vgx2]
+zero za.d[w11, 4:7, vgx2]
+zero za.d[w9, 0:3, vgx2]
+zero za.d[w10, 4:7, vgx2]
+
+zero za.d[w8, 0:3, vgx4]
+zero za.d[w11, 0:3, vgx4]
+zero za.d[w8, 4:7, vgx4]
+zero za.d[w11, 4:7, vgx4]
+zero za.d[w9, 0:3, vgx4]
+zero za.d[w10, 4:7, vgx4]
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 5a2b99d2bc5..1b01931b0cb 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -1387,7 +1387,10 @@ extern const aarch64_opcode aarch64_opcode_table[];
#define F_OPD_SIZE (1ULL << 34)
/* RCPC3 instruction has the field of 'size'. */
#define F_RCPC3_SIZE (1ULL << 35)
-/* Next bit is 36. */
+/* This instruction need VGx2 or VGx4 mandatorily in the operand passed to
+ assembler. */
+#define F_VG_REQ (1ULL << 36)
+/* Next bit is 37. */
/* Instruction constraints. */
/* This instruction has a predication constraint on the instruction at PC+4. */
@@ -1450,6 +1453,12 @@ get_opcode_dependent_value (const aarch64_opcode *opcode)
return (opcode->flags >> 24) & 0x7;
}
+static inline bool
+get_opcode_dependent_vg_status (const aarch64_opcode *opcode)
+{
+ return (opcode->flags >> 36) & 0x1;
+}
+
static inline bool
opcode_has_special_coder (const aarch64_opcode *opcode)
{
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index 7a7af4afea2..4138ec8907f 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -271,7 +271,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000x000101x00xxxxxxxxxxxxxx
luti4. */
- return 3420;
+ return 3428;
}
else
{
@@ -310,7 +310,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx01101x00xxxxxxxxxxxxxx
luti4. */
- return 3421;
+ return 3429;
}
else
{
@@ -408,21 +408,109 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 22) & 0x1) == 0)
{
- if (((word >> 14) & 0x1) == 0)
+ if (((word >> 23) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000000x00011xxx0xx00xxxxxxxxxx
- luti2. */
- return 2668;
+ if (((word >> 15) & 0x1) == 0)
+ {
+ if (((word >> 16) & 0x1) == 0)
+ {
+ if (((word >> 17) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000000011000xxx00xxxxxxxxxx
+ zero. */
+ return 3317;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000000011100xxx00xxxxxxxxxx
+ zero. */
+ return 3318;
+ }
+ }
+ else
+ {
+ if (((word >> 17) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000000011010xxx00xxxxxxxxxx
+ zero. */
+ return 3320;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000000011110xxx00xxxxxxxxxx
+ zero. */
+ return 3323;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 16) & 0x1) == 0)
+ {
+ if (((word >> 17) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000000011001xxx00xxxxxxxxxx
+ zero. */
+ return 3319;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000000011101xxx00xxxxxxxxxx
+ zero. */
+ return 3322;
+ }
+ }
+ else
+ {
+ if (((word >> 17) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000000011011xxx00xxxxxxxxxx
+ zero. */
+ return 3321;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000000011111xxx00xxxxxxxxxx
+ zero. */
+ return 3324;
+ }
+ }
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000000x00011xxx1xx00xxxxxxxxxx
- luti2. */
- return 2667;
+ if (((word >> 14) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000100011xxx0xx00xxxxxxxxxx
+ luti2. */
+ return 2668;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000100011xxx1xx00xxxxxxxxxx
+ luti2. */
+ return 2667;
+ }
}
}
else
@@ -454,7 +542,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000010011x1xxxx00xxxxxxxxxx
movt. */
- return 3422;
+ return 3430;
}
}
else
@@ -1278,7 +1366,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000000101xxxxxxxxxxxxxxxx00xxx
fmopa. */
- return 3488;
+ return 3496;
}
else
{
@@ -1286,7 +1374,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000000101xxxxxxxxxxxxxxxx01xxx
fmopa. */
- return 3487;
+ return 3495;
}
}
else
@@ -1634,7 +1722,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010001xxxx1xx0xxxxx1000xxx
fmlall. */
- return 3481;
+ return 3489;
}
}
}
@@ -1664,7 +1752,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010001xxxxxxx1xxxxxx00xxxx
fdot. */
- return 3466;
+ return 3474;
}
}
else
@@ -2036,7 +2124,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011001xxxxxxx0xxxxxx100xxx
fmlall. */
- return 3480;
+ return 3488;
}
}
}
@@ -2141,7 +2229,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011001xxxxxxx1xxxxxx10xxxx
fmlal. */
- return 3473;
+ return 3481;
}
}
}
@@ -2314,7 +2402,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011001xxxxxxx1xxxxxx11xxxx
fmlal. */
- return 3472;
+ return 3480;
}
}
}
@@ -2356,7 +2444,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010100xxxxxxxxxxxxxxxx0xxx
fmlall. */
- return 3479;
+ return 3487;
}
else
{
@@ -2724,7 +2812,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx000010101xxxx0xx0xxxxxx111xxx
fdot. */
- return 3459;
+ return 3467;
}
else
{
@@ -2793,7 +2881,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx000010101xxxx1xx0xxxxxx001xxx
fdot. */
- return 3460;
+ return 3468;
}
else
{
@@ -2872,7 +2960,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011100xxxxxxx0xxxxxxx0xxxx
fmlal. */
- return 3471;
+ return 3479;
}
else
{
@@ -2927,7 +3015,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011101xxxx0xx01xxxxx00xxxx
fvdotb. */
- return 3490;
+ return 3498;
}
else
{
@@ -2945,7 +3033,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011101xxxxxxx0xxxxxx10xxxx
fdot. */
- return 3465;
+ return 3473;
}
}
}
@@ -3019,7 +3107,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011101xxxxxxx1xxxxxx10xxxx
fvdot. */
- return 3489;
+ return 3497;
}
}
}
@@ -3099,7 +3187,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000001110xxxxx0xx01xxxxxx1xxxx
fvdott. */
- return 3491;
+ return 3499;
}
else
{
@@ -3276,7 +3364,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx00xx000xxxx10000x
fmlall. */
- return 3485;
+ return 3493;
}
else
{
@@ -3284,7 +3372,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx10xx000xxxx10000x
fmlall. */
- return 3486;
+ return 3494;
}
}
}
@@ -3339,7 +3427,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx10xxxx0xx000xxxxx00x1x
fmlall. */
- return 3483;
+ return 3491;
}
else
{
@@ -3347,7 +3435,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx000xxxxx00x1x
fmlall. */
- return 3484;
+ return 3492;
}
}
}
@@ -3401,7 +3489,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx00xx100xxxx100xxx
fdot. */
- return 3469;
+ return 3477;
}
else
{
@@ -3409,7 +3497,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx10xx100xxxx100xxx
fdot. */
- return 3470;
+ return 3478;
}
}
}
@@ -3471,7 +3559,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001101xxxx00xx010xxxx1000xx
fmlal. */
- return 3477;
+ return 3485;
}
else
{
@@ -3479,7 +3567,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001101xxxx10xx010xxxx1000xx
fmlal. */
- return 3478;
+ return 3486;
}
}
}
@@ -3534,7 +3622,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx10xxxx0xx010xxxxx001xx
fmlal. */
- return 3475;
+ return 3483;
}
else
{
@@ -3542,7 +3630,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx010xxxxx001xx
fmlal. */
- return 3476;
+ return 3484;
}
}
}
@@ -3611,7 +3699,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx001xxxxx000xx
fmlall. */
- return 3482;
+ return 3490;
}
}
else
@@ -3694,7 +3782,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx011xxxxx00xxx
fmlal. */
- return 3474;
+ return 3482;
}
}
else
@@ -3715,7 +3803,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xx1x00xx111xxxxx00xxx
fadd. */
- return 3423;
+ return 3431;
}
}
else
@@ -3734,7 +3822,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xx1x10xx111xxxxx00xxx
fadd. */
- return 3424;
+ return 3432;
}
}
}
@@ -3860,7 +3948,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx00xx100xxxx110xxx
fdot. */
- return 3463;
+ return 3471;
}
else
{
@@ -3868,7 +3956,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx10xx100xxxx110xxx
fdot. */
- return 3464;
+ return 3472;
}
}
}
@@ -4159,7 +4247,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx10xxxx0xx100xxxxx01xxx
fdot. */
- return 3467;
+ return 3475;
}
else
{
@@ -4167,7 +4255,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx100xxxxx01xxx
fdot. */
- return 3468;
+ return 3476;
}
}
}
@@ -4438,7 +4526,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xx1x00xx111xxxxx01xxx
fsub. */
- return 3425;
+ return 3433;
}
}
else
@@ -4457,7 +4545,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xx1x10xx111xxxxx01xxx
fsub. */
- return 3426;
+ return 3434;
}
}
}
@@ -4519,7 +4607,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx10xxxx0xx100xxxxx11xxx
fdot. */
- return 3461;
+ return 3469;
}
else
{
@@ -4527,7 +4615,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx100xxxxx11xxx
fdot. */
- return 3462;
+ return 3470;
}
}
}
@@ -5062,7 +5150,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xxxxx101000xx1x0xxxx0
fscale. */
- return 3397;
+ return 3405;
}
}
else
@@ -5210,7 +5298,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001x0100100111000xxxx0xxxxx
fcvt. */
- return 3394;
+ return 3402;
}
else
{
@@ -5218,7 +5306,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001x1100100111000xxxx0xxxxx
bfcvt. */
- return 3389;
+ return 3397;
}
}
else
@@ -5227,7 +5315,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx110100111000xxxx0xxxxx
fcvt. */
- return 3395;
+ return 3403;
}
}
else
@@ -5278,7 +5366,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xx100111000xxxx1xxxxx
fcvtn. */
- return 3396;
+ return 3404;
}
}
}
@@ -5361,7 +5449,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000010010x110111000xxxxxxxxx0
f1cvt. */
- return 3390;
+ return 3398;
}
else
{
@@ -5369,7 +5457,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011010x110111000xxxxxxxxx0
f2cvt. */
- return 3391;
+ return 3399;
}
}
else
@@ -5380,7 +5468,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000010110x110111000xxxxxxxxx0
bf1cvt. */
- return 3385;
+ return 3393;
}
else
{
@@ -5388,7 +5476,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011110x110111000xxxxxxxxx0
bf2cvt. */
- return 3386;
+ return 3394;
}
}
}
@@ -5423,7 +5511,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001001xxx10111000xxxxxxxxx1
f1cvtl. */
- return 3392;
+ return 3400;
}
else
{
@@ -5431,7 +5519,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001101xxx10111000xxxxxxxxx1
f2cvtl. */
- return 3393;
+ return 3401;
}
}
else
@@ -5442,7 +5530,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001011xxx10111000xxxxxxxxx1
bf1cvtl. */
- return 3387;
+ return 3395;
}
else
{
@@ -5450,7 +5538,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001111xxx10111000xxxxxxxxx1
bf2cvtl. */
- return 3388;
+ return 3396;
}
}
}
@@ -5719,7 +5807,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xxxxx1x1100xx100xxxx0
fscale. */
- return 3399;
+ return 3407;
}
}
else
@@ -5895,7 +5983,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xxxxx1x1010xx100xxxx0
fscale. */
- return 3398;
+ return 3406;
}
else
{
@@ -5903,7 +5991,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xxxxx1x1110xx100xxxx0
fscale. */
- return 3400;
+ return 3408;
}
}
}
@@ -11071,7 +11159,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x11010000xxxxxxx1xxxxxxxxxxxxx
addpt. */
- return 3401;
+ return 3409;
}
else
{
@@ -11079,7 +11167,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1x11010000xxxxxxx1xxxxxxxxxxxxx
subpt. */
- return 3402;
+ return 3410;
}
}
}
@@ -11997,7 +12085,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxx1011x11xxxxx0xxxxxxxxxxxxxxx
maddpt. */
- return 3403;
+ return 3411;
}
else
{
@@ -12005,7 +12093,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxx1011x11xxxxx1xxxxxxxxxxxxxxx
msubpt. */
- return 3404;
+ return 3412;
}
}
}
@@ -12090,7 +12178,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx000100000xxxxxxxxxxxxx
addpt. */
- return 3405;
+ return 3413;
}
else
{
@@ -12197,7 +12285,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx000101000xxxxxxxxxxxxx
subpt. */
- return 3407;
+ return 3415;
}
else
{
@@ -12402,7 +12490,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx1xxxxx000010xxxxxxxxxx
addpt. */
- return 3406;
+ return 3414;
}
else
{
@@ -12443,7 +12531,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx1xxxxx000011xxxxxxxxxx
subpt. */
- return 3408;
+ return 3416;
}
else
{
@@ -14101,7 +14189,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx110100xxxxxxxxxx
mlapt. */
- return 3410;
+ return 3418;
}
}
else
@@ -14131,7 +14219,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx110110xxxxxxxxxx
madpt. */
- return 3409;
+ return 3417;
}
}
}
@@ -14439,7 +14527,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx00x100001xxxxxxxxxxxxx
smaxqv. */
- return 3319;
+ return 3327;
}
else
{
@@ -14447,7 +14535,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx01x100001xxxxxxxxxxxxx
orqv. */
- return 3330;
+ return 3338;
}
}
else
@@ -14458,7 +14546,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx0x0101001xxxxxxxxxxxxx
addqv. */
- return 3317;
+ return 3325;
}
else
{
@@ -14468,7 +14556,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx001101001xxxxxxxxxxxxx
umaxqv. */
- return 3321;
+ return 3329;
}
else
{
@@ -14476,7 +14564,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx011101001xxxxxxxxxxxxx
eorqv. */
- return 3323;
+ return 3331;
}
}
}
@@ -14513,7 +14601,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx00x110001xxxxxxxxxxxxx
sminqv. */
- return 3320;
+ return 3328;
}
else
{
@@ -14521,7 +14609,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx01x110001xxxxxxxxxxxxx
andqv. */
- return 3318;
+ return 3326;
}
}
}
@@ -14541,7 +14629,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx0xx111001xxxxxxxxxxxxx
uminqv. */
- return 3322;
+ return 3330;
}
}
}
@@ -15285,7 +15373,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
110001x0x00xxxxx101xxxxxxxxxxxxx
ld1q. */
- return 3346;
+ return 3354;
}
else
{
@@ -16299,7 +16387,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx111x00xxxxxxxxxx
zipq1. */
- return 3336;
+ return 3344;
}
else
{
@@ -16309,7 +16397,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx111010xxxxxxxxxx
uzpq1. */
- return 3334;
+ return 3342;
}
else
{
@@ -16317,7 +16405,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx111110xxxxxxxxxx
tblq. */
- return 3331;
+ return 3339;
}
}
}
@@ -16329,7 +16417,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx111x01xxxxxxxxxx
zipq2. */
- return 3337;
+ return 3345;
}
else
{
@@ -16337,7 +16425,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx111x11xxxxxxxxxx
uzpq2. */
- return 3335;
+ return 3343;
}
}
}
@@ -16817,7 +16905,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0x00xxxxx000xxxxxxxxxxxxx
st3q. */
- return 3355;
+ return 3363;
}
else
{
@@ -16827,7 +16915,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0010xxxxx000xxxxxxxxxxxxx
st2q. */
- return 3354;
+ return 3362;
}
else
{
@@ -16835,7 +16923,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0110xxxxx000xxxxxxxxxxxxx
st4q. */
- return 3356;
+ return 3364;
}
}
}
@@ -17282,7 +17370,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0xx0x0000101xxxxxxxxxxxxx
faddqv. */
- return 3324;
+ return 3332;
}
else
{
@@ -17299,7 +17387,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0xx0xx100101xxxxxxxxxxxxx
fmaxnmqv. */
- return 3325;
+ return 3333;
}
}
else
@@ -17340,7 +17428,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0xx0xx110101xxxxxxxxxxxxx
fmaxqv. */
- return 3326;
+ return 3334;
}
}
}
@@ -17362,7 +17450,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0xx0xx101101xxxxxxxxxxxxx
fminnmqv. */
- return 3327;
+ return 3335;
}
}
else
@@ -17381,7 +17469,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0xx0xx111101xxxxxxxxxxxxx
fminqv. */
- return 3328;
+ return 3336;
}
}
}
@@ -17501,7 +17589,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x0xx01xxxx111xxxxxxxxxxxxx
ld2q. */
- return 3347;
+ return 3355;
}
}
}
@@ -17637,7 +17725,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x0xx1xxxxx100xxxxxxxxxxxxx
ld2q. */
- return 3350;
+ return 3358;
}
}
else
@@ -17782,7 +17870,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x00x1xxxxx000xxxxxxxxxxxxx
st2q. */
- return 3357;
+ return 3365;
}
}
else
@@ -17825,7 +17913,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0101xxxxx000xxxxxxxxxxxxx
st3q. */
- return 3358;
+ return 3366;
}
}
else
@@ -17866,7 +17954,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0111xxxxx000xxxxxxxxxxxxx
st4q. */
- return 3359;
+ return 3367;
}
}
}
@@ -17895,7 +17983,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0001xxxxx0100x1xxxxxxxxxx
fdot. */
- return 3446;
+ return 3454;
}
}
else
@@ -17904,7 +17992,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0001xxxxx0101xxxxxxxxxxxx
fmlalb. */
- return 3448;
+ return 3456;
}
}
else
@@ -17945,7 +18033,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0101xxxxx0101xxxxxxxxxxxx
fmlalt. */
- return 3458;
+ return 3466;
}
}
else
@@ -17978,7 +18066,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0011xxxxx010xx1xxxxxxxxxx
fdot. */
- return 3444;
+ return 3452;
}
}
else
@@ -18049,7 +18137,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx100010xxxxxxxxxx
fmlallbb. */
- return 3449;
+ return 3457;
}
}
else
@@ -18058,7 +18146,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1000x1xxxxxxxxxx
fdot. */
- return 3445;
+ return 3453;
}
}
else
@@ -18067,7 +18155,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1100xxxxxxxxxxxx
fmlallbb. */
- return 3450;
+ return 3458;
}
}
else
@@ -18076,7 +18164,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1x01xxxxxxxxxxxx
fmlallbt. */
- return 3451;
+ return 3459;
}
}
else
@@ -18103,7 +18191,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0101xxxxx100010xxxxxxxxxx
fmlalb. */
- return 3447;
+ return 3455;
}
}
else
@@ -18121,7 +18209,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0101xxxxx1100xxxxxxxxxxxx
fmlalltb. */
- return 3454;
+ return 3462;
}
}
else
@@ -18130,7 +18218,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0101xxxxx1x01xxxxxxxxxxxx
fmlalt. */
- return 3457;
+ return 3465;
}
}
else
@@ -18163,7 +18251,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0011xxxxx100xx1xxxxxxxxxx
fdot. */
- return 3443;
+ return 3451;
}
}
else
@@ -18172,7 +18260,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0011xxxxx110xxxxxxxxxxxxx
fmlallbt. */
- return 3452;
+ return 3460;
}
}
else
@@ -18204,7 +18292,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0111xxxxx110xxxxxxxxxxxxx
fmlalltt. */
- return 3456;
+ return 3464;
}
}
else
@@ -18503,7 +18591,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0xx1xxxxx001xxxxxxxxxxxxx
st1q. */
- return 3353;
+ return 3361;
}
}
else
@@ -18518,7 +18606,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1010xxxxxxxxxxxx
fmlalltb. */
- return 3453;
+ return 3461;
}
else
{
@@ -18526,7 +18614,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1011xxxxxxxxxxxx
fmlalltt. */
- return 3455;
+ return 3463;
}
}
else
@@ -19244,7 +19332,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x1001010x0001110xxxxxxxxxx
pmov. */
- return 3338;
+ return 3346;
}
else
{
@@ -19252,7 +19340,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x1001011x0001110xxxxxxxxxx
pmov. */
- return 3339;
+ return 3347;
}
}
else
@@ -19261,7 +19349,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x101101xx0001110xxxxxxxxxx
pmov. */
- return 3340;
+ return 3348;
}
}
else
@@ -19270,7 +19358,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x11x101xx0001110xxxxxxxxxx
pmov. */
- [...]
[diff truncated at 100000 bytes]