[binutils-gdb] RISC-V: Add platform property/capability extensions
Nelson Chu
nelsonc1225@sourceware.org
Thu Jul 11 05:01:25 GMT 2024
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=25f05199bb7e35820c23e802424484accb7936b1
commit 25f05199bb7e35820c23e802424484accb7936b1
Author: Tsukasa OI <research_trasio@irq.a4lg.com>
Date: Wed Jul 26 00:05:53 2023 +0000
RISC-V: Add platform property/capability extensions
RISC-V Profiles document defines number of "extensions" that indicate
certain platform properties/capabilities just like 'Zkt' extension from the
RISC-V cryptography extensions.
This commit defines 20 platform property/capability extensions as defined
in the RISC-V Profiles documentation.
The only exception: 'Ssstateen' extension is defined separately because it
defines a subset (supervisor/hypervisor view) of the 'Smstateen' extension.
This is based on the ratified version of RISC-V Profiles:
<https://github.com/riscv/riscv-profiles/releases/tag/v1.0>
[Definition]
"Main memory regions":
Main memory regions (in contrast to I/O or vacant memory regions) with
both the cacheability and coherence PMAs.
[New Unprivileged Extensions]
1. 'Ziccif'
"Main memory regions" support instruction fetch and any instruction
fetches of naturally aligned power-of-2 sizes up to min(ILEN, XLEN)
are atomic.
2. 'Ziccrse'
"Main memory regions" provide the eventual success guarantee for
LR/SC sequence (RsrvEventual).
3. 'Ziccamoa'
"Main memory regions" support all currently-defined AMO operations
including swap, logical and arithmetic operations (AMOArithmetic).
4. 'Za64rs'
For LR/SC instructions, reservation sets are contiguous, naturally
aligned and at most 64-bytes in size.
5. 'Za128rs'
Likewise, but reservation sets are at most 128-bytes in size.
6. 'Zicclsm'
Misaligned loads / stores to "main memory regions" are supported.
Those include both regular scalar and vector accesses but does not
include AMOs and other specialized forms of memory accesses.
7. 'Zic64b'
Cache blocks are (exactly) 64-bytes in size and naturally aligned.
[New Privileged Extensions]
1. 'Svbare'
"satp" mode Bare is supported.
2. 'Svade'
Page-fault exceptions are raised when a page is accessed when A bit is
clear, or written when D bit is clear.
3. 'Ssccptr'
"Main memory regions" support hardware page-table reads.
4. 'Sstvecd'
"stvec" mode Direct is supported. When "stvec" mode is Direct,
"stvec.BASE" is capable of holding any valid 4-byte aligned address.
5. 'Sstvala'
"stval" is always written with a nonzero value whenever possible as
specified in the Privileged Architecture documentation
(version 20211203: see section 4.1.9).
6. 'Sscounterenw'
For any "hpmcounter" that is not read-only zero, the corresponding bit
in "scounteren" is writable.
7. 'Ssu64xl'
"sstatus.UXL" is capable of holding the value 0b10
(UXLEN==64 is supported).
8. 'Shcounterenw'
Similar to 'Sscounterenw' but the same rule applies to "hcounteren".
9. 'Shvstvala'
Similar to 'Sstvala' but the same rule applies to "vstval".
10. 'Shtvala'
"htval" is written with the faulting guest physical address as long as
permitted by the ISA (a bit similar to 'Sstvala' and 'Shvstvala').
11. 'Shvstvecd'
Similar to 'Sstvecd' but the same rule applies to "vstvec".
12. 'Shvsatpa'
All translation modes supported in "satp" are also supported in "vsatp".
13. 'Shgatpa'
For each supported virtual memory scheme SvNN supported in "satp", the
corresponding "hgatp" SvNNx4 mode is supported. The "hgatp" mode Bare
is also supported.
[Implications]
(Due to reservation set size constraints)
- 'Za64rs' -> 'Za128rs'
(Due to the fact that a privileged "extension" directly refers a CSR)
- 'Svbare' -> 'Zicsr'
- 'Sstvecd' -> 'Zicsr'
- 'Sstvala' -> 'Zicsr'
- 'Sscounterenw' -> 'Zicsr'
- 'Ssu64xl' -> 'Zicsr'
(Due to the fact that a privileged "extension" indirectly depends on CSRs)
- 'Svade' -> 'Zicsr'
(Due to the fact that a privileged "extension" is a hypervisor property)
- 'Shcounterenw' -> 'H'
- 'Shvstvala' -> 'H'
- 'Shtvala' -> 'H'
- 'Shvstvecd' -> 'H'
- 'Shvsatpa' -> 'H'
- 'Shgatpa' -> 'H'
bfd/
* elfxx-riscv.c (riscv_implicit_subsets): Updated for property
and capability extensions.
(riscv_supported_std_z_ext): Added zic64b, ziccamoa, ziccif, zicclsm,
ziccrse, za64rs and za128rs extensions.
(riscv_supported_std_s_ext): Added shcounterenw, shgatpa, shtvala,
shvsatpa, shvstvala, shvstvecd, ssccptr, sscounterenw, sstvala,
sstvecd, ssu64xlm svade and svbare extensions.
gas/
* testsuite/gas/riscv/imply.d: Updated for property and capability
extensions.
* testsuite/gas/riscv/imply.s: Likewise.
* testsuite/gas/riscv/march-help.l: Likewse.
Diff:
---
bfd/elfxx-riscv.c | 33 +++++++++++++++++++++++++++++++++
gas/testsuite/gas/riscv/imply.d | 12 ++++++++++++
gas/testsuite/gas/riscv/imply.s | 13 +++++++++++++
gas/testsuite/gas/riscv/march-help.l | 20 ++++++++++++++++++++
4 files changed, 78 insertions(+)
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 44dd62492ed..b3adbed1913 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1214,6 +1214,12 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
{"zcf", "+f,+zca", check_implicit_always},
{"zcmp", "+zca", check_implicit_always},
+ {"shcounterenw", "+h", check_implicit_always},
+ {"shgatpa", "+h", check_implicit_always},
+ {"shtvala", "+h", check_implicit_always},
+ {"shvsatpa", "+h", check_implicit_always},
+ {"shvstvala", "+h", check_implicit_always},
+ {"shvstvecd", "+h", check_implicit_always},
{"h", "+zicsr", check_implicit_always},
{"zhinx", "+zhinxmin", check_implicit_always},
{"zhinxmin", "+zfinx", check_implicit_always},
@@ -1253,9 +1259,16 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
{"ssaia", "+zicsr", check_implicit_always},
{"sscsrind", "+zicsr", check_implicit_always},
{"sscofpmf", "+zicsr", check_implicit_always},
+ {"sscounterenw", "+zicsr", check_implicit_always},
{"ssstateen", "+zicsr", check_implicit_always},
{"sstc", "+zicsr", check_implicit_always},
+ {"sstvala", "+zicsr", check_implicit_always},
+ {"sstvecd", "+zicsr", check_implicit_always},
+ {"ssu64xl", "+zicsr", check_implicit_always},
+
+ {"svade", "+zicsr", check_implicit_always},
{"svadu", "+zicsr", check_implicit_always},
+ {"svbare", "+zicsr", check_implicit_always},
{NULL, NULL, NULL}
};
@@ -1314,6 +1327,11 @@ static struct riscv_supported_ext riscv_supported_std_ext[] =
static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{
+ {"zic64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"ziccamoa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"ziccif", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zicclsm", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"ziccrse", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zicbom", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zicbop", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zicboz", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
@@ -1327,6 +1345,8 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{"zihintpause", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 },
{"zihpm", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 },
{"zmmul", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"za64rs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"za128rs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zaamo", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zabha", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zacas", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
@@ -1406,17 +1426,30 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
static struct riscv_supported_ext riscv_supported_std_s_ext[] =
{
+ {"shcounterenw", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"shgatpa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"shtvala", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"shvsatpa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"shvstvala", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"shvstvecd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"smaia", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"smcsrind", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"smcntrpmf", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"smepmp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"smstateen", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"ssaia", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"ssccptr", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"sscsrind", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"sscofpmf", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"sscounterenw", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"ssstateen", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"sstc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"sstvala", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"sstvecd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"ssu64xl", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"svade", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"svadu", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"svbare", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"svinval", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"svnapot", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"svpbmt", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
diff --git a/gas/testsuite/gas/riscv/imply.d b/gas/testsuite/gas/riscv/imply.d
index dee889099f4..0c726d3ab79 100644
--- a/gas/testsuite/gas/riscv/imply.d
+++ b/gas/testsuite/gas/riscv/imply.d
@@ -44,6 +44,12 @@ SYMBOL TABLE:
[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_d2p2_zicsr2p0_zca1p0_zcd1p0
[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_zicsr2p0_zca1p0_zcf1p0
[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zca1p0_zcmp1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_h1p0_zicsr2p0_shcounterenw1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_h1p0_zicsr2p0_shgatpa1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_h1p0_zicsr2p0_shtvala1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_h1p0_zicsr2p0_shvsatpa1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_h1p0_zicsr2p0_shvstvala1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_h1p0_zicsr2p0_shvstvecd1p0
[0-9a-f]+ l .text 0+000 \$xrv32i2p1_h1p0_zicsr2p0
[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zfinx1p0_zhinx1p0_zhinxmin1p0
[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zfinx1p0_zhinxmin1p0
@@ -76,7 +82,13 @@ SYMBOL TABLE:
[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_ssaia1p0
[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_sscsrind1p0
[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_sscofpmf1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_sscounterenw1p0
[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_ssstateen1p0
[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_sstc1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_sstvala1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_sstvecd1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_ssu64xl1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_svade1p0
[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_svadu1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_svbare1p0
[0-9a-f]+ l d .riscv.attributes 0+000 .riscv.attributes
diff --git a/gas/testsuite/gas/riscv/imply.s b/gas/testsuite/gas/riscv/imply.s
index f341283c968..8eca66f7a89 100644
--- a/gas/testsuite/gas/riscv/imply.s
+++ b/gas/testsuite/gas/riscv/imply.s
@@ -48,6 +48,12 @@ imply zcd
imply zcf
imply zcmp
+imply shcounterenw
+imply shgatpa
+imply shtvala
+imply shvsatpa
+imply shvstvala
+imply shvstvecd
imply h
imply zhinx
imply zhinxmin
@@ -86,6 +92,13 @@ imply smepmp
imply ssaia
imply sscsrind
imply sscofpmf
+imply sscounterenw
imply ssstateen
imply sstc
+imply sstvala
+imply sstvecd
+imply ssu64xl
+
+imply svade
imply svadu
+imply svbare
diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l
index c33d856686b..97521c7c02b 100644
--- a/gas/testsuite/gas/riscv/march-help.l
+++ b/gas/testsuite/gas/riscv/march-help.l
@@ -10,6 +10,11 @@ All available -march extensions for RISC-V:
b 1.0
v 1.0
h 1.0
+ zic64b 1.0
+ ziccamoa 1.0
+ ziccif 1.0
+ zicclsm 1.0
+ ziccrse 1.0
zicbom 1.0
zicbop 1.0
zicboz 1.0
@@ -21,6 +26,8 @@ All available -march extensions for RISC-V:
zihintpause 2.0
zihpm 2.0
zmmul 1.0
+ za64rs 1.0
+ za128rs 1.0
zaamo 1.0
zabha 1.0
zacas 1.0
@@ -95,17 +102,30 @@ All available -march extensions for RISC-V:
zcf 1.0
zcd 1.0
zcmp 1.0
+ shcounterenw 1.0
+ shgatpa 1.0
+ shtvala 1.0
+ shvsatpa 1.0
+ shvstvala 1.0
+ shvstvecd 1.0
smaia 1.0
smcsrind 1.0
smcntrpmf 1.0
smepmp 1.0
smstateen 1.0
ssaia 1.0
+ ssccptr 1.0
sscsrind 1.0
sscofpmf 1.0
+ sscounterenw 1.0
ssstateen 1.0
sstc 1.0
+ sstvala 1.0
+ sstvecd 1.0
+ ssu64xl 1.0
+ svade 1.0
svadu 1.0
+ svbare 1.0
svinval 1.0
svnapot 1.0
svpbmt 1.0
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