https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=de7a30ceaa4df45d05e12338744f1ad20f1e4032
commit de7a30ceaa4df45d05e12338744f1ad20f1e4032
Author: srinath <srinath.parvathaneni@arm.com>
Date: Mon Jul 8 17:44:33 2024 +0100
aarch64: Add support for sve2p1 pmov instruction.
This patch adds support for followign SVE2p1 instruction, spec is available here [1].
1. PMOV (to vector)
2. PMOV (to predicate)
Both pmov (to vector) and pmov (to predicate) have destination scalable vector
register and source scalable vector register respectively as an operand with no
suffix and optional index. To handle this case we have added 8 new operands in
this patch.
AARCH64_OPND_SVE_Zn0_INDEX, /* Zn[index], bits [9:5]. */
AARCH64_OPND_SVE_Zn1_17_INDEX, /* Zn[index], bits [9:5,17]. */
AARCH64_OPND_SVE_Zn2_18_INDEX, /* Zn[index], bits [9:5,18:17]. */
AARCH64_OPND_SVE_Zn3_22_INDEX, /* Zn[index], bits [9:5,18:17,22]. */
AARCH64_OPND_SVE_Zd0_INDEX, /* Zn[index], bits [4:0]. */
AARCH64_OPND_SVE_Zd1_17_INDEX, /* Zn[index], bits [4:0,17]. */
AARCH64_OPND_SVE_Zd2_18_INDEX, /* Zn[index], bits [4:0,18:17]. */
AARCH64_OPND_SVE_Zd3_22_INDEX, /* Zn[index], bits [4:0,18:17,22]. */
Since the index of the <Zd> operand is optional, the index part is
dropped in disassembly in both the cases of "no index" or "zero index".
As per spec: PMOV <Zd>{[<imm>]}, <Pn>.D
PMOV <Pn>.D, <Zd>{[<imm>]}
Example1:
Assembly: pmov z5[0], p6.d
Disassembly: pmov z5, p6.d
Assembly: pmov z5, p6.d
Disassembly: pmov z5, p6.d
Example2:
Assembly: pmov p4.b, z5[0]
Disassembly: pmov p4.b, z5
Assembly: pmov p4.b, z5
Disassembly: pmov p4.b, z5
[1]: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions?lang=en
Diff:
---
gas/config/tc-aarch64.c | 28 +-
gas/testsuite/gas/aarch64/sve2p1-7-invalid.d | 3 +
gas/testsuite/gas/aarch64/sve2p1-7-invalid.l | 118 +++++++
gas/testsuite/gas/aarch64/sve2p1-7-invalid.s | 76 +++++
gas/testsuite/gas/aarch64/sve2p1-7.d | 64 ++++
gas/testsuite/gas/aarch64/sve2p1-7.s | 63 ++++
include/opcode/aarch64.h | 8 +
opcodes/aarch64-asm-2.c | 40 ++-
opcodes/aarch64-dis-2.c | 492 ++++++++++++++++-----------
opcodes/aarch64-opc-2.c | 8 +
opcodes/aarch64-opc.c | 34 +-
opcodes/aarch64-opc.h | 2 +
opcodes/aarch64-tbl.h | 54 ++-
13 files changed, 766 insertions(+), 224 deletions(-)
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 3dfbeb7bd00..8690b8f9142 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -113,6 +113,7 @@ enum vector_el_type
#define NTA_HASTYPE 1
#define NTA_HASINDEX 2
#define NTA_HASVARWIDTH 4
+#define NTA_NOINDEX 8
struct vector_type_el
{
@@ -1185,11 +1186,15 @@ parse_index_expression (char **str, int64_t *imm)
register index.
FLAGS includes PTR_GOOD_MATCH if we are sufficiently far into parsing
- an operand that we can be confident that it is a good match. */
+ an operand that we can be confident that it is a good match.
+
+ FLAGS includes PTR_OPTIONAL_INDEX to handle instructions with optional index
+ operands. */
#define PTR_IN_REGLIST (1U << 0)
#define PTR_FULL_REG (1U << 1)
#define PTR_GOOD_MATCH (1U << 2)
+#define PTR_OPTIONAL_INDEX (1U << 3)
static const reg_entry *
parse_typed_reg (char **ccp, aarch64_reg_type type,
@@ -1277,7 +1282,10 @@ parse_typed_reg (char **ccp, aarch64_reg_type type,
atype.width = parsetype.width;
}
- if (!(flags & PTR_FULL_REG) && skip_past_char (&str, '['))
+ if ((flags & PTR_OPTIONAL_INDEX) && (*str == '\0' || *str == ','))
+ atype.defined |= NTA_NOINDEX;
+ else if ((!(flags & PTR_FULL_REG) || (flags & PTR_OPTIONAL_INDEX))
+ && skip_past_char (&str, '['))
{
/* Reject Sn[index] syntax. */
if (reg->type != REG_TYPE_Z
@@ -6886,6 +6894,20 @@ parse_operands (char *str, const aarch64_opcode *opcode)
reg_type = REG_TYPE_Z;
goto vector_reg_index;
+ case AARCH64_OPND_SVE_Zn0_INDEX:
+ case AARCH64_OPND_SVE_Zn1_17_INDEX:
+ case AARCH64_OPND_SVE_Zn2_18_INDEX:
+ case AARCH64_OPND_SVE_Zn3_22_INDEX:
+ case AARCH64_OPND_SVE_Zd0_INDEX:
+ case AARCH64_OPND_SVE_Zd1_17_INDEX:
+ case AARCH64_OPND_SVE_Zd2_18_INDEX:
+ case AARCH64_OPND_SVE_Zd3_22_INDEX:
+ reg_type = REG_TYPE_Z;
+ reg = parse_typed_reg (&str, reg_type, &vectype, PTR_OPTIONAL_INDEX);
+ if (!reg || !(vectype.defined & (NTA_HASINDEX | NTA_NOINDEX)))
+ goto failure;
+ goto vector_reg_optional_index;
+
case AARCH64_OPND_Ed:
case AARCH64_OPND_En:
case AARCH64_OPND_Em:
@@ -6899,7 +6921,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
goto failure;
if (!(vectype.defined & NTA_HASINDEX))
goto failure;
-
+ vector_reg_optional_index:
if (reg->type == REG_TYPE_Z && vectype.type == NT_invtype)
/* Unqualified Zn[index] is allowed in LUTI2 instructions. */
info->qualifier = AARCH64_OPND_QLF_NIL;
diff --git a/gas/testsuite/gas/aarch64/sve2p1-7-invalid.d b/gas/testsuite/gas/aarch64/sve2p1-7-invalid.d
new file mode 100644
index 00000000000..ddf2ccb0deb
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-7-invalid.d
@@ -0,0 +1,3 @@
+#name: Test of illegal pmov instruction.
+#as: -march=armv9.4-a
+#error_output: sve2p1-7-invalid.l
diff --git a/gas/testsuite/gas/aarch64/sve2p1-7-invalid.l b/gas/testsuite/gas/aarch64/sve2p1-7-invalid.l
new file mode 100644
index 00000000000..4559f6f8d36
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-7-invalid.l
@@ -0,0 +1,118 @@
+.*: Assembler messages:
+.*: Error: operand mismatch -- `pmov p0,z0'
+.*: Info: did you mean this\?
+.*: Info: pmov p0.h, z0
+.*: Error: expected an SVE vector or predicate register at operand 1 -- `pmov p16.b,z0'
+.*: Error: register element index must be 0 at operand 2 -- `pmov p0.b,z31\[1\]'
+.*: Error: comma expected between operands at operand 2 -- `pmov p15.b'
+.*: Error: operand mismatch -- `pmov p15,z31.b\[4\]'
+.*: Info: did you mean this\?
+.*: Info: pmov p15.h, z31\[4\]
+.*: Error: operand mismatch -- `pmov p7,z15.b'
+.*: Info: did you mean this\?
+.*: Info: pmov p7.h, z15
+.*: Error: expected an SVE predicate register at operand 2 -- `mov p7,w15.b'
+.*: Error: expected an SVE predicate register at operand 2 -- `mov p7.b,x15'
+.*: Error: operand mismatch -- `pmov p0,z0\[3\]'
+.*: Info: did you mean this\?
+.*: Info: pmov p0.h, z0\[3\]
+.*: Error: expected an SVE vector or predicate register at operand 1 -- `pmov p16.h,z0'
+.*: Error: register element index out of range 0 to 1 at operand 2 -- `pmov p0.h,z31\[2\]'
+.*: Error: comma expected between operands at operand 2 -- `pmov p15.h'
+.*: Error: operand mismatch -- `pmov p15,z31.h\[4\]'
+.*: Info: did you mean this\?
+.*: Info: pmov p15.h, z31\[4\]
+.*: Error: operand mismatch -- `pmov p7.h,z15.h'
+.*: Info: did you mean this\?
+.*: Info: pmov p7.h, z15
+.*: Error: expected an SVE vector register at operand 2 -- `pmov p7.h,x15.h'
+.*: Error: expected an SVE vector register at operand 2 -- `pmov p7.h,w15'
+.*: Error: operand mismatch -- `pmov p0,z0\[4\]'
+.*: Info: did you mean this\?
+.*: Info: pmov p0.h, z0\[4\]
+.*: Error: expected an SVE vector or predicate register at operand 1 -- `pmov p16.s,z0'
+.*: Error: register element index out of range 0 to 3 at operand 2 -- `pmov p0.s,z31\[5\]'
+.*: Error: comma expected between operands at operand 2 -- `pmov p15.s'
+.*: Error: operand mismatch -- `pmov p15,z31.s\[6\]'
+.*: Info: did you mean this\?
+.*: Info: pmov p15.h, z31\[6\]
+.*: Error: operand mismatch -- `pmov p7.s,z15.s'
+.*: Info: did you mean this\?
+.*: Info: pmov p7.s, z15
+.*: Error: expected an SVE vector register at operand 2 -- `pmov p7.s,w15.s'
+.*: Error: expected an SVE vector register at operand 2 -- `pmov p7.s,x15'
+.*: Error: operand mismatch -- `pmov p0,z0\[8\]'
+.*: Info: did you mean this\?
+.*: Info: pmov p0.h, z0\[8\]
+.*: Error: expected an SVE vector or predicate register at operand 1 -- `pmov p16.d,z0'
+.*: Error: register element index out of range 0 to 7 at operand 2 -- `pmov p0.d,z31\[10\]'
+.*: Error: comma expected between operands at operand 2 -- `pmov p15.d'
+.*: Error: operand mismatch -- `pmov p15,z31.d\[12\]'
+.*: Info: did you mean this\?
+.*: Info: pmov p15.h, z31\[12\]
+.*: Error: operand mismatch -- `pmov p7.d,z15.d'
+.*: Info: did you mean this\?
+.*: Info: pmov p7.d, z15
+.*: Error: expected an SVE vector register at operand 2 -- `pmov p7.d,x15.d'
+.*: Error: expected an SVE vector register at operand 2 -- `pmov p7.d,w15'
+.*: Error: operand mismatch -- `pmov z0,p0'
+.*: Info: did you mean this\?
+.*: Info: pmov z0, p0.b
+.*: Error: expected an SVE predicate register at operand 2 -- `pmov z0,p16.b'
+.*: Error: register element index must be 0 at operand 1 -- `pmov z31\[1\],p0.b'
+.*: Error: comma expected between operands at operand 2 -- `pmov p15.b'
+.*: Error: operand mismatch -- `pmov z31.b\[4\],p15'
+.*: Info: did you mean this\?
+.*: Info: pmov z31\[4\], p15.b
+.*: Error: operand mismatch -- `pmov z15.b,p7.b'
+.*: Info: did you mean this\?
+.*: Info: pmov z15, p7.b
+.*: Error: expected an SVE vector or predicate register at operand 1 -- `pmov x15.b,p7.b'
+.*: Error: expected an SVE vector or predicate register at operand 1 -- `pmov w15.b,p7'
+.*: Error: operand mismatch -- `pmov z0\[3\],p0'
+.*: Info: did you mean this\?
+.*: Info: pmov z0\[3\], p0.b
+.*: Error: expected an SVE predicate register at operand 2 -- `pmov z0,p16.h'
+.*: Error: register element index out of range 0 to 1 at operand 1 -- `pmov z31\[2\],p0.h'
+.*: Error: comma expected between operands at operand 2 -- `pmov p15.h'
+.*: Error: operand mismatch -- `pmov z31.h\[5\],p15'
+.*: Info: did you mean this\?
+.*: Info: pmov z31\[5\], p15.b
+.*: Error: operand mismatch -- `pmov z15,p7'
+.*: Info: did you mean this\?
+.*: Info: pmov z15, p7.b
+.*: Error: operand mismatch -- `pmov z8.h,p7.h'
+.*: Info: did you mean this\?
+.*: Info: pmov z8, p7.h
+.*: Error: expected an SVE vector or predicate register at operand 1 -- `pmov x8.h,p7.h'
+.*: Error: expected an SVE vector or predicate register at operand 1 -- `pmov w8.h,p7'
+.*: Error: register element index out of range 0 to 3 at operand 1 -- `pmov z0\[5\],p0.s'
+.*: Error: expected an SVE predicate register at operand 2 -- `pmov z0,p16.s'
+.*: Error: register element index out of range 0 to 3 at operand 1 -- `pmov z31\[6\],p0.s'
+.*: Error: comma expected between operands at operand 2 -- `pmov p15.s'
+.*: Error: operand mismatch -- `pmov z31.s\[7\],p15'
+.*: Info: did you mean this\?
+.*: Info: pmov z31\[7\], p15.b
+.*: Error: operand mismatch -- `pmov z15,p7'
+.*: Info: did you mean this\?
+.*: Info: pmov z15, p7.b
+.*: Error: operand mismatch -- `pmov z8.s,p7.s'
+.*: Info: did you mean this\?
+.*: Info: pmov z8, p7.s
+.*: Error: expected an SVE vector or predicate register at operand 1 -- `pmov x8.s,p7.s'
+.*: Error: expected an SVE vector or predicate register at operand 1 -- `pmov w8.s,p7'
+.*: Error: register element index out of range 0 to 7 at operand 1 -- `pmov z0\[8\],p0.d'
+.*: Error: expected an SVE predicate register at operand 2 -- `pmov z0,p16.d'
+.*: Error: register element index out of range 0 to 7 at operand 1 -- `pmov z31\[9\],p0.d'
+.*: Error: comma expected between operands at operand 2 -- `pmov p15.d'
+.*: Error: operand mismatch -- `pmov z31.d\[10\],p15'
+.*: Info: did you mean this\?
+.*: Info: pmov z31\[10\], p15.b
+.*: Error: operand mismatch -- `pmov z15,p7'
+.*: Info: did you mean this\?
+.*: Info: pmov z15, p7.b
+.*: Error: operand mismatch -- `pmov z8.d,p7.d'
+.*: Info: did you mean this\?
+.*: Info: pmov z8, p7.d
+.*: Error: expected an SVE vector or predicate register at operand 1 -- `pmov w8.d,p7.d'
+.*: Error: expected an SVE vector or predicate register at operand 1 -- `pmov x8.d,p7'
diff --git a/gas/testsuite/gas/aarch64/sve2p1-7-invalid.s b/gas/testsuite/gas/aarch64/sve2p1-7-invalid.s
new file mode 100644
index 00000000000..b83ef36ba8c
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-7-invalid.s
@@ -0,0 +1,76 @@
+/* PMOV (to predicate). */
+pmov p0, z0
+pmov p16.b, z0
+pmov p0.b, z31[1]
+pmov p15.b
+pmov p15, z31.b[4]
+pmov p7, z15.b
+mov p7, w15.b
+mov p7.b, x15
+
+pmov p0, z0[3]
+pmov p16.h, z0
+pmov p0.h, z31[2]
+pmov p15.h
+pmov p15, z31.h[4]
+pmov p7.h, z15.h
+pmov p7.h, x15.h
+pmov p7.h, w15
+
+pmov p0, z0[4]
+pmov p16.s, z0
+pmov p0.s, z31[5]
+pmov p15.s
+pmov p15, z31.s[6]
+pmov p7.s, z15.s
+pmov p7.s, w15.s
+pmov p7.s, x15
+
+pmov p0, z0[8]
+pmov p16.d, z0
+pmov p0.d, z31[10]
+pmov p15.d
+pmov p15, z31.d[12]
+pmov p7.d, z15.d
+pmov p7.d, x15.d
+pmov p7.d, w15
+
+/* PMOV (to vector). */
+pmov z0, p0
+pmov z0, p16.b
+pmov z31[1], p0.b
+pmov p15.b
+pmov z31.b[4], p15
+pmov z15.b, p7.b
+pmov x15.b, p7.b
+pmov w15.b, p7
+
+pmov z0[3], p0
+pmov z0, p16.h
+pmov z31[2], p0.h
+pmov p15.h
+pmov z31.h[5], p15
+pmov z15, p7
+pmov z8.h, p7.h
+pmov x8.h, p7.h
+pmov w8.h, p7
+
+pmov z0[5], p0.s
+pmov z0, p16.s
+pmov z31[6], p0.s
+pmov p15.s
+pmov z31.s[7], p15
+pmov z15, p7
+pmov z8.s, p7.s
+pmov x8.s, p7.s
+pmov w8.s, p7
+
+pmov z0[8], p0.d
+pmov z0, p16.d
+pmov z31[9], p0.d
+pmov p15.d
+pmov z31.d[10], p15
+pmov z15, p7
+pmov z8.d, p7.d
+pmov w8.d, p7.d
+pmov x8.d, p7
diff --git a/gas/testsuite/gas/aarch64/sve2p1-7.d b/gas/testsuite/gas/aarch64/sve2p1-7.d
new file mode 100644
index 00000000000..6bd1a22aaf4
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-7.d
@@ -0,0 +1,64 @@
+#name: Test of SVE2.1 pmov instruction.
+#as: -march=armv9.4-a
+#objdump: -dr
+
+[^:]+: file format .*
+
+
+[^:]+:
+
+[^:]+:
+.*: 052a3800 pmov p0.b, z0
+.*: 052a380f pmov p15.b, z0
+.*: 052a3be0 pmov p0.b, z31
+.*: 052a3bef pmov p15.b, z31
+.*: 052a3bef pmov p15.b, z31
+.*: 052a39e7 pmov p7.b, z15
+.*: 052c3800 pmov p0.h, z0
+.*: 052c380f pmov p15.h, z0
+.*: 052c3be0 pmov p0.h, z31
+.*: 052e3800 pmov p0.h, z0\[1\]
+.*: 052e3bef pmov p15.h, z31\[1\]
+.*: 052c39e7 pmov p7.h, z15
+.*: 052c3903 pmov p3.h, z8
+.*: 05683800 pmov p0.s, z0
+.*: 0568380f pmov p15.s, z0
+.*: 05683be0 pmov p0.s, z31
+.*: 056e3800 pmov p0.s, z0\[3\]
+.*: 056e3bef pmov p15.s, z31\[3\]
+.*: 056a39e7 pmov p7.s, z15\[1\]
+.*: 05683903 pmov p3.s, z8
+.*: 05a83800 pmov p0.d, z0
+.*: 05a8380f pmov p15.d, z0
+.*: 05a83be0 pmov p0.d, z31
+.*: 05ee3800 pmov p0.d, z0\[7\]
+.*: 05ee3bef pmov p15.d, z31\[7\]
+.*: 05ae39e7 pmov p7.d, z15\[3\]
+.*: 05a83903 pmov p3.d, z8
+.*: 052b3800 pmov z0, p0.b
+.*: 052b381f pmov z31, p0.b
+.*: 052b39e0 pmov z0, p15.b
+.*: 052b39ff pmov z31, p15.b
+.*: 052b38e0 pmov z0, p7.b
+.*: 052b38ef pmov z15, p7.b
+.*: 052d3800 pmov z0, p0.h
+.*: 052d381f pmov z31, p0.h
+.*: 052f3800 pmov z0\[1\], p0.h
+.*: 052d39e0 pmov z0, p15.h
+.*: 052f39ff pmov z31\[1\], p15.h
+.*: 052d39ef pmov z15, p15.h
+.*: 052d38e8 pmov z8, p7.h
+.*: 05693800 pmov z0, p0.s
+.*: 0569381f pmov z31, p0.s
+.*: 056f3800 pmov z0\[3\], p0.s
+.*: 056939e0 pmov z0, p15.s
+.*: 056f39ff pmov z31\[3\], p15.s
+.*: 056d39ef pmov z15\[2\], p15.s
+.*: 056938e8 pmov z8, p7.s
+.*: 05a93800 pmov z0, p0.d
+.*: 05a9381f pmov z31, p0.d
+.*: 05ef3800 pmov z0\[7\], p0.d
+.*: 05a939e0 pmov z0, p15.d
+.*: 05ef39ff pmov z31\[7\], p15.d
+.*: 05af39ef pmov z15\[3\], p15.d
+.*: 05a938e8 pmov z8, p7.d
diff --git a/gas/testsuite/gas/aarch64/sve2p1-7.s b/gas/testsuite/gas/aarch64/sve2p1-7.s
new file mode 100644
index 00000000000..3d16548460a
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-7.s
@@ -0,0 +1,63 @@
+/* PMOV (to predicate). */
+pmov p0.b, z0
+pmov p15.b, z0
+pmov p0.b, z31
+pmov p15.b, z31
+pmov p15.b, z31[0]
+pmov p7.b, z15
+
+pmov p0.h, z0[0]
+pmov p15.h, z0[0]
+pmov p0.h, z31[0]
+pmov p0.h, z0[1]
+pmov p15.h, z31[1]
+pmov p7.h, z15[0]
+pmov p3.h, z8
+
+pmov p0.s, z0[0]
+pmov p15.s, z0[0]
+pmov p0.s, z31[0]
+pmov p0.s, z0[3]
+pmov p15.s, z31[3]
+pmov p7.s, z15[1]
+pmov p3.s, z8
+
+pmov p0.d, z0[0]
+pmov p15.d, z0[0]
+pmov p0.d, z31[0]
+pmov p0.d, z0[7]
+pmov p15.d, z31[7]
+pmov p7.d, z15[3]
+pmov p3.d, z8
+
+/* PMOV (to vector). */
+pmov z0, p0.b
+pmov z31, p0.b
+pmov z0, p15.b
+pmov z31, p15.b
+pmov z0[0], p7.b
+pmov z15[0], p7.b
+
+pmov z0[0], p0.h
+pmov z31[0], p0.h
+pmov z0[1], p0.h
+pmov z0[0], p15.h
+pmov z31[1], p15.h
+pmov z15[0], p15.h
+pmov z8, p7.h
+
+pmov z0[0], p0.s
+pmov z31[0], p0.s
+pmov z0[3], p0.s
+pmov z0[0], p15.s
+pmov z31[3], p15.s
+pmov z15[2], p15.s
+pmov z8, p7.s
+
+pmov z0[0], p0.d
+pmov z31[0], p0.d
+pmov z0[7], p0.d
+pmov z0[0], p15.d
+pmov z31[7], p15.d
+pmov z15[3], p15.d
+pmov z8, p7.d
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index dfed0a509b2..fc749fa280d 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -867,6 +867,14 @@ enum aarch64_opnd
AARCH64_OPND_SME_Zn_INDEX3_14, /* Zn[index], bits [9:5] and [16:14]. */
AARCH64_OPND_SME_Zn_INDEX3_15, /* Zn[index], bits [9:5] and [17:15]. */
AARCH64_OPND_SME_Zn_INDEX4_14, /* Zn[index], bits [9:5] and [17:14]. */
+ AARCH64_OPND_SVE_Zn0_INDEX, /* Zn[index], bits [9:5]. */
+ AARCH64_OPND_SVE_Zn1_17_INDEX, /* Zn[index], bits [9:5,17]. */
+ AARCH64_OPND_SVE_Zn2_18_INDEX, /* Zn[index], bits [9:5,18:17]. */
+ AARCH64_OPND_SVE_Zn3_22_INDEX, /* Zn[index], bits [9:5,18:17,22]. */
+ AARCH64_OPND_SVE_Zd0_INDEX, /* Zn[index], bits [4:0]. */
+ AARCH64_OPND_SVE_Zd1_17_INDEX, /* Zn[index], bits [4:0,17]. */
+ AARCH64_OPND_SVE_Zd2_18_INDEX, /* Zn[index], bits [4:0,18:17]. */
+ AARCH64_OPND_SVE_Zd3_22_INDEX, /* Zn[index], bits [4:0,18:17,22]. */
AARCH64_OPND_SME_VLxN_10, /* VLx2 or VLx4, in bit 10. */
AARCH64_OPND_SME_VLxN_13, /* VLx2 or VLx4, in bit 13. */
AARCH64_OPND_SME_ZT0, /* The fixed token zt0/ZT0 (not encoded). */
diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
index 00d10f1e151..bfc2d8027c2 100644
--- a/opcodes/aarch64-asm-2.c
+++ b/opcodes/aarch64-asm-2.c
@@ -687,12 +687,14 @@ aarch64_insert_operand (const aarch64_operand *self,
case 267:
case 268:
case 269:
+ case 303:
+ case 307:
return aarch64_ins_regno (self, info, code, inst, errors);
case 6:
case 119:
case 120:
- case 305:
- case 308:
+ case 313:
+ case 316:
return aarch64_ins_none (self, info, code, inst, errors);
case 17:
return aarch64_ins_reg_extended (self, info, code, inst, errors);
@@ -707,7 +709,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case 37:
case 38:
case 39:
- case 310:
+ case 318:
return aarch64_ins_reglane (self, info, code, inst, errors);
case 40:
case 41:
@@ -734,6 +736,12 @@ aarch64_insert_operand (const aarch64_operand *self,
case 300:
case 301:
case 302:
+ case 304:
+ case 305:
+ case 306:
+ case 308:
+ case 309:
+ case 310:
return aarch64_ins_simple_index (self, info, code, inst, errors);
case 43:
return aarch64_ins_reglist (self, info, code, inst, errors);
@@ -784,13 +792,13 @@ aarch64_insert_operand (const aarch64_operand *self,
case 211:
case 212:
case 272:
- case 303:
- case 304:
- case 306:
- case 307:
- case 309:
+ case 311:
+ case 312:
case 314:
case 315:
+ case 317:
+ case 322:
+ case 323:
return aarch64_ins_imm (self, info, code, inst, errors);
case 52:
case 53:
@@ -1002,16 +1010,16 @@ aarch64_insert_operand (const aarch64_operand *self,
return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
case 284:
return aarch64_ins_plain_shrimm (self, info, code, inst, errors);
- case 311:
- case 312:
- case 313:
- return aarch64_ins_x0_to_x30 (self, info, code, inst, errors);
- case 316:
- case 317:
- case 318:
case 319:
- return aarch64_ins_rcpc3_addr_opt_offset (self, info, code, inst, errors);
case 320:
+ case 321:
+ return aarch64_ins_x0_to_x30 (self, info, code, inst, errors);
+ case 324:
+ case 325:
+ case 326:
+ case 327:
+ return aarch64_ins_rcpc3_addr_opt_offset (self, info, code, inst, errors);
+ case 328:
return aarch64_ins_rcpc3_addr_offset (self, info, code, inst, errors);
default: assert (0); abort ();
}
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index 6458bbca0e8..64407afaca4 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -216,7 +216,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000x000101x00xxxxxxxxxxxxxx
luti4. */
- return 3401;
+ return 3409;
}
else
{
@@ -251,7 +251,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000xx01101xxxxxxxxxxxxxxxxx
luti4. */
- return 3402;
+ return 3410;
}
}
}
@@ -375,7 +375,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000000010x11x1xxxx00xxxxxxxxxx
movt. */
- return 3403;
+ return 3411;
}
}
else
@@ -1157,7 +1157,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000000101xxxxxxxxxxxxxxxx00xxx
fmopa. */
- return 3469;
+ return 3477;
}
else
{
@@ -1165,7 +1165,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000000101xxxxxxxxxxxxxxxx01xxx
fmopa. */
- return 3468;
+ return 3476;
}
}
else
@@ -1513,7 +1513,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010001xxxx1xx0xxxxx1000xxx
fmlall. */
- return 3462;
+ return 3470;
}
}
}
@@ -1543,7 +1543,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010001xxxxxxx1xxxxxx00xxxx
fdot. */
- return 3447;
+ return 3455;
}
}
else
@@ -1915,7 +1915,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011001xxxxxxx0xxxxxx100xxx
fmlall. */
- return 3461;
+ return 3469;
}
}
}
@@ -2020,7 +2020,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011001xxxxxxx1xxxxxx10xxxx
fmlal. */
- return 3454;
+ return 3462;
}
}
}
@@ -2193,7 +2193,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011001xxxxxxx1xxxxxx11xxxx
fmlal. */
- return 3453;
+ return 3461;
}
}
}
@@ -2235,7 +2235,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000010100xxxxxxxxxxxxxxxx0xxx
fmlall. */
- return 3460;
+ return 3468;
}
else
{
@@ -2603,7 +2603,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx000010101xxxx0xx0xxxxxx111xxx
fdot. */
- return 3440;
+ return 3448;
}
else
{
@@ -2672,7 +2672,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx000010101xxxx1xx0xxxxxx001xxx
fdot. */
- return 3441;
+ return 3449;
}
else
{
@@ -2751,7 +2751,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011100xxxxxxx0xxxxxxx0xxxx
fmlal. */
- return 3452;
+ return 3460;
}
else
{
@@ -2806,7 +2806,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011101xxxx0xx01xxxxx00xxxx
fvdotb. */
- return 3471;
+ return 3479;
}
else
{
@@ -2824,7 +2824,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011101xxxxxxx0xxxxxx10xxxx
fdot. */
- return 3446;
+ return 3454;
}
}
}
@@ -2898,7 +2898,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx0000011101xxxxxxx1xxxxxx10xxxx
fvdot. */
- return 3470;
+ return 3478;
}
}
}
@@ -2978,7 +2978,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xx000001110xxxxx0xx01xxxxxx1xxxx
fvdott. */
- return 3472;
+ return 3480;
}
else
{
@@ -3155,7 +3155,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx00xx000xxxx10000x
fmlall. */
- return 3466;
+ return 3474;
}
else
{
@@ -3163,7 +3163,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx10xx000xxxx10000x
fmlall. */
- return 3467;
+ return 3475;
}
}
}
@@ -3218,7 +3218,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx10xxxx0xx000xxxxx00x1x
fmlall. */
- return 3464;
+ return 3472;
}
else
{
@@ -3226,7 +3226,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx000xxxxx00x1x
fmlall. */
- return 3465;
+ return 3473;
}
}
}
@@ -3280,7 +3280,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx00xx100xxxx100xxx
fdot. */
- return 3450;
+ return 3458;
}
else
{
@@ -3288,7 +3288,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx10xx100xxxx100xxx
fdot. */
- return 3451;
+ return 3459;
}
}
}
@@ -3350,7 +3350,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001101xxxx00xx010xxxx1000xx
fmlal. */
- return 3458;
+ return 3466;
}
else
{
@@ -3358,7 +3358,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001101xxxx10xx010xxxx1000xx
fmlal. */
- return 3459;
+ return 3467;
}
}
}
@@ -3413,7 +3413,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx10xxxx0xx010xxxxx001xx
fmlal. */
- return 3456;
+ return 3464;
}
else
{
@@ -3421,7 +3421,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx010xxxxx001xx
fmlal. */
- return 3457;
+ return 3465;
}
}
}
@@ -3490,7 +3490,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx001xxxxx000xx
fmlall. */
- return 3463;
+ return 3471;
}
}
else
@@ -3573,7 +3573,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx011xxxxx00xxx
fmlal. */
- return 3455;
+ return 3463;
}
}
else
@@ -3594,7 +3594,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xx1x00xx111xxxxx00xxx
fadd. */
- return 3404;
+ return 3412;
}
}
else
@@ -3613,7 +3613,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xx1x10xx111xxxxx00xxx
fadd. */
- return 3405;
+ return 3413;
}
}
}
@@ -3739,7 +3739,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx00xx100xxxx110xxx
fdot. */
- return 3444;
+ return 3452;
}
else
{
@@ -3747,7 +3747,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011x1xxxx10xx100xxxx110xxx
fdot. */
- return 3445;
+ return 3453;
}
}
}
@@ -4038,7 +4038,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx10xxxx0xx100xxxxx01xxx
fdot. */
- return 3448;
+ return 3456;
}
else
{
@@ -4046,7 +4046,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx100xxxxx01xxx
fdot. */
- return 3449;
+ return 3457;
}
}
}
@@ -4317,7 +4317,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xx1x00xx111xxxxx01xxx
fsub. */
- return 3406;
+ return 3414;
}
}
else
@@ -4336,7 +4336,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xx1x10xx111xxxxx01xxx
fsub. */
- return 3407;
+ return 3415;
}
}
}
@@ -4398,7 +4398,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx10xxxx0xx100xxxxx11xxx
fdot. */
- return 3442;
+ return 3450;
}
else
{
@@ -4406,7 +4406,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx11xxxx0xx100xxxxx11xxx
fdot. */
- return 3443;
+ return 3451;
}
}
}
@@ -4941,7 +4941,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xxxxx101000xx1x0xxxx0
fscale. */
- return 3378;
+ return 3386;
}
}
else
@@ -5089,7 +5089,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001x0100100111000xxxx0xxxxx
fcvt. */
- return 3375;
+ return 3383;
}
else
{
@@ -5097,7 +5097,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001x1100100111000xxxx0xxxxx
bfcvt. */
- return 3370;
+ return 3378;
}
}
else
@@ -5106,7 +5106,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx110100111000xxxx0xxxxx
fcvt. */
- return 3376;
+ return 3384;
}
}
else
@@ -5157,7 +5157,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xx100111000xxxx1xxxxx
fcvtn. */
- return 3377;
+ return 3385;
}
}
}
@@ -5240,7 +5240,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000010010x110111000xxxxxxxxx0
f1cvt. */
- return 3371;
+ return 3379;
}
else
{
@@ -5248,7 +5248,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011010x110111000xxxxxxxxx0
f2cvt. */
- return 3372;
+ return 3380;
}
}
else
@@ -5259,7 +5259,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000010110x110111000xxxxxxxxx0
bf1cvt. */
- return 3366;
+ return 3374;
}
else
{
@@ -5267,7 +5267,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10000011110x110111000xxxxxxxxx0
bf2cvt. */
- return 3367;
+ return 3375;
}
}
}
@@ -5302,7 +5302,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001001xxx10111000xxxxxxxxx1
f1cvtl. */
- return 3373;
+ return 3381;
}
else
{
@@ -5310,7 +5310,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001101xxx10111000xxxxxxxxx1
f2cvtl. */
- return 3374;
+ return 3382;
}
}
else
@@ -5321,7 +5321,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001011xxx10111000xxxxxxxxx1
bf1cvtl. */
- return 3368;
+ return 3376;
}
else
{
@@ -5329,7 +5329,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001111xxx10111000xxxxxxxxx1
bf2cvtl. */
- return 3369;
+ return 3377;
}
}
}
@@ -5598,7 +5598,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xxxxx1x1100xx100xxxx0
fscale. */
- return 3380;
+ return 3388;
}
}
else
@@ -5774,7 +5774,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xxxxx1x1010xx100xxxx0
fscale. */
- return 3379;
+ return 3387;
}
else
{
@@ -5782,7 +5782,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1000001xx1xxxxx1x1110xx100xxxx0
fscale. */
- return 3381;
+ return 3389;
}
}
}
@@ -10950,7 +10950,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0x11010000xxxxxxx1xxxxxxxxxxxxx
addpt. */
- return 3382;
+ return 3390;
}
else
{
@@ -10958,7 +10958,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1x11010000xxxxxxx1xxxxxxxxxxxxx
subpt. */
- return 3383;
+ return 3391;
}
}
}
@@ -11876,7 +11876,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxx1011x11xxxxx0xxxxxxxxxxxxxxx
maddpt. */
- return 3384;
+ return 3392;
}
else
{
@@ -11884,7 +11884,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxxx1011x11xxxxx1xxxxxxxxxxxxxxx
msubpt. */
- return 3385;
+ return 3393;
}
}
}
@@ -11969,7 +11969,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx000100000xxxxxxxxxxxxx
addpt. */
- return 3386;
+ return 3394;
}
else
{
@@ -12076,7 +12076,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx000101000xxxxxxxxxxxxx
subpt. */
- return 3388;
+ return 3396;
}
else
{
@@ -12281,7 +12281,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx1xxxxx000010xxxxxxxxxx
addpt. */
- return 3387;
+ return 3395;
}
else
{
@@ -12322,7 +12322,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx1xxxxx000011xxxxxxxxxx
subpt. */
- return 3389;
+ return 3397;
}
else
{
@@ -13980,7 +13980,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx110100xxxxxxxxxx
mlapt. */
- return 3391;
+ return 3399;
}
}
else
@@ -14010,7 +14010,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx110110xxxxxxxxxx
madpt. */
- return 3390;
+ return 3398;
}
}
}
@@ -15164,7 +15164,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
110001x0x00xxxxx101xxxxxxxxxxxxx
ld1q. */
- return 3327;
+ return 3335;
}
else
{
@@ -16696,7 +16696,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0x00xxxxx000xxxxxxxxxxxxx
st3q. */
- return 3336;
+ return 3344;
}
else
{
@@ -16706,7 +16706,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0010xxxxx000xxxxxxxxxxxxx
st2q. */
- return 3335;
+ return 3343;
}
else
{
@@ -16714,7 +16714,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0110xxxxx000xxxxxxxxxxxxx
st4q. */
- return 3337;
+ return 3345;
}
}
}
@@ -17380,7 +17380,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x0xx01xxxx111xxxxxxxxxxxxx
ld2q. */
- return 3328;
+ return 3336;
}
}
}
@@ -17516,7 +17516,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
101001x0xx1xxxxx100xxxxxxxxxxxxx
ld2q. */
- return 3331;
+ return 3339;
}
}
else
@@ -17661,7 +17661,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x00x1xxxxx000xxxxxxxxxxxxx
st2q. */
- return 3338;
+ return 3346;
}
}
else
@@ -17704,7 +17704,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0101xxxxx000xxxxxxxxxxxxx
st3q. */
- return 3339;
+ return 3347;
}
}
else
@@ -17745,7 +17745,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0111xxxxx000xxxxxxxxxxxxx
st4q. */
- return 3340;
+ return 3348;
}
}
}
@@ -17774,7 +17774,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0001xxxxx0100x1xxxxxxxxxx
fdot. */
- return 3427;
+ return 3435;
}
}
else
@@ -17783,7 +17783,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0001xxxxx0101xxxxxxxxxxxx
fmlalb. */
- return 3429;
+ return 3437;
}
}
else
@@ -17824,7 +17824,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0101xxxxx0101xxxxxxxxxxxx
fmlalt. */
- return 3439;
+ return 3447;
}
}
else
@@ -17857,7 +17857,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0011xxxxx010xx1xxxxxxxxxx
fdot. */
- return 3425;
+ return 3433;
}
}
else
@@ -17928,7 +17928,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx100010xxxxxxxxxx
fmlallbb. */
- return 3430;
+ return 3438;
}
}
else
@@ -17937,7 +17937,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1000x1xxxxxxxxxx
fdot. */
- return 3426;
+ return 3434;
}
}
else
@@ -17946,7 +17946,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1100xxxxxxxxxxxx
fmlallbb. */
- return 3431;
+ return 3439;
}
}
else
@@ -17955,7 +17955,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1x01xxxxxxxxxxxx
fmlallbt. */
- return 3432;
+ return 3440;
}
}
else
@@ -17982,7 +17982,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0101xxxxx100010xxxxxxxxxx
fmlalb. */
- return 3428;
+ return 3436;
}
}
else
@@ -18000,7 +18000,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0101xxxxx1100xxxxxxxxxxxx
fmlalltb. */
- return 3435;
+ return 3443;
}
}
else
@@ -18009,7 +18009,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0101xxxxx1x01xxxxxxxxxxxx
fmlalt. */
- return 3438;
+ return 3446;
}
}
else
@@ -18042,7 +18042,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0011xxxxx100xx1xxxxxxxxxx
fdot. */
- return 3424;
+ return 3432;
}
}
else
@@ -18051,7 +18051,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0011xxxxx110xxxxxxxxxxxxx
fmlallbt. */
- return 3433;
+ return 3441;
}
}
else
@@ -18083,7 +18083,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
011001x0111xxxxx110xxxxxxxxxxxxx
fmlalltt. */
- return 3437;
+ return 3445;
}
}
else
@@ -18382,7 +18382,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
111001x0xx1xxxxx001xxxxxxxxxxxxx
st1q. */
- return 3334;
+ return 3342;
}
}
else
@@ -18397,7 +18397,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1010xxxxxxxxxxxx
fmlalltb. */
- return 3434;
+ return 3442;
}
else
{
@@ -18405,7 +18405,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x11001x0001xxxxx1011xxxxxxxxxxxx
fmlalltt. */
- return 3436;
+ return 3444;
}
}
else
@@ -19057,11 +19057,11 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 16) & 0x1) == 0)
{
- if (((word >> 17) & 0x1) == 0)
+ if (((word >> 19) & 0x1) == 0)
{
- if (((word >> 18) & 0x1) == 0)
+ if (((word >> 17) & 0x1) == 0)
{
- if (((word >> 19) & 0x1) == 0)
+ if (((word >> 18) & 0x1) == 0)
{
if (((word >> 20) & 0x1) == 0)
{
@@ -19082,59 +19082,147 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 000001x1xx1x1000001110xxxxxxxxxx
- rev. */
- return 1869;
+ if (((word >> 20) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 000001x1xx100100001110xxxxxxxxxx
+ insr. */
+ return 1559;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 000001x1xx110100001110xxxxxxxxxx
+ insr. */
+ return 1560;
+ }
}
}
else
{
- if (((word >> 20) & 0x1) == 0)
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 000001x1xx1x0x10001110xxxxxxxxxx
+ uunpklo. */
+ return 2080;
+ }
+ }
+ else
+ {
+ if (((word >> 20) & 0x1) == 0)
+ {
+ if (((word >> 23) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 000001x1xx10x100001110xxxxxxxxxx
- insr. */
- return 1559;
+ if (((word >> 22) & 0x1) == 0)
+ {
+ if (((word >> 18) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 000001x1001010x0001110xxxxxxxxxx
+ pmov. */
+ return 3327;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 000001x1001011x0001110xxxxxxxxxx
+ pmov. */
+ return 3328;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 000001x101101xx0001110xxxxxxxxxx
+ pmov. */
+ return 3329;
+ }
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- 000001x1xx11x100001110xxxxxxxxxx
- insr. */
- return 1560;
+ 000001x11x101xx0001110xxxxxxxxxx
+ pmov. */
+ return 3330;
}
}
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 000001x1xx1xxx10001110xxxxxxxxxx
- uunpklo. */
- return 2080;
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 000001x1xx111xx0001110xxxxxxxxxx
+ rev. */
+ return 1869;
+ }
}
}
else
{
- if (((word >> 17) & 0x1) == 0)
+ if (((word >> 19) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 000001x1xx1xxx01001110xxxxxxxxxx
- sunpkhi. */
- return 2016;
+ if (((word >> 17) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 000001x1xx1x0x01001110xxxxxxxxxx
+ sunpkhi. */
+ return 2016;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 000001x1xx1x0x11001110xxxxxxxxxx
+ uunpkhi. */
+ return 2079;
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 000001x1xx1xxx11001110xxxxxxxxxx
- uunpkhi. */
- return 2079;
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 22) & 0x1) == 0)
+ {
+ if (((word >> 18) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 000001x1001x10x1001110xxxxxxxxxx
+ pmov. */
+ return 3331;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 000001x1001x11x1001110xxxxxxxxxx
+ pmov. */
+ return 3332;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 000001x1011x1xx1001110xxxxxxxxxx
+ pmov. */
+ return 3333;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 000001x11x1x1xx1001110xxxxxxxxxx
+ pmov. */
+ return 3334;
+ }
}
}
}
@@ -20772,7 +20860,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101100xxxxxxxxxx
luti2. */
- return 3396;
+ return 3404;
}
}
else
@@ -20781,7 +20869,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101x10xxxxxxxxxx
luti2. */
- return 3397;
+ return 3405;
}
}
else
@@ -20794,7 +20882,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x1xx1xxxxx101001xxxxxxxxxx
luti4. */
- return 3398;
+ [...]
[diff truncated at 100000 bytes]