[binutils-gdb] aarch64: Add ite feature system registers.

[SRINATH PARVATHANENI]

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=bde5096397811b8859813afab21dd3e8a5b0082b

commit bde5096397811b8859813afab21dd3e8a5b0082b
Author: srinath <srinath.parvathaneni@arm.com>
Date:   Mon Jan 8 14:08:58 2024 +0000

    aarch64: Add ite feature system registers.
    
    This patch adds ite feature (FEAT_ITE) system registers,
    trcitecr_el1, trcitecr_el12, trcitecr_el2 and trciteedcr.

Diff:
---
 gas/testsuite/gas/aarch64/illegal-ite1-1.l | 8 ++++++++
 gas/testsuite/gas/aarch64/ite1.d           | 8 ++++++++
 gas/testsuite/gas/aarch64/ite1.s           | 9 +++++++++
 opcodes/aarch64-sys-regs.def               | 4 ++++
 4 files changed, 29 insertions(+)

diff --git a/gas/testsuite/gas/aarch64/illegal-ite1-1.l b/gas/testsuite/gas/aarch64/illegal-ite1-1.l
index 1e97c9147ee..9f048180efb 100644
--- a/gas/testsuite/gas/aarch64/illegal-ite1-1.l
+++ b/gas/testsuite/gas/aarch64/illegal-ite1-1.l
@@ -1,2 +1,10 @@
 [^:]*: Assembler messages:
 [^:]*:[0-9]+: Error: selected processor does not support `trcit x1'
+.*: Error: selected processor does not support system register name 'trcitecr_el1'
+.*: Error: selected processor does not support system register name 'trcitecr_el12'
+.*: Error: selected processor does not support system register name 'trcitecr_el2'
+.*: Error: selected processor does not support system register name 'trciteedcr'
+.*: Error: selected processor does not support system register name 'trcitecr_el1'
+.*: Error: selected processor does not support system register name 'trcitecr_el12'
+.*: Error: selected processor does not support system register name 'trcitecr_el2'
+.*: Error: selected processor does not support system register name 'trciteedcr'
diff --git a/gas/testsuite/gas/aarch64/ite1.d b/gas/testsuite/gas/aarch64/ite1.d
index 7c4b486ced8..10ccbdac53b 100644
--- a/gas/testsuite/gas/aarch64/ite1.d
+++ b/gas/testsuite/gas/aarch64/ite1.d
@@ -7,3 +7,11 @@ Disassembly of section \.text:
 
 0+ <.*>:
 .*:	d50b72e1 	trcit	x1
+.*:	d5381261 	mrs	x1, trcitecr_el1
+.*:	d53d1263 	mrs	x3, trcitecr_el12
+.*:	d53c1265 	mrs	x5, trcitecr_el2
+.*:	d5310227 	mrs	x7, trciteedcr
+.*:	d5181261 	msr	trcitecr_el1, x1
+.*:	d51d1263 	msr	trcitecr_el12, x3
+.*:	d51c1265 	msr	trcitecr_el2, x5
+.*:	d5110227 	msr	trciteedcr, x7
diff --git a/gas/testsuite/gas/aarch64/ite1.s b/gas/testsuite/gas/aarch64/ite1.s
index be1cab4da87..77168420ad5 100644
--- a/gas/testsuite/gas/aarch64/ite1.s
+++ b/gas/testsuite/gas/aarch64/ite1.s
@@ -1,3 +1,12 @@
 /* File to test the +ite option.  */
 func:
 	trcit x1
+
+	mrs  x1, trcitecr_el1
+	mrs  x3, trcitecr_el12
+	mrs  x5, trcitecr_el2
+	mrs  x7, trciteedcr
+	msr  trcitecr_el1, x1
+	msr  trcitecr_el12, x3
+	msr  trcitecr_el2, x5
+	msr  trciteedcr, x7
diff --git a/opcodes/aarch64-sys-regs.def b/opcodes/aarch64-sys-regs.def
index b6e3d1a57fa..054c12cb7e5 100644
--- a/opcodes/aarch64-sys-regs.def
+++ b/opcodes/aarch64-sys-regs.def
@@ -984,6 +984,10 @@
   SYSREG ("trcimspec6",		CPENC (2,1,0,6,7),	0,			AARCH64_NO_FEATURES)
   SYSREG ("trcimspec7",		CPENC (2,1,0,7,7),	0,			AARCH64_NO_FEATURES)
   SYSREG ("trcitctrl",		CPENC (2,1,7,0,4),	0,			AARCH64_NO_FEATURES)
+  SYSREG ("trcitecr_el1",	CPENC (3,0,1,2,3),	F_ARCHEXT,		AARCH64_FEATURE (ITE))
+  SYSREG ("trcitecr_el12",	CPENC (3,5,1,2,3),	F_ARCHEXT,		AARCH64_FEATURE (ITE))
+  SYSREG ("trcitecr_el2",	CPENC (3,4,1,2,3),	F_ARCHEXT,		AARCH64_FEATURE (ITE))
+  SYSREG ("trciteedcr",		CPENC (2,1,0,2,1),	F_ARCHEXT,		AARCH64_FEATURE (ITE))
   SYSREG ("trclar",		CPENC (2,1,7,12,6),	F_REG_WRITE,		AARCH64_NO_FEATURES)
   SYSREG ("trclsr",		CPENC (2,1,7,13,6),	F_REG_READ,		AARCH64_NO_FEATURES)
   SYSREG ("trcoslar",		CPENC (2,1,1,0,4),	F_REG_WRITE,		AARCH64_NO_FEATURES)