[binutils-gdb] x86/APX: VROUND{P, S}{S, D} encodings require AVX512{F, VL}

[Jan Beulich]

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=5a635f1f59ad08e572e36419f1145433fd670214

commit 5a635f1f59ad08e572e36419f1145433fd670214
Author: Jan Beulich <jbeulich@suse.com>
Date:   Fri Feb 9 08:38:52 2024 +0100

    x86/APX: VROUND{P,S}{S,D} encodings require AVX512{F,VL}
    
    In eea4357967b6 ("x86/APX: VROUND{P,S}{S,D} can generally be encoded") I
    failed to add the AVX512* ISA dependency of the two new entries.

Diff:
---
 opcodes/i386-opc.tbl | 4 ++--
 opcodes/i386-tbl.h   | 8 ++++----
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 55c704b0159..e79e5ba2fe8 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -1794,8 +1794,8 @@ vroundp<sd>, 0x6608 | <sd:opc>, AVX, Modrm|Vex|Space0F3A|VexWIG|CheckOperandSize
 vrounds<sd>, 0x660a | <sd:opc>, AVX, Modrm|VexLIG|Space0F3A|VexVVVV|VexWIG|NoSuf, { Imm8, <sd:elem>|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
 // These are really clones of VRNDSCALE{P,S}{S,D}, with broadcast, masking, SAE,
 // 512-bit operand size, and register sources dropped.
-vroundp<sd>, 0x6608 | <sd:opc>, APX_F, Modrm|Space0F3A|<sd:vexw>|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM }
-vrounds<sd>, 0x660a | <sd:opc>, APX_F, Modrm|EVexLIG|Space0F3A|VexVVVV|<sd:vexw>|Disp8MemShift|NoSuf, { Imm8, <sd:elem>|Unspecified|BaseIndex, RegXMM, RegXMM }
+vroundp<sd>, 0x6608 | <sd:opc>, APX_F&AVX512VL, Modrm|Space0F3A|<sd:vexw>|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM }
+vrounds<sd>, 0x660a | <sd:opc>, APX_F&AVX512F, Modrm|EVexLIG|Space0F3A|VexVVVV|<sd:vexw>|Disp8MemShift|NoSuf, { Imm8, <sd:elem>|Unspecified|BaseIndex, RegXMM, RegXMM }
 vrsqrtps, 0x52, AVX, Modrm|Vex|Space0F|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
 vrsqrtss, 0xf352, AVX, Modrm|Vex=3|Space0F|VexVVVV|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
 vshufp<sd>, 0x<sd:ppfx>c6, AVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index 4031b6aed05..a1e288bc9b5 100644
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -25296,7 +25296,7 @@ static const insn_template i386_optab[] =
     { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
       0, 0, 0, 0, 0, 1, 1, 0, 0, 5, 0, 0, 0, 0, 7, 0, 0, 0, 0, 0,
       0 },
-    { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0 } },
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
     { { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 	  0, 0, 0, 0, 0, 0 } },
@@ -25320,7 +25320,7 @@ static const insn_template i386_optab[] =
     { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
       0, 0, 0, 0, 0, 2, 1, 0, 0, 5, 0, 0, 0, 0, 7, 0, 0, 0, 0, 0,
       0 },
-    { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0 } },
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
     { { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 	  0, 0, 0, 0, 0, 0 } },
@@ -25346,7 +25346,7 @@ static const insn_template i386_optab[] =
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
       0, 0, 0, 0, 1, 1, 1, 0, 0, 4, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0,
       0 },
-    { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0 } },
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
     { { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 	  0, 0, 0, 0, 0, 0 } },
@@ -25374,7 +25374,7 @@ static const insn_template i386_optab[] =
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
       0, 0, 0, 0, 1, 2, 1, 0, 0, 4, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0,
       0 },
-    { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0 } },
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
     { { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 	  0, 0, 0, 0, 0, 0 } },