[binutils-gdb/riscv-mte] [RFC] RISC-V: Add Zimte extension support
Christoph Mﾃｼllner
cmuellner@sourceware.org
Mon Dec 9 10:39:02 GMT 2024
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=c112fc1330748fb209a6a0d7ea611c9c93851a70
commit c112fc1330748fb209a6a0d7ea611c9c93851a70
Author: Christoph Müllner <christoph.muellner@vrull.eu>
Date: Mon Dec 9 11:36:37 2024 +0100
[RFC] RISC-V: Add Zimte extension support
This patch adds RISC-V Zimte (memory tagging extension) support
based on the specification draft from Dec 2, 2024.
The specification can be found here:
https://github.com/riscv/riscv-memory-tagging
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Diff:
---
bfd/elfxx-riscv.c | 5 +++++
gas/config/tc-riscv.c | 12 ++++++++++++
gas/testsuite/gas/riscv/zimte.d | 14 ++++++++++++++
gas/testsuite/gas/riscv/zimte.s | 5 +++++
gas/testsuite/gas/riscv/zimte_zimop.d | 12 ++++++++++++
gas/testsuite/gas/riscv/zimte_zimop.s | 5 +++++
include/opcode/riscv-opc.h | 14 ++++++++++++++
include/opcode/riscv.h | 5 +++++
opcodes/riscv-dis.c | 4 ++++
opcodes/riscv-opc.c | 6 ++++++
10 files changed, 82 insertions(+)
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index a6511f6558d..480d4015a64 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1353,6 +1353,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{"zihintntl", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zihintpause", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 },
{"zihpm", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 },
+ {"zimte", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zimop", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zmmul", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"za64rs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
@@ -2576,6 +2577,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
|| riscv_subset_supports (rps, "zca")));
case INSN_CLASS_ZIHINTPAUSE:
return riscv_subset_supports (rps, "zihintpause");
+ case INSN_CLASS_ZIMTE:
+ return riscv_subset_supports (rps, "zimte");
case INSN_CLASS_ZIMOP:
return riscv_subset_supports (rps, "zimop");
case INSN_CLASS_M:
@@ -2839,6 +2842,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return _("c' or `zca");
case INSN_CLASS_ZIHINTPAUSE:
return "zihintpause";
+ case INSN_CLASS_ZIMTE:
+ return "zimte";
case INSN_CLASS_ZIMOP:
return "zimop";
case INSN_CLASS_M:
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 3fb7727c250..c0fcc6b5b34 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -1628,6 +1628,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
switch (*++oparg)
{
case 'f': used_bits |= ENCODE_STYPE_IMM (-1U); break;
+ case 't': used_bits |= ENCODE_ZIMTE_IMM (-1U); break;
default:
goto unknown_validate_operand;
}
@@ -3828,6 +3829,17 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
imm_expr->X_op = O_absent;
asarg = expr_parse_end;
continue;
+ case 't': /* Zimte tag. */
+ my_getExpression (imm_expr, asarg);
+ check_absolute_expr (ip, imm_expr, FALSE);
+ if (imm_expr->X_add_number < 0
+ || imm_expr->X_add_number >= 16)
+ as_bad (_("Bad tag immediate, value must be 0..15"));
+ ip->insn_opcode |=
+ ENCODE_ZIMTE_IMM (imm_expr->X_add_number);
+ imm_expr->X_op = O_absent;
+ asarg = expr_parse_end;
+ continue;
default:
goto unknown_riscv_ip_operand;
}
diff --git a/gas/testsuite/gas/riscv/zimte.d b/gas/testsuite/gas/riscv/zimte.d
new file mode 100644
index 00000000000..a5a1b418cb5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zimte.d
@@ -0,0 +1,14 @@
+#as: -march=rv64i_zimte
+#source: zimte.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+0:[ ]+86054073[ ]+gentag[ ]+a0
+[ ]+4:[ ]+86a5c073[ ]+addtag[ ]+a1,0xa
+[ ]+8:[ ]+82564073[ ]+settag[ ]+a2,0x5
+[ ]+c:[ ]+83c6c073[ ]+setinvtag[ ]+a3,0xc
diff --git a/gas/testsuite/gas/riscv/zimte.s b/gas/testsuite/gas/riscv/zimte.s
new file mode 100644
index 00000000000..8fdf0824e40
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zimte.s
@@ -0,0 +1,5 @@
+target:
+ gentag a0
+ addtag a1, 0xa
+ settag a2, 0x5
+ setinvtag a3, 0xc
diff --git a/gas/testsuite/gas/riscv/zimte_zimop.d b/gas/testsuite/gas/riscv/zimte_zimop.d
new file mode 100644
index 00000000000..825e47762f0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zimte_zimop.d
@@ -0,0 +1,12 @@
+#as: -march=rv64i_zimte_zimop
+#source: zimte_zimop.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+0:[ ]+86054073[ ]+gentag[ ]+a0
+[ ]+4:[ ]+86a5c073[ ]+addtag[ ]+a1,0xa
diff --git a/gas/testsuite/gas/riscv/zimte_zimop.s b/gas/testsuite/gas/riscv/zimte_zimop.s
new file mode 100644
index 00000000000..44c2d2d670f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zimte_zimop.s
@@ -0,0 +1,5 @@
+target:
+ # gentag alias:
+ mop.rr.1 x0, a0, x0
+ # addtag alias:
+ mop.rr.1 x0, a1, a0
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 253148b50be..17b73da00cb 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2390,6 +2390,15 @@
#define MASK_C_NTL_S1 0xffff
#define MATCH_C_NTL_ALL 0x9016
#define MASK_C_NTL_ALL 0xffff
+/* Zimte instructions. */
+#define MATCH_GENTAG 0x86004073
+#define MASK_GENTAG 0xfff07fff
+#define MATCH_ADDTAG 0x86004073
+#define MASK_ADDTAG 0xff007fff
+#define MATCH_SETTAG 0x82004073
+#define MASK_SETTAG 0xff007fff
+#define MATCH_SETINVTAG 0x83004073
+#define MASK_SETINVTAG 0xff007fff
/* Zimop instructions. */
#define MATCH_MOP_R_0 0x81c04073
#define MASK_MOP_R_0 0xfff0707f
@@ -4626,6 +4635,11 @@ DECLARE_INSN(c_ntl_p1, MATCH_C_NTL_P1, MASK_C_NTL_P1)
DECLARE_INSN(c_ntl_pall, MATCH_C_NTL_PALL, MASK_C_NTL_PALL)
DECLARE_INSN(c_ntl_s1, MATCH_C_NTL_S1, MASK_C_NTL_S1)
DECLARE_INSN(c_ntl_all, MATCH_C_NTL_ALL, MASK_C_NTL_ALL)
+/* Zimte instructions. */
+DECLARE_INSN(gentag, MATCH_GENTAG, MASK_GENTAG)
+DECLARE_INSN(addtag, MATCH_ADDTAG, MASK_ADDTAG)
+DECLARE_INSN(settag, MATCH_SETTAG, MASK_SETTAG)
+DECLARE_INSN(setinvtag, MATCH_SETINVTAG, MASK_SETINVTAG)
/* Zimop instructions. */
DECLARE_INSN(MOP_R_0, MATCH_MOP_R_0, MASK_MOP_R_0)
DECLARE_INSN(MOP_R_1, MATCH_MOP_R_1, MASK_MOP_R_1)
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index fedfdd24468..27a99d0e470 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -117,6 +117,8 @@ static inline unsigned int riscv_insn_length (insn_t insn)
(RV_X(x, 2, 2) << 4)
#define EXTRACT_ZCMT_INDEX(x) \
(RV_X(x, 2, 8))
+#define EXTRACT_ZIMTE_IMM(x) \
+ (RV_X(x, 20, 4))
/* Vendor-specific (CORE-V) extract macros. */
#define EXTRACT_CV_IS2_UIMM5(x) \
(RV_X(x, 20, 5))
@@ -187,6 +189,8 @@ static inline unsigned int riscv_insn_length (insn_t insn)
(RV_X(x, 4, 2) << 2)
#define ENCODE_ZCMT_INDEX(x) \
(RV_X(x, 0, 8) << 2)
+#define ENCODE_ZIMTE_IMM(x) \
+ (RV_X(x, 0, 4) << 20)
/* Vendor-specific (CORE-V) encode macros. */
#define ENCODE_CV_IS2_UIMM5(x) \
(RV_X(x, 0, 5) << 20)
@@ -469,6 +473,7 @@ enum riscv_insn_class
INSN_CLASS_ZIHINTNTL,
INSN_CLASS_ZIHINTNTL_AND_C,
INSN_CLASS_ZIHINTPAUSE,
+ INSN_CLASS_ZIMTE,
INSN_CLASS_ZIMOP,
INSN_CLASS_ZMMUL,
INSN_CLASS_ZAAMO,
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index c1212b14a05..4294d7ebd6d 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -692,6 +692,10 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
print (info->stream, dis_style_address_offset, "%d",
(int) EXTRACT_STYPE_IMM (l));
break;
+ case 't':
+ print (info->stream, dis_style_immediate, "0x%x",
+ (int) EXTRACT_ZIMTE_IMM (l));
+ break;
default:
goto undefined_modifier;
}
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 200fe26d292..f82eedc4866 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -1150,6 +1150,12 @@ const struct riscv_opcode riscv_opcodes[] =
{"czero.eqz", 0, INSN_CLASS_ZICOND, "d,s,t", MATCH_CZERO_EQZ, MASK_CZERO_EQZ, match_opcode, 0 },
{"czero.nez", 0, INSN_CLASS_ZICOND, "d,s,t", MATCH_CZERO_NEZ, MASK_CZERO_NEZ, match_opcode, 0 },
+/* Zimte instructions. */
+{"gentag", 64, INSN_CLASS_ZIMTE, "s", MATCH_GENTAG, MASK_GENTAG, match_opcode, 0 },
+{"addtag", 64, INSN_CLASS_ZIMTE, "s,Wit", MATCH_ADDTAG, MASK_ADDTAG, match_opcode, 0 },
+{"settag", 64, INSN_CLASS_ZIMTE, "s,Wit", MATCH_SETTAG, MASK_SETTAG, match_opcode, 0 },
+{"setinvtag", 64, INSN_CLASS_ZIMTE, "s,Wit", MATCH_SETINVTAG, MASK_SETINVTAG, match_opcode, 0 },
+
/* Zimop instructions. */
{"mop.r.0", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_0, MASK_MOP_R_0, match_opcode, 0 },
{"mop.r.1", 0, INSN_CLASS_ZIMOP, "d,s", MATCH_MOP_R_1, MASK_MOP_R_1, match_opcode, 0 },
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