[binutils-gdb] RISC-V: Add support for Zcmop extension
Nelson Chu
nelsonc1225@sourceware.org
Tue Aug 6 06:14:36 GMT 2024
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=8a3ffa71945816b941d3dea9ebc7013d5be7a1a4
commit 8a3ffa71945816b941d3dea9ebc7013d5be7a1a4
Author: Xiao Zeng <zengxiao@eswincomputing.com>
Date: Wed Jun 12 09:28:18 2024 +0800
RISC-V: Add support for Zcmop extension
This implements the Zcmop (Compressed Zimop) extension, as of version 1.0.
View detailed information in:
<https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc>
The Zcmop extension requires the Zca extension.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Handle Zcmop.
(riscv_multi_subset_supports_ext): Ditto.
gas/ChangeLog:
* NEWS: Updated.
* testsuite/gas/riscv/march-help.l: Ditto.
* testsuite/gas/riscv/zcmop.d: New test.
* testsuite/gas/riscv/zcmop.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h (DECLARE_INSN): New declarations for Zcmop.
(MATCH_C_MOP_1, MATCH_C_MOP_3, MATCH_C_MOP_5, MATCH_C_MOP_7,
MATCH_C_MOP_9, MATCH_C_MOP_11, MATCH_C_MOP_13, MATCH_C_MOP_15): Define.
(MASK_C_MOP_1, MASK_C_MOP_3, MASK_C_MOP_5, MASK_C_MOP_7,
MASK_C_MOP_9, MASK_C_MOP_11, MASK_C_MOP_13, MASK_C_MOP_15): Ditto.
* opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_ZCMOP.
opcodes/ChangeLog:
* riscv-opc.c: Add Zcmop instructions.
Diff:
---
bfd/elfxx-riscv.c | 6 ++++++
gas/NEWS | 2 +-
gas/testsuite/gas/riscv/imply.d | 1 +
gas/testsuite/gas/riscv/imply.s | 1 +
gas/testsuite/gas/riscv/march-help.l | 1 +
gas/testsuite/gas/riscv/zcmop.d | 16 ++++++++++++++++
gas/testsuite/gas/riscv/zcmop.s | 10 ++++++++++
include/opcode/riscv-opc.h | 26 ++++++++++++++++++++++++++
include/opcode/riscv.h | 1 +
opcodes/riscv-opc.c | 10 ++++++++++
10 files changed, 73 insertions(+), 1 deletion(-)
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 164a11c4cea..eee8114858a 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1213,6 +1213,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
{"zcd", "+d,+zca", check_implicit_always},
{"zcf", "+f,+zca", check_implicit_always},
{"zcmp", "+zca", check_implicit_always},
+ {"zcmop", "+zca", check_implicit_always},
{"shcounterenw", "+h", check_implicit_always},
{"shgatpa", "+h", check_implicit_always},
@@ -1421,6 +1422,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{"zcb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zcf", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zcd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zcmop", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zcmp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{NULL, 0, 0, 0, 0}
};
@@ -2711,6 +2713,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
case INSN_CLASS_ZCB_AND_ZMMUL:
return (riscv_subset_supports (rps, "zcb")
&& riscv_subset_supports (rps, "zmmul"));
+ case INSN_CLASS_ZCMOP:
+ return riscv_subset_supports (rps, "zcmop");
case INSN_CLASS_ZCMP:
return riscv_subset_supports (rps, "zcmp");
case INSN_CLASS_SVINVAL:
@@ -2987,6 +2991,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return _("zcb' and `zbb");
case INSN_CLASS_ZCB_AND_ZMMUL:
return _("zcb' and `zmmul', or `zcb' and `m");
+ case INSN_CLASS_ZCMOP:
+ return "zcmop";
case INSN_CLASS_ZCMP:
return "zcmp";
case INSN_CLASS_SVINVAL:
diff --git a/gas/NEWS b/gas/NEWS
index 96077f8664d..e0484bcd14b 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,6 +1,6 @@
-*- text -*-
-* Add support for RISC-V Zimop extension with version 1.0.
+* Add support for RISC-V Zimop, Zcmop extensions with version 1.0.
Changes in 2.43:
diff --git a/gas/testsuite/gas/riscv/imply.d b/gas/testsuite/gas/riscv/imply.d
index 0c726d3ab79..88b8c46bb89 100644
--- a/gas/testsuite/gas/riscv/imply.d
+++ b/gas/testsuite/gas/riscv/imply.d
@@ -44,6 +44,7 @@ SYMBOL TABLE:
[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_d2p2_zicsr2p0_zca1p0_zcd1p0
[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_zicsr2p0_zca1p0_zcf1p0
[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zca1p0_zcmp1p0
+[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zca1p0_zcmop1p0
[0-9a-f]+ l .text 0+000 \$xrv32i2p1_h1p0_zicsr2p0_shcounterenw1p0
[0-9a-f]+ l .text 0+000 \$xrv32i2p1_h1p0_zicsr2p0_shgatpa1p0
[0-9a-f]+ l .text 0+000 \$xrv32i2p1_h1p0_zicsr2p0_shtvala1p0
diff --git a/gas/testsuite/gas/riscv/imply.s b/gas/testsuite/gas/riscv/imply.s
index 8eca66f7a89..dabb08d8c8b 100644
--- a/gas/testsuite/gas/riscv/imply.s
+++ b/gas/testsuite/gas/riscv/imply.s
@@ -47,6 +47,7 @@ imply zcb
imply zcd
imply zcf
imply zcmp
+imply zcmop
imply shcounterenw
imply shgatpa
diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l
index cb8590a37a8..054c2e9667d 100644
--- a/gas/testsuite/gas/riscv/march-help.l
+++ b/gas/testsuite/gas/riscv/march-help.l
@@ -102,6 +102,7 @@ All available -march extensions for RISC-V:
zcb 1.0
zcf 1.0
zcd 1.0
+ zcmop 1.0
zcmp 1.0
shcounterenw 1.0
shgatpa 1.0
diff --git a/gas/testsuite/gas/riscv/zcmop.d b/gas/testsuite/gas/riscv/zcmop.d
new file mode 100644
index 00000000000..5f608c676c3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zcmop.d
@@ -0,0 +1,16 @@
+#as: -march=rv64i_zcmop
+#objdump: -d
+
+.*:[ ]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+6081[ ]+c.mop.1
+[ ]+[0-9a-f]+:[ ]+6181[ ]+c.mop.3
+[ ]+[0-9a-f]+:[ ]+6281[ ]+c.mop.5
+[ ]+[0-9a-f]+:[ ]+6381[ ]+c.mop.7
+[ ]+[0-9a-f]+:[ ]+6481[ ]+c.mop.9
+[ ]+[0-9a-f]+:[ ]+6581[ ]+c.mop.11
+[ ]+[0-9a-f]+:[ ]+6681[ ]+c.mop.13
+[ ]+[0-9a-f]+:[ ]+6781[ ]+c.mop.15
diff --git a/gas/testsuite/gas/riscv/zcmop.s b/gas/testsuite/gas/riscv/zcmop.s
new file mode 100644
index 00000000000..4b02e694f46
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zcmop.s
@@ -0,0 +1,10 @@
+target:
+ # c.mop.n
+ c.mop.1
+ c.mop.3
+ c.mop.5
+ c.mop.7
+ c.mop.9
+ c.mop.11
+ c.mop.13
+ c.mop.15
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 9ef9c6f7b9f..22e63baf2e3 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2275,6 +2275,23 @@
#define MASK_C_NOT 0xfc7f
#define MATCH_C_MUL 0x9c41
#define MASK_C_MUL 0xfc63
+/* Zcmop instructions. */
+#define MATCH_C_MOP_1 0x6081
+#define MASK_C_MOP_1 0xffff
+#define MATCH_C_MOP_3 0x6181
+#define MASK_C_MOP_3 0xffff
+#define MATCH_C_MOP_5 0x6281
+#define MASK_C_MOP_5 0xffff
+#define MATCH_C_MOP_7 0x6381
+#define MASK_C_MOP_7 0xffff
+#define MATCH_C_MOP_9 0x6481
+#define MASK_C_MOP_9 0xffff
+#define MATCH_C_MOP_11 0x6581
+#define MASK_C_MOP_11 0xffff
+#define MATCH_C_MOP_13 0x6681
+#define MASK_C_MOP_13 0xffff
+#define MATCH_C_MOP_15 0x6781
+#define MASK_C_MOP_15 0xffff
/* Zcmp instructions. */
#define MATCH_CM_PUSH 0xb802
#define MASK_CM_PUSH 0xff03
@@ -4213,6 +4230,15 @@ DECLARE_INSN(c_lhu, MATCH_C_LHU, MASK_C_LHU)
DECLARE_INSN(c_lh, MATCH_C_LH, MASK_C_LH)
DECLARE_INSN(c_sb, MATCH_C_SB, MASK_C_SB)
DECLARE_INSN(c_sh, MATCH_C_SH, MASK_C_SH)
+/* Zcmop instructions. */
+DECLARE_INSN(c_mop_1, MATCH_C_MOP_1, MASK_C_MOP_1)
+DECLARE_INSN(c_mop_3, MATCH_C_MOP_3, MASK_C_MOP_3)
+DECLARE_INSN(c_mop_5, MATCH_C_MOP_5, MASK_C_MOP_5)
+DECLARE_INSN(c_mop_7, MATCH_C_MOP_7, MASK_C_MOP_7)
+DECLARE_INSN(c_mop_9, MATCH_C_MOP_9, MASK_C_MOP_9)
+DECLARE_INSN(c_mop_11, MATCH_C_MOP_11, MASK_C_MOP_11)
+DECLARE_INSN(c_mop_13, MATCH_C_MOP_13, MASK_C_MOP_13)
+DECLARE_INSN(c_mop_15, MATCH_C_MOP_15, MASK_C_MOP_15)
/* Zcmp instructions. */
DECLARE_INSN(cm_push, MATCH_CM_PUSH, MASK_CM_PUSH)
DECLARE_INSN(cm_pop, MATCH_CM_POP, MASK_CM_POP)
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 6793d99ce8e..9ccf0ec2454 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -487,6 +487,7 @@ enum riscv_insn_class
INSN_CLASS_ZCB_AND_ZBA,
INSN_CLASS_ZCB_AND_ZBB,
INSN_CLASS_ZCB_AND_ZMMUL,
+ INSN_CLASS_ZCMOP,
INSN_CLASS_ZCMP,
INSN_CLASS_SVINVAL,
INSN_CLASS_ZICBOM,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 7e326273491..e6831bda9fd 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2171,6 +2171,16 @@ const struct riscv_opcode riscv_opcodes[] =
{"c.zext.b", 0, INSN_CLASS_ZCB, "Cs", MATCH_C_ZEXT_B, MASK_C_ZEXT_B, match_opcode, 0 },
{"c.sext.w", 64, INSN_CLASS_ZCB, "d", MATCH_C_ADDIW, MASK_C_ADDIW|MASK_RVC_IMM, match_rd_nonzero, INSN_ALIAS },
+/* Zcmop instructions. */
+{"c.mop.1", 0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_1, MASK_C_MOP_1, match_opcode, 0 },
+{"c.mop.3", 0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_3, MASK_C_MOP_3, match_opcode, 0 },
+{"c.mop.5", 0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_5, MASK_C_MOP_5, match_opcode, 0 },
+{"c.mop.7", 0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_7, MASK_C_MOP_7, match_opcode, 0 },
+{"c.mop.9", 0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_9, MASK_C_MOP_9, match_opcode, 0 },
+{"c.mop.11", 0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_11, MASK_C_MOP_11, match_opcode, 0 },
+{"c.mop.13", 0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_13, MASK_C_MOP_13, match_opcode, 0 },
+{"c.mop.15", 0, INSN_CLASS_ZCMOP, "", MATCH_C_MOP_15, MASK_C_MOP_15, match_opcode, 0 },
+
/* Zcmp instructions. */
{"cm.push", 0, INSN_CLASS_ZCMP, "{Wcr},Wcp", MATCH_CM_PUSH, MASK_CM_PUSH, match_opcode, 0 },
{"cm.pop", 0, INSN_CLASS_ZCMP, "{Wcr},Wcp", MATCH_CM_POP, MASK_CM_POP, match_opcode, 0 },
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