[binutils-gdb] x86: fold certain VEX and EVEX templates
Jan Beulich
jbeulich@sourceware.org
Wed Sep 27 12:16:27 GMT 2023
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=a6f3add0027e42f78b2f1366a7b4cdee418987ce
commit a6f3add0027e42f78b2f1366a7b4cdee418987ce
Author: Jan Beulich <jbeulich@suse.com>
Date: Wed Sep 27 14:15:19 2023 +0200
x86: fold certain VEX and EVEX templates
In anticipation of APX introduce logic to reduce the number of templates
we have now, allowing to limit some the number of ones we then need to
gain.
The fundamental requirements are that
- attributes be compatible, which specifically means VexW needs to be
the same in the templates (which often isn't the case, for VEX
encodings having far more WIG tha, EVEX ones),
- the EVEX form being AVX512F (with or without AVX512VL), not any of its
extensions (the same will then be required for APX - it'll need to be
APX_F).
Note that in check_register() there's now a redundant zmm check. Since
this logic will need revisiting for APX anyway, I'd like to keep it that
way for now. (Similarly a couple of if()-s which could be folded are
kept separate, to reduce code churn when adding APX support.)
Diff:
---
gas/config/tc-i386-intel.c | 5 +
gas/config/tc-i386.c | 102 ++-
opcodes/i386-opc.tbl | 114 ++--
opcodes/i386-tbl.h | 1576 +++++++++++++++++---------------------------
4 files changed, 764 insertions(+), 1033 deletions(-)
diff --git a/gas/config/tc-i386-intel.c b/gas/config/tc-i386-intel.c
index 68bf6150181..f1d995f028a 100644
--- a/gas/config/tc-i386-intel.c
+++ b/gas/config/tc-i386-intel.c
@@ -209,6 +209,11 @@ operatorT i386_operator (const char *name, unsigned int operands, char *pc)
|| i386_types[j].sz[0] > 8
|| (i386_types[j].sz[0] & (i386_types[j].sz[0] - 1)))
return O_illegal;
+ if (i.vec_encoding == vex_encoding_default)
+ i.vec_encoding = vex_encoding_evex;
+ else if (i.vec_encoding != vex_encoding_evex
+ && i.vec_encoding != vex_encoding_evex512)
+ return O_illegal;
if (!i.broadcast.bytes && !i.broadcast.type)
{
i.broadcast.bytes = i386_types[j].sz[0];
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 5df9fde2b29..8e5a16ee4b5 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -436,6 +436,7 @@ struct _i386_insn
vex_encoding_vex,
vex_encoding_vex3,
vex_encoding_evex,
+ vex_encoding_evex512,
vex_encoding_error
} vec_encoding;
@@ -1872,6 +1873,13 @@ cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS;
+static INLINE bool need_evex_encoding (void)
+{
+ return i.vec_encoding == vex_encoding_evex
+ || i.vec_encoding == vex_encoding_evex512
+ || i.mask.reg;
+}
+
#define CPU_FLAGS_ARCH_MATCH 0x1
#define CPU_FLAGS_64BIT_MATCH 0x2
@@ -1899,6 +1907,29 @@ cpu_flags_match (const insn_template *t)
/* This instruction is available only on some archs. */
i386_cpu_flags cpu = cpu_arch_flags;
+ /* Dual VEX/EVEX templates may need stripping of one of the flags. */
+ if (t->opcode_modifier.vex && t->opcode_modifier.evex)
+ {
+ /* Dual AVX/AVX512F templates need to retain AVX512F only if we already
+ know that EVEX encoding will be needed. */
+ if ((x.bitfield.cpuavx || x.bitfield.cpuavx2)
+ && x.bitfield.cpuavx512f)
+ {
+ if (need_evex_encoding ())
+ {
+ x.bitfield.cpuavx = 0;
+ x.bitfield.cpuavx2 = 0;
+ }
+ /* need_evex_encoding() isn't reliable before operands were
+ parsed. */
+ else if (i.operands)
+ {
+ x.bitfield.cpuavx512f = 0;
+ x.bitfield.cpuavx512vl = 0;
+ }
+ }
+ }
+
/* AVX512VL is no standalone feature - match it and then strip it. */
if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl)
return match;
@@ -1924,6 +1955,8 @@ cpu_flags_match (const insn_template *t)
&& (!x.bitfield.cpupclmulqdq || cpu.bitfield.cpupclmulqdq))
match |= CPU_FLAGS_ARCH_MATCH;
}
+ else if (x.bitfield.cpuavx2 && cpu.bitfield.cpuavx2)
+ match |= CPU_FLAGS_ARCH_MATCH;
else if (x.bitfield.cpuavx512f)
{
/* We need to check a few extra flags with AVX512F. */
@@ -3646,6 +3679,27 @@ install_template (const insn_template *t)
i.tm = *t;
+ /* Dual VEX/EVEX templates need stripping one of the possible variants. */
+ if (t->opcode_modifier.vex && t->opcode_modifier.evex)
+ {
+ if ((is_cpu (t, CpuAVX) || is_cpu (t, CpuAVX2))
+ && is_cpu (t, CpuAVX512F))
+ {
+ if (need_evex_encoding ())
+ {
+ i.tm.opcode_modifier.vex = 0;
+ i.tm.cpu.bitfield.cpuavx = 0;
+ if (is_cpu (&i.tm, CpuAVX2))
+ i.tm.cpu.bitfield.isa = 0;
+ }
+ else
+ {
+ i.tm.opcode_modifier.evex = 0;
+ i.tm.cpu.bitfield.cpuavx512f = 0;
+ }
+ }
+ }
+
/* Note that for pseudo prefixes this produces a length of 1. But for them
the length isn't interesting at all. */
for (l = 1; l < 4; ++l)
@@ -4553,6 +4607,8 @@ optimize_encoding (void)
i.tm.opcode_modifier.vex = VEX128;
i.tm.opcode_modifier.vexw = VEXW0;
i.tm.opcode_modifier.evex = 0;
+ i.vec_encoding = vex_encoding_vex;
+ i.mask.reg = NULL;
}
else if (optimize > 1)
i.tm.opcode_modifier.evex = EVEX128;
@@ -5438,6 +5494,11 @@ md_assemble (char *line)
if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize)
optimize_encoding ();
+ /* Past optimization there's no need to distinguish vex_encoding_evex and
+ vex_encoding_evex512 anymore. */
+ if (i.vec_encoding == vex_encoding_evex512)
+ i.vec_encoding = vex_encoding_evex;
+
if (use_unaligned_vector_move)
encode_with_unaligned_vector_move ();
@@ -5467,6 +5528,7 @@ md_assemble (char *line)
if (i.tm.operand_types[j].bitfield.tmmword)
i.xstate |= xstate_tmm;
else if (i.tm.operand_types[j].bitfield.zmmword
+ && !i.tm.opcode_modifier.vex
&& vector_size >= VSZ512)
i.xstate |= xstate_zmm;
else if (i.tm.operand_types[j].bitfield.ymmword
@@ -6474,7 +6536,8 @@ check_VecOperands (const insn_template *t)
cpu = cpu_flags_and (cpu_flags_from_attr (t->cpu), avx512);
if (!cpu_flags_all_zero (&cpu)
&& !is_cpu (t, CpuAVX512VL)
- && !cpu_arch_flags.bitfield.cpuavx512vl)
+ && !cpu_arch_flags.bitfield.cpuavx512vl
+ && (!t->opcode_modifier.vex || need_evex_encoding ()))
{
for (op = 0; op < t->operands; ++op)
{
@@ -6785,6 +6848,8 @@ check_VecOperands (const insn_template *t)
/* Check vector Disp8 operand. */
if (t->opcode_modifier.disp8memshift
+ && (!t->opcode_modifier.vex
+ || need_evex_encoding ())
&& i.disp_encoding <= disp_encoding_8bit)
{
if (i.broadcast.type || i.broadcast.bytes)
@@ -6880,7 +6945,8 @@ VEX_check_encoding (const insn_template *t)
return 1;
}
- if (i.vec_encoding == vex_encoding_evex)
+ if (i.vec_encoding == vex_encoding_evex
+ || i.vec_encoding == vex_encoding_evex512)
{
/* This instruction must be encoded with EVEX prefix. */
if (!is_evex_encoding (t))
@@ -11219,6 +11285,10 @@ s_insn (int dummy ATTRIBUTE_UNUSED)
goto done;
}
+ /* No need to distinguish vex_encoding_evex and vex_encoding_evex512. */
+ if (i.vec_encoding == vex_encoding_evex512)
+ i.vec_encoding = vex_encoding_evex;
+
/* Are we to emit ModR/M encoding? */
if (!i.short_form
&& (i.mem_operands
@@ -11642,6 +11712,12 @@ RC_SAE_specifier (const char *pstr)
return NULL;
}
+ if (i.vec_encoding == vex_encoding_default)
+ i.vec_encoding = vex_encoding_evex512;
+ else if (i.vec_encoding != vex_encoding_evex
+ && i.vec_encoding != vex_encoding_evex512)
+ return NULL;
+
i.rounding.type = RC_NamesTable[j].type;
return (char *)(pstr + RC_NamesTable[j].len);
@@ -11701,6 +11777,12 @@ check_VecOperations (char *op_string)
}
op_string++;
+ if (i.vec_encoding == vex_encoding_default)
+ i.vec_encoding = vex_encoding_evex;
+ else if (i.vec_encoding != vex_encoding_evex
+ && i.vec_encoding != vex_encoding_evex512)
+ goto unknown_vec_op;
+
i.broadcast.type = bcst_type;
i.broadcast.operand = this_operand;
@@ -13962,8 +14044,17 @@ static bool check_register (const reg_entry *r)
}
}
- if (vector_size < VSZ512 && r->reg_type.bitfield.zmmword)
- return false;
+ if (r->reg_type.bitfield.zmmword)
+ {
+ if (vector_size < VSZ512)
+ return false;
+
+ if (i.vec_encoding == vex_encoding_default)
+ i.vec_encoding = vex_encoding_evex512;
+ else if (i.vec_encoding != vex_encoding_evex
+ && i.vec_encoding != vex_encoding_evex512)
+ i.vec_encoding = vex_encoding_error;
+ }
if (vector_size < VSZ256 && r->reg_type.bitfield.ymmword)
return false;
@@ -13988,7 +14079,8 @@ static bool check_register (const reg_entry *r)
|| flag_code != CODE_64BIT)
return false;
- if (i.vec_encoding == vex_encoding_default)
+ if (i.vec_encoding == vex_encoding_default
+ || i.vec_encoding == vex_encoding_evex512)
i.vec_encoding = vex_encoding_evex;
else if (i.vec_encoding != vex_encoding_evex)
i.vec_encoding = vex_encoding_error;
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index a534c53ca17..63cc1ab15ad 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -131,6 +131,8 @@
#define EVexLIG EVex=EVEXLIG
#define EVexDYN EVex=EVEXDYN
+#define Disp8ShiftVL Disp8MemShift=DISP8_SHIFT_VL
+
#define Vsz256 Vsz=VSZ256
#define Vsz512 Vsz=VSZ512
@@ -1518,8 +1520,8 @@ vdivs<sd>, 0x<sd:spfx>5e, AVX, Modrm|VexLIG|Space0F|VexVVVV|VexWIG|NoSuf, { <sd:
vdppd, 0x6641, AVX, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vdpps, 0x6640, AVX, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vextractf128, 0x6619, AVX, Modrm|Vex=2|Space0F3A|VexW=1|NoSuf, { Imm8, RegYMM, Unspecified|BaseIndex|RegXMM }
-vextractps, 0x6617, AVX, Modrm|Vex|Space0F3A|VexWIG|NoSuf, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex }
-vextractps, 0x6617, AVX|x64, RegMem|Vex|Space0F3A|VexWIG|NoSuf, { Imm8, RegXMM, Reg64 }
+vextractps, 0x6617, AVX|AVX512F, Modrm|Vex128|EVex128|Space0F3A|VexWIG|Disp8MemShift=2|NoSuf, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex }
+vextractps, 0x6617, AVX|AVX512F|x64, RegMem|Vex128|EVex128|Space0F3A|VexWIG|NoSuf, { Imm8, RegXMM, Reg64 }
vhaddpd, 0x667c, AVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vhaddps, 0xf27c, AVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vhsubpd, 0x667d, AVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
@@ -1541,7 +1543,7 @@ vmovap<sd>, 0x<sd:ppfx>28, AVX, D|Modrm|Vex|Space0F|VexWIG|CheckOperandSize|NoSu
// by Intel AVX spec). To avoid extra template in gcc x86 backend and
// support assembler for AMD64, we accept 64bit operand on vmovd so
// that we can use one template for both SSE and AVX instructions.
-vmovd, 0x666e, AVX, D|Modrm|Vex=1|Space0F|NoSuf, { Reg32|Unspecified|BaseIndex, RegXMM }
+vmovd, 0x666e, AVX|AVX512F, D|Modrm|Vex128|EVex128|Space0F|Disp8MemShift=2|NoSuf, { Reg32|Unspecified|BaseIndex, RegXMM }
vmovd, 0x667e, AVX|x64, D|RegMem|Vex=1|Space0F|VexW=2|NoSuf|Size64, { RegXMM, Reg64 }
vmovddup, 0xf212, AVX, Modrm|Vex|Space0F|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
vmovddup, 0xf212, AVX, Modrm|Vex=2|Space0F|VexWIG|NoSuf, { Unspecified|BaseIndex|RegYMM, RegYMM }
@@ -1559,7 +1561,7 @@ vmovntdqa, 0x662a, AVX|AVX2, Modrm|Vex|Space0F38|VexWIG|CheckOperandSize|NoSuf,
vmovntp<sd>, 0x<sd:ppfx>2b, AVX, Modrm|Vex|Space0F|VexWIG|CheckOperandSize|NoSuf, { RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex }
vmovq, 0xf37e, AVX, Load|Modrm|Vex=1|Space0F|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
vmovq, 0x66d6, AVX, Modrm|Vex=1|Space0F|VexWIG|NoSuf, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM }
-vmovq, 0x666e, AVX|x64, D|Modrm|Vex=1|Space0F|VexW=2|NoSuf, { Reg64|Unspecified|BaseIndex, RegXMM }
+vmovq, 0x666e, AVX|AVX512F|x64, D|Modrm|Vex128|EVex128|Space0F|VexW1|Disp8MemShift=3|NoSuf, { Reg64|Unspecified|BaseIndex, RegXMM }
vmovs<sd>, 0x<sd:spfx>10, AVX, D|Modrm|VexLIG|Space0F|VexWIG|NoSuf, { <sd:elem>|Unspecified|BaseIndex, RegXMM }
vmovs<sd>, 0x<sd:spfx>10, AVX, D|Modrm|VexLIG|Space0F|VexVVVV|VexWIG|NoSuf, { RegXMM, RegXMM, RegXMM }
vmovshdup, 0xf316, AVX, Modrm|Vex|Space0F|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
@@ -1599,8 +1601,10 @@ vpcmpgtq, 0x6637, AVX|AVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckOperandSize|
vpcmpistri, 0x6663, AVX, Modrm|Vex|Space0F3A|VexWIG|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM }
vpcmpistrm, 0x6662, AVX, Modrm|Vex|Space0F3A|VexWIG|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegXMM }
vperm2f128, 0x6606, AVX, Modrm|Vex256|Space0F3A|VexVVVV|VexW0|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
-vpermilp<sd>, 0x660c | <sd:opc>, AVX, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vpermilp<sd>, 0x6604 | <sd:opc>, AVX, Modrm|Vex|Space0F3A|VexW0|CheckOperandSize|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
+vpermilps, 0x660c, AVX|AVX512F, Modrm|Vex|EVexDYN|Masking|Space0F38|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
+vpermilps, 0x6604, AVX|AVX512F, Modrm|Vex|EVexDYN|Masking|Space0F3A|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
+vpermilpd, 0x660d, AVX, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
+vpermilpd, 0x6605, AVX, Modrm|Vex|Space0F3A|VexW0|CheckOperandSize|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
vpextr<dq>, 0x6616, AVX|<dq:cpu64>, Modrm|Vex|Space0F3A|<dq:vexw64>|NoSuf, { Imm8, RegXMM, <dq:gpr>|Unspecified|BaseIndex }
vpextrw, 0x66c5, AVX, Load|Modrm|Vex|Space0F|VexWIG|No_bSuf|No_wSuf|No_sSuf, { Imm8, RegXMM, Reg32|Reg64 }
vpextr<bw>, 0x6614 | <bw:opc>, AVX, RegMem|Vex|Space0F3A|VexWIG|NoSuf, { Imm8, RegXMM, Reg32|Reg64 }
@@ -1632,18 +1636,18 @@ vpminub, 0x66da, AVX|AVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckOperandSize|N
vpminud, 0x663b, AVX|AVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vpminuw, 0x663a, AVX|AVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vpmovmskb, 0x66d7, AVX|AVX2, Modrm|Vex|Space0F|VexWIG|No_bSuf|No_wSuf|No_sSuf, { RegXMM|RegYMM, Reg32|Reg64 }
-vpmovsxbd, 0x6621, AVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
-vpmovsxbq, 0x6622, AVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Word|Unspecified|BaseIndex|RegXMM, RegXMM }
+vpmovsxbd, 0x6621, AVX|AVX512F|AVX512VL, Modrm|Vex128|EVex128|Masking|Space0F38|VexWIG|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM }
+vpmovsxbq, 0x6622, AVX|AVX512F|AVX512VL, Modrm|Vex128|EVex128|Masking|Space0F38|VexWIG|Disp8MemShift=1|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegXMM }
vpmovsxbw, 0x6620, AVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
vpmovsxdq, 0x6625, AVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
-vpmovsxwd, 0x6623, AVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
-vpmovsxwq, 0x6624, AVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
-vpmovzxbd, 0x6631, AVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
-vpmovzxbq, 0x6632, AVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Word|Unspecified|BaseIndex|RegXMM, RegXMM }
+vpmovsxwd, 0x6623, AVX|AVX512F|AVX512VL, Modrm|Vex128|EVex128|Masking|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM }
+vpmovsxwq, 0x6624, AVX|AVX512F|AVX512VL, Modrm|Vex128|EVex128|Masking|Space0F38|VexWIG|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM }
+vpmovzxbd, 0x6631, AVX|AVX512F|AVX512VL, Modrm|Vex128|EVex128|Masking|Space0F38|VexWIG|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM }
+vpmovzxbq, 0x6632, AVX|AVX512F|AVX512VL, Modrm|Vex128|EVex128|Masking|Space0F38|VexWIG|Disp8MemShift=1|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegXMM }
vpmovzxbw, 0x6630, AVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
vpmovzxdq, 0x6635, AVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
-vpmovzxwd, 0x6633, AVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
-vpmovzxwq, 0x6634, AVX, Modrm|Vex|Space0F38|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
+vpmovzxwd, 0x6633, AVX|AVX512F|AVX512VL, Modrm|Vex128|EVex128|Masking|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM }
+vpmovzxwq, 0x6634, AVX|AVX512F|AVX512VL, Modrm|Vex128|EVex128|Masking|Space0F38|VexWIG|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM }
vpmuldq, 0x6628, AVX|AVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vpmulhrsw, 0x660b, AVX|AVX2, Modrm|Vex|Space0F38|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vpmulhuw, 0x66e4, AVX|AVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
@@ -1710,39 +1714,40 @@ vzeroupper, 0x77, AVX, Vex|Space0F|VexWIG|NoSuf, {}
// 256bit integer AVX2 instructions.
-vpmovsxbd, 0x6621, AVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegYMM }
-vpmovsxbq, 0x6622, AVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegYMM }
+vpmovsxbd, 0x6621, AVX2|AVX512F|AVX512VL, Modrm|Vex256|EVex256|Masking|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM }
+vpmovsxbq, 0x6622, AVX2|AVX512F|AVX512VL, Modrm|Vex256|EVex256|Masking|Space0F38|VexWIG|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM }
vpmovsxbw, 0x6620, AVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegYMM }
vpmovsxdq, 0x6625, AVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegYMM }
-vpmovsxwd, 0x6623, AVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegYMM }
-vpmovsxwq, 0x6624, AVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegYMM }
-vpmovzxbd, 0x6631, AVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegYMM }
-vpmovzxbq, 0x6632, AVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegYMM }
+vpmovsxwd, 0x6623, AVX2|AVX512F|AVX512VL, Modrm|Vex256|EVex256|Masking|Space0F38|VexWIG|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM }
+vpmovsxwq, 0x6624, AVX2|AVX512F|AVX512VL, Modrm|Vex256|EVex256|Masking|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM }
+vpmovzxbd, 0x6631, AVX2|AVX512F|AVX512VL, Modrm|Vex256|EVex256|Masking|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM }
+vpmovzxbq, 0x6632, AVX2|AVX512F|AVX512VL, Modrm|Vex256|EVex256|Masking|Space0F38|VexWIG|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM }
vpmovzxbw, 0x6630, AVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegYMM }
vpmovzxdq, 0x6635, AVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegYMM }
-vpmovzxwd, 0x6633, AVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Unspecified|BaseIndex|RegXMM, RegYMM }
-vpmovzxwq, 0x6634, AVX2, Modrm|Vex=2|Space0F38|VexWIG|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegYMM }
+vpmovzxwd, 0x6633, AVX2|AVX512F|AVX512VL, Modrm|Vex256|EVex256|Masking|Space0F38|VexWIG|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM }
+vpmovzxwq, 0x6634, AVX2|AVX512F|AVX512VL, Modrm|Vex256|EVex256|Masking|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM }
// New AVX2 instructions.
vbroadcasti128, 0x665A, AVX2, Modrm|Vex=2|Space0F38|VexW=1|NoSuf, { Xmmword|Unspecified|BaseIndex, RegYMM }
vbroadcastsd, 0x6619, AVX2, Modrm|Vex=2|Space0F38|VexW=1|NoSuf, { RegXMM, RegYMM }
-vbroadcastss, 0x6618, AVX2, Modrm|Vex|Space0F38|VexW=1|NoSuf, { RegXMM, RegXMM|RegYMM }
+vbroadcastss, 0x6618, AVX2|AVX512F, Modrm|Vex|EVexDYN|Masking|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
vpblendd, 0x6602, AVX2, Modrm|Vex|Space0F3A|VexVVVV|VexW0|CheckOperandSize|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vpbroadcast<bw>, 0x6678 | <bw:opc>, AVX2, Modrm|Vex|Space0F38|VexW0|NoSuf, { <bw:elem>|Unspecified|BaseIndex|RegXMM, RegXMM|RegYMM }
-vpbroadcast<dq>, 0x6658 | <dq:opc>, AVX2, Modrm|Vex|Space0F38|VexW0|NoSuf|Optimize, { <dq:elem>|Unspecified|BaseIndex|RegXMM, RegXMM|RegYMM }
+vpbroadcastd, 0x6658, AVX2|AVX512F, Modrm|Vex|EVexDYN|Masking|Space0F38|VexW0|Disp8MemShift|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
+vpbroadcastq, 0x6659, AVX2, Modrm|Vex|Space0F38|VexW0|NoSuf|Optimize, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM }
vperm2i128, 0x6646, AVX2, Modrm|Vex=2|Space0F3A|VexVVVV|VexW0|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
-vpermd, 0x6636, AVX2, Modrm|Vex256|Space0F38|VexVVVV|VexW0|NoSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
-vpermpd, 0x6601, AVX2, Modrm|Vex=2|Space0F3A|VexW1|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegYMM, RegYMM }
-vpermps, 0x6616, AVX2, Modrm|Vex256|Space0F38|VexVVVV|VexW0|NoSuf, { Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
-vpermq, 0x6600, AVX2, Modrm|Vex=2|Space0F3A|VexW1|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegYMM, RegYMM }
+vpermd, 0x6636, AVX2|AVX512F, Modrm|Vex256|EVexDYN|Masking|Space0F38|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM }
+vpermpd, 0x6601, AVX2|AVX512F, Modrm|Vex256|EVexDYN|Masking|Space0F3A|VexW1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM }
+vpermps, 0x6616, AVX2|AVX512F, Modrm|Vex256|EVexDYN|Masking|Space0F38|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM }
+vpermq, 0x6600, AVX2|AVX512F, Modrm|Vex256|EVexDYN|Masking|Space0F3A|VexW1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM }
vextracti128, 0x6639, AVX2, Modrm|Vex=2|Space0F3A|VexW=1|NoSuf, { Imm8, RegYMM, Unspecified|BaseIndex|RegXMM }
vinserti128, 0x6638, AVX2, Modrm|Vex256|Space0F3A|VexVVVV|VexW0|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM, RegYMM, RegYMM }
vpmaskmov<dq>, 0x668e, AVX2, Modrm|Vex|Space0F38|VexVVVV|<dq:vexw>|CheckOperandSize|NoSuf, { RegXMM|RegYMM, RegXMM|RegYMM, Xmmword|Ymmword|Unspecified|BaseIndex }
vpmaskmov<dq>, 0x668c, AVX2, Modrm|Vex|Space0F38|VexVVVV|<dq:vexw>|CheckOperandSize|NoSuf, { Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
-vpsllv<dq>, 0x6647, AVX2, Modrm|Vex|Space0F38|VexVVVV|<dq:vexw>|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vpsravd, 0x6646, AVX2, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vpsrlv<dq>, 0x6645, AVX2, Modrm|Vex|Space0F38|VexVVVV|<dq:vexw>|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
+vpsllv<dq>, 0x6647, AVX2|AVX512F, Modrm|Vex|EVexDYN|Masking|Space0F38|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
+vpsravd, 0x6646, AVX2|AVX512F, Modrm|Vex|EVexDYN|Masking|Space0F38|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
+vpsrlv<dq>, 0x6645, AVX2|AVX512F, Modrm|Vex|EVexDYN|Masking|Space0F38|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
// AVX gather instructions
vgatherdpd, 0x6692, AVX2, Modrm|Vex|Space0F38|VexVVVV|VexW1|SwapSources|CheckOperandSize|NoSuf|VecSIB128, { RegXMM|RegYMM, Qword|Unspecified|BaseIndex, RegXMM|RegYMM }
@@ -1779,7 +1784,7 @@ vpclmulhqhqdq, 0x6644/0x11, AVX|PCLMULQDQ, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|No
vgf2p8affineinvqb, 0x66cf, AVX|GFNI, Modrm|Vex|Space0F3A|VexVVVV|VexW1|CheckOperandSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vgf2p8affineqb, 0x66ce, AVX|GFNI, Modrm|Vex|Space0F3A|VexVVVV|VexW1|CheckOperandSize|NoSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vgf2p8mulb, 0x66cf, AVX|GFNI, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckOperandSize|NoSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
+vgf2p8mulb, 0x66cf, GFNI|AVX|AVX512F, Modrm|Vex|EVexDYN|Masking|Space0F38|VexVVVV|VexW0|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
// FSGSBASE, RDRND and F16C
@@ -2082,8 +2087,6 @@ vpclmulhqhqdq, 0x6644/0x11, VPCLMULQDQ, Modrm|Vex|Space0F3A|VexWIG|VexVVVV|Check
// AVX512F instructions.
-#define Disp8ShiftVL Disp8MemShift=DISP8_SHIFT_VL
-
<sdh:cpu:cpudq:ppfx:spfx:pfx:spc1:spc2:opc:vexw:elem, +
s:AVX512F:AVX512DQ::f3:66:Space0F:Space0F38:0:VexW0:Dword, +
d:AVX512F:AVX512DQ:66:f2:66:Space0F:Space0F38:1:VexW1:Qword, +
@@ -2142,9 +2145,7 @@ vpmuldq, 0x6628, AVX512F, Modrm|Masking|Space0F38|VexVVVV|VexW=2|Broadcast|Disp8
vpmulld, 0x6640, AVX512F, Modrm|Masking|Space0F38|VexVVVV|VexW=1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
vprolv<dq>, 0x6615, AVX512F, Modrm|Masking|Space0F38|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
vprorv<dq>, 0x6614, AVX512F, Modrm|Masking|Space0F38|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
-vpsllv<dq>, 0x6647, AVX512F, Modrm|Masking|Space0F38|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
-vpsrav<dq>, 0x6646, AVX512F, Modrm|Masking|Space0F38|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
-vpsrlv<dq>, 0x6645, AVX512F, Modrm|Masking|Space0F38|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
+vpsravq, 0x6646, AVX512F, Modrm|Masking|Space0F38|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
vpternlog<dq>, 0x6625, AVX512F, Modrm|Masking|Space0F3A|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
vbroadcastf32x4, 0x661A, AVX512F, Modrm|Masking|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { XMMword|Unspecified|BaseIndex, RegYMM|RegZMM }
@@ -2153,10 +2154,9 @@ vbroadcasti32x4, 0x665A, AVX512F, Modrm|Masking|Space0F38|VexW=1|Disp8MemShift=4
vbroadcastf64x4, 0x661B, AVX512F, Modrm|EVex=1|Masking|Space0F38|VexW=2|Disp8MemShift=5|NoSuf, { YMMword|Unspecified|BaseIndex, RegZMM }
vbroadcasti64x4, 0x665B, AVX512F, Modrm|EVex=1|Masking|Space0F38|VexW=2|Disp8MemShift=5|NoSuf, { YMMword|Unspecified|BaseIndex, RegZMM }
-vbroadcastss, 0x6618, AVX512F, Modrm|Masking|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
vbroadcastsd, 0x6619, AVX512F, Modrm|Masking|Space0F38|VexW1|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM }
-vpbroadcast<dq>, 0x6658 | <dq:opc>, AVX512F, Modrm|Masking|Space0F38|<dq:vexw>|Disp8MemShift|NoSuf, { RegXMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
+vpbroadcastq, 0x6659, AVX512F, Modrm|Masking|Space0F38|VexW1|Disp8MemShift|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
vpbroadcast<dq>, 0x667c, AVX512F, Modrm|Masking|Space0F38|<dq:vexw64>|NoSuf, { <dq:gpr>, RegXMM|RegYMM|RegZMM }
vcmp<frel>p<sd>, 0x<sd:ppfx>C2/0x<frel:imm>, AVX512F, Modrm|Masking|Space0F|VexVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|ImmExt|SAE, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
@@ -2246,9 +2246,6 @@ vextracti32x4, 0x6639, AVX512F, Modrm|Masking|Space0F3A|VexW=1|Disp8MemShift=4|N
vextractf64x4, 0x661B, AVX512F, Modrm|EVex=1|Masking|Space0F3A|VexW=2|Disp8MemShift=5|NoSuf, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex }
vextracti64x4, 0x663B, AVX512F, Modrm|EVex=1|Masking|Space0F3A|VexW=2|Disp8MemShift=5|NoSuf, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex }
-vextractps, 0x6617, AVX512F, Modrm|EVex128|Space0F3A|VexWIG|Disp8MemShift=2|NoSuf, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex }
-vextractps, 0x6617, AVX512F|x64, RegMem|EVex128|Space0F3A|VexWIG|NoSuf, { Imm8, RegXMM, Reg64 }
-
vfixupimmp<sd>, 0x6654, AVX512F, Modrm|Masking|Space0F3A|VexVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf|SAE, { Imm8|Imm8S, RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
vfixupimms<sd>, 0x6655, AVX512F, Modrm|EVexLIG|Masking|Space0F3A|VexVVVV|<sd:vexw>|Disp8MemShift|NoSuf|SAE, { Imm8|Imm8S, RegXMM|<sd:elem>|Unspecified|BaseIndex, RegXMM, RegXMM }
@@ -2304,8 +2301,6 @@ vmovap<sd>, 0x<sd:ppfx>28, AVX512F, D|Modrm|Masking|Space0F|<sd:vexw>|Disp8Shift
vmovntp<sd>, 0x<sd:ppfx>2B, AVX512F, Modrm|Space0F|<sd:vexw>|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM, XMMword|YMMword|ZMMword|Unspecified|BaseIndex }
vmovup<sd>, 0x<sd:ppfx>10, AVX512F, D|Modrm|Masking|Space0F|<sd:vexw>|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
-vmovd, 0x666E, AVX512F, D|Modrm|EVex=2|Space0F|Disp8MemShift=2|NoSuf, { Reg32|Unspecified|BaseIndex, RegXMM }
-
vmovddup, 0xF212, AVX512F, Modrm|Masking|Space0F|VexW=2|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegYMM|RegZMM|Unspecified|BaseIndex, RegYMM|RegZMM }
vmovdqa64, 0x666F, AVX512F, D|Modrm|Masking|Space0F|VexW=2|Disp8ShiftVL|CheckOperandSize|NoSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
@@ -2322,7 +2317,6 @@ vmovhp<sd>, 0x<sd:ppfx>17, AVX512F, Modrm|EVexLIG|Space0F|<sd:vexw>|Disp8MemShif
vmovlp<sd>, 0x<sd:ppfx>12, AVX512F, Modrm|EVexLIG|Space0F|VexVVVV|<sd:vexw>|Disp8MemShift=3|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
vmovlp<sd>, 0x<sd:ppfx>13, AVX512F, Modrm|EVexLIG|Space0F|<sd:vexw>|Disp8MemShift=3|NoSuf, { RegXMM, Qword|Unspecified|BaseIndex }
-vmovq, 0x666E, AVX512F|x64, D|Modrm|EVex128|Space0F|VexW1|Disp8MemShift=3|NoSuf, { Reg64|Unspecified|BaseIndex, RegXMM }
vmovq, 0xF37E, AVX512F, Load|Modrm|EVex=2|Space0F|VexW1|Disp8MemShift=3|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
vmovq, 0x66D6, AVX512F, Modrm|EVex=2|Space0F|VexW1|Disp8MemShift=3|NoSuf, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM }
@@ -2360,15 +2354,10 @@ vpcmp<irel>u<dq>, 0x661e/<irel:imm>, AVX512F, Modrm|Masking|Space0F3A|VexVVVV|<d
vptestm<dq>, 0x6627, AVX512F, Modrm|Masking|Space0F38|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
vptestnm<dq>, 0xf327, AVX512F, Modrm|Masking|Space0F38|VexVVVV|<dq:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|<dq:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
-vpermd, 0x6636, AVX512F, Modrm|Masking|Space0F38|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM }
-vpermps, 0x6616, AVX512F, Modrm|Masking|Space0F38|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM }
+vpermilpd, 0x6605, AVX512F, Modrm|Masking|Space0F3A|VexW1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
+vpermilpd, 0x660d, AVX512F, Modrm|Masking|Space0F38|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
-vpermilp<sd>, 0x6604 | <sd:opc>, AVX512F, Modrm|Masking|Space0F3A|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
-vpermilp<sd>, 0x660C | <sd:opc>, AVX512F, Modrm|Masking|Space0F38|VexVVVV|<sd:vexw>|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
-
-vpermpd, 0x6601, AVX512F, Modrm|Masking|Space0F3A|VexW=2|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM }
vpermpd, 0x6616, AVX512F, Modrm|Masking|Space0F38|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM }
-vpermq, 0x6600, AVX512F, Modrm|Masking|Space0F3A|VexW=2|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8|Imm8S, RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM }
vpermq, 0x6636, AVX512F, Modrm|Masking|Space0F38|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM }
vpmovdb, 0xF331, AVX512F, Modrm|EVex=1|Masking|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegZMM, RegXMM|Unspecified|BaseIndex }
@@ -2593,31 +2582,11 @@ vpmovsqw, 0xF324, AVX512F|AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW0|Disp8Me
vpmovusqw, 0xF314, AVX512F|AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex }
vpmovusqw, 0xF314, AVX512F|AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex }
-vpmovsxbd, 0x6621, AVX512F|AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexWIG|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM }
-vpmovsxbd, 0x6621, AVX512F|AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM }
-vpmovzxbd, 0x6631, AVX512F|AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexWIG|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM }
-vpmovzxbd, 0x6631, AVX512F|AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM }
-
-vpmovsxbq, 0x6622, AVX512F|AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexWIG|Disp8MemShift=1|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegXMM }
-vpmovsxbq, 0x6622, AVX512F|AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexWIG|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM }
-vpmovzxbq, 0x6632, AVX512F|AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexWIG|Disp8MemShift=1|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegXMM }
-vpmovzxbq, 0x6632, AVX512F|AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexWIG|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM }
-
vpmovsxdq, 0x6625, AVX512F|AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM }
vpmovsxdq, 0x6625, AVX512F|AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM }
vpmovzxdq, 0x6635, AVX512F|AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM }
vpmovzxdq, 0x6635, AVX512F|AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexW=1|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM }
-vpmovsxwd, 0x6623, AVX512F|AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM }
-vpmovsxwd, 0x6623, AVX512F|AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexWIG|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM }
-vpmovzxwd, 0x6633, AVX512F|AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM }
-vpmovzxwd, 0x6633, AVX512F|AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexWIG|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM }
-
-vpmovsxwq, 0x6624, AVX512F|AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexWIG|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM }
-vpmovsxwq, 0x6624, AVX512F|AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM }
-vpmovzxwq, 0x6634, AVX512F|AVX512VL, Modrm|EVex=2|Masking|Space0F38|VexWIG|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM }
-vpmovzxwq, 0x6634, AVX512F|AVX512VL, Modrm|EVex=3|Masking|Space0F38|VexWIG|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM }
-
// AVX512VL instructions end.
// AVX512BW instructions.
@@ -2960,7 +2929,6 @@ vpshufbitqmb, 0x668f, AVX512_BITALG, Modrm|Masking|Space0F38|VexVVVV|VexW0|Disp8
vgf2p8affineinvqb, 0x66cf, GFNI|AVX512F, Modrm|Masking|Space0F3A|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
vgf2p8affineqb, 0x66ce, GFNI|AVX512F, Modrm|Masking|Space0F3A|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
-vgf2p8mulb, 0x66cf, GFNI|AVX512F, Modrm|Masking|Space0F38|VexVVVV|VexW0|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
// AVX512 + GFNI instructions end
diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index 64223ae6f06..572527d8c61 100644
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -12747,18 +12747,9 @@ static const insn_template i386_optab[] =
1, 1, 0, 0, 0, 0 } } } },
{ MN_vbroadcastss, 0x18, 2, SPACE_0F38, None,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 1, 0, 1, 1, 0, 0, 5, 1, 0, 0, 0, 2, 0, 0, 0, 0, 0,
0 },
- { { 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
- { { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 1, 0, 0, 0, 0, 0 } },
- { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 1, 1, 0, 0, 0, 0 } } } },
- { MN_vbroadcastss, 0x18, 2, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 2, 0, 0, 0, 0, 0,
- 0 },
- { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } },
+ { { 30, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } },
{ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0,
1, 0, 0, 0, 1, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -17691,9 +17682,9 @@ static const insn_template i386_optab[] =
1, 0, 0, 0, 1, 0 } } } },
{ MN_vextractps, 0x17, 3, SPACE_0F3A, None,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 1, 0, 3, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 1, 0, 3, 1, 0, 0, 2, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0,
0 },
- { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0 } },
{ { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -17702,31 +17693,9 @@ static const insn_template i386_optab[] =
0, 0, 0, 0, 1, 0 } } } },
{ MN_vextractps, 0x17, 3, SPACE_0F3A, None,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 1, 0, 0,
- 0, 0, 0, 1, 0, 3, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 1, 0, 3, 1, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0 },
- { { 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0 } },
- { { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0 } },
- { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 1, 0, 0, 0, 0, 0 } },
- { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
- 0, 0, 0, 0, 0, 0 } } } },
- { MN_vextractps, 0x17, 3, SPACE_0F3A, None,
- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 3, 1, 0, 0, 2, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0,
- 0 },
- { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } },
- { { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0 } },
- { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 1, 0, 0, 0, 0, 0 } },
- { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0,
- 0, 0, 0, 0, 1, 0 } } } },
- { MN_vextractps, 0x17, 3, SPACE_0F3A, None,
- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 1, 0, 0,
- 0, 0, 0, 0, 0, 3, 1, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0 },
- { { 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0 } },
{ { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -18099,9 +18068,9 @@ static const insn_template i386_optab[] =
1, 1, 1, 0, 0, 0 } } } },
{ MN_vmovd, 0x6e, 2, SPACE_0F, None,
{ 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 1, 0, 0, 1, 0, 0, 2, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0,
0 },
- { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0 } },
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0,
0, 0, 0, 0, 1, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -18115,15 +18084,6 @@ static const insn_template i386_optab[] =
1, 0, 0, 0, 0, 0 } },
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
0, 0, 0, 0, 0, 0 } } } },
- { MN_vmovd, 0x6e, 2, SPACE_0F, None,
- { 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 1, 0, 0, 2, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0,
- 0 },
- { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } },
- { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0,
- 0, 0, 0, 0, 1, 0 } },
- { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 1, 0, 0, 0, 0, 0 } } } },
{ MN_vmovddup, 0x12, 2, SPACE_0F, None,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 1, 0, 3, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -18492,18 +18452,9 @@ static const insn_template i386_optab[] =
1, 0, 0, 0, 1, 0 } } } },
{ MN_vmovq, 0x6e, 2, SPACE_0F, None,
{ 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 1, 0, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0 },
- { { 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0 } },
- { { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0,
- 0, 0, 0, 0, 1, 0 } },
- { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 1, 0, 0, 0, 0, 0 } } } },
- { MN_vmovq, 0x6e, 2, SPACE_0F, None,
- { 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 2, 1, 0, 0, 2, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0,
+ 0, 0, 0, 1, 0, 2, 1, 0, 0, 2, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0,
0 },
- { { 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0 } },
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0,
0, 0, 0, 0, 1, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -19558,51 +19509,29 @@ static const insn_template i386_optab[] =
0, 1, 0, 0, 0, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 1, 0, 0, 0, 0 } } } },
- { MN_vpermilps, 0x0c | 0, 3, SPACE_0F38, None,
+ { MN_vpermilps, 0x0c, 3, SPACE_0F38, None,
{ 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 1, 1, 1, 1, 0, 0, 5, 1, 3, 0, 0, 7, 0, 0, 0, 0, 0,
0 },
- { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } },
- { { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0,
- 1, 1, 0, 0, 1, 0 } },
- { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 1, 1, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0 } },
+ { { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0,
+ 1, 1, 1, 0, 1, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 1, 1, 0, 0, 0, 0 } } } },
- { MN_vpermilps, 0x04 | 0, 3, SPACE_0F3A, None,
- { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0 },
- { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } },
- { { { 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0 } },
- { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0,
- 1, 1, 0, 0, 1, 0 } },
+ 1, 1, 1, 0, 0, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 1, 1, 0, 0, 0, 0 } } } },
- { MN_vpermilps, 0x04 | 0, 3, SPACE_0F3A, None,
+ 1, 1, 1, 0, 0, 0 } } } },
+ { MN_vpermilps, 0x04, 3, SPACE_0F3A, None,
{ 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 1, 3, 0, 0, 7, 0, 0, 0, 0, 0,
+ 0, 0, 0, 1, 0, 1, 1, 0, 0, 5, 1, 3, 0, 0, 7, 0, 0, 0, 0, 0,
0 },
- { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0 } },
{ { { 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0,
1, 1, 1, 0, 1, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1, 1, 1, 0, 0, 0 } } } },
- { MN_vpermilps, 0x0c | 0, 3, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 1, 3, 0, 0, 7, 0, 0, 0, 0, 0,
- 0 },
- { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } },
- { { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0,
- 1, 1, 1, 0, 1, 0 } },
- { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 1, 1, 1, 0, 0, 0 } },
- { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 1, 1, 1, 0, 0, 0 } } } },
- { MN_vpermilpd, 0x0c | 1, 3, SPACE_0F38, None,
+ { MN_vpermilpd, 0x0d, 3, SPACE_0F38, None,
{ 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0 },
@@ -19613,7 +19542,7 @@ static const insn_template i386_optab[] =
1, 1, 0, 0, 0, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1, 1, 0, 0, 0, 0 } } } },
- { MN_vpermilpd, 0x04 | 1, 3, SPACE_0F3A, None,
+ { MN_vpermilpd, 0x05, 3, SPACE_0F3A, None,
{ 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0 },
@@ -19624,7 +19553,7 @@ static const insn_template i386_optab[] =
1, 1, 0, 0, 1, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1, 1, 0, 0, 0, 0 } } } },
- { MN_vpermilpd, 0x04 | 1, 3, SPACE_0F3A, None,
+ { MN_vpermilpd, 0x05, 3, SPACE_0F3A, None,
{ 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 2, 1, 0, 0, 0, 1, 4, 0, 0, 7, 0, 0, 0, 0, 0,
0 },
@@ -19635,7 +19564,7 @@ static const insn_template i386_optab[] =
1, 1, 1, 0, 1, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1, 1, 1, 0, 0, 0 } } } },
- { MN_vpermilpd, 0x0c | 1, 3, SPACE_0F38, None,
+ { MN_vpermilpd, 0x0d, 3, SPACE_0F38, None,
{ 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 0, 1, 2, 1, 0, 0, 0, 1, 4, 0, 0, 7, 0, 0, 0, 0, 0,
0 },
@@ -20350,18 +20279,18 @@ static const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0 } } } },
{ MN_vpmovsxbd, 0x21, 2, SPACE_0F38, None,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 1, 0, 3, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 1, 0, 3, 1, 0, 0, 2, 1, 0, 0, 0, 2, 0, 0, 0, 0, 0,
0 },
- { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0 } },
{ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0,
1, 0, 0, 0, 1, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1, 0, 0, 0, 0, 0 } } } },
{ MN_vpmovsxbd, 0x21, 2, SPACE_0F38, None,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 2, 0, 3, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 2, 0, 3, 1, 0, 0, 3, 1, 0, 0, 0, 3, 0, 0, 0, 0, 0,
0 },
- { { 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+ { { 30, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0 } },
{ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 1, 0,
1, 0, 0, 0, 1, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -20375,38 +20304,20 @@ static const insn_template i386_optab[] =
1, 0, 0, 0, 1, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 1, 0, 0, 0 } } } },
- { MN_vpmovsxbd, 0x21, 2, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 3, 1, 0, 0, 2, 1, 0, 0, 0, 2, 0, 0, 0, 0, 0,
- 0 },
- { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0 } },
- { { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0,
- 1, 0, 0, 0, 1, 0 } },
- { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 1, 0, 0, 0, 0, 0 } } } },
- { MN_vpmovsxbd, 0x21, 2, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 3, 1, 0, 0, 3, 1, 0, 0, 0, 3, 0, 0, 0, 0, 0,
- 0 },
- { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0 } },
- { { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 1, 0,
- 1, 0, 0, 0, 1, 0 } },
- { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 1, 0, 0, 0, 0 } } } },
{ MN_vpmovsxbq, 0x22, 2, SPACE_0F38, None,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 1, 0, 3, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 1, 0, 3, 1, 0, 0, 2, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0,
0 },
- { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0 } },
{ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 1, 0, 0, 0, 0,
1, 0, 0, 0, 1, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1, 0, 0, 0, 0, 0 } } } },
{ MN_vpmovsxbq, 0x22, 2, SPACE_0F38, None,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 2, 0, 3, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 2, 0, 3, 1, 0, 0, 3, 1, 0, 0, 0, 2, 0, 0, 0, 0, 0,
0 },
- { { 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+ { { 30, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0 } },
{ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0,
1, 0, 0, 0, 1, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -20420,24 +20331,6 @@ static const insn_template i386_optab[] =
1, 0, 0, 0, 1, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 1, 0, 0, 0 } } } },
- { MN_vpmovsxbq, 0x22, 2, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 3, 1, 0, 0, 2, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0,
- 0 },
- { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0 } },
- { { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 1, 0, 0, 0, 0,
- 1, 0, 0, 0, 1, 0 } },
- { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 1, 0, 0, 0, 0, 0 } } } },
- { MN_vpmovsxbq, 0x22, 2, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 3, 1, 0, 0, 3, 1, 0, 0, 0, 2, 0, 0, 0, 0, 0,
- 0 },
- { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0 } },
- { { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0,
- 1, 0, 0, 0, 1, 0 } },
- { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 1, 0, 0, 0, 0 } } } },
{ MN_vpmovsxbw, 0x20, 2, SPACE_0F38, None,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 1, 0, 3, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -20530,18 +20423,18 @@ static const insn_template i386_optab[] =
0, 1, 0, 0, 0, 0 } } } },
{ MN_vpmovsxwd, 0x23, 2, SPACE_0F38, None,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 1, 0, 3, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 1, 0, 3, 1, 0, 0, 2, 1, 0, 0, 0, 3, 0, 0, 0, 0, 0,
0 },
- { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0 } },
{ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 1, 0,
1, 0, 0, 0, 1, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1, 0, 0, 0, 0, 0 } } } },
{ MN_vpmovsxwd, 0x23, 2, SPACE_0F38, None,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 2, 0, 3, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 2, 0, 3, 1, 0, 0, 3, 1, 0, 0, 0, 4, 0, 0, 0, 0, 0,
0 },
- { { 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+ { { 30, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0 } },
{ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0,
1, 0, 0, 0, 1, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -20555,38 +20448,20 @@ static const insn_template i386_optab[] =
0, 1, 0, 0, 1, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 1, 0, 0, 0 } } } },
- { MN_vpmovsxwd, 0x23, 2, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 3, 1, 0, 0, 2, 1, 0, 0, 0, 3, 0, 0, 0, 0, 0,
- 0 },
- { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0 } },
- { { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 1, 0,
- 1, 0, 0, 0, 1, 0 } },
- { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 1, 0, 0, 0, 0, 0 } } } },
- { MN_vpmovsxwd, 0x23, 2, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 3, 1, 0, 0, 3, 1, 0, 0, 0, 4, 0, 0, 0, 0, 0,
- 0 },
- { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0 } },
- { { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0,
- 1, 0, 0, 0, 1, 0 } },
- { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 1, 0, 0, 0, 0 } } } },
{ MN_vpmovsxwq, 0x24, 2, SPACE_0F38, None,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 1, 0, 3, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 1, 0, 3, 1, 0, 0, 2, 1, 0, 0, 0, 2, 0, 0, 0, 0, 0,
0 },
- { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0 } },
{ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0,
1, 0, 0, 0, 1, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1, 0, 0, 0, 0, 0 } } } },
{ MN_vpmovsxwq, 0x24, 2, SPACE_0F38, None,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 2, 0, 3, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 2, 0, 3, 1, 0, 0, 3, 1, 0, 0, 0, 3, 0, 0, 0, 0, 0,
0 },
- { { 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+ { { 30, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0 } },
{ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 1, 0,
1, 0, 0, 0, 1, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -20600,38 +20475,20 @@ static const insn_template i386_optab[] =
1, 0, 0, 0, 1, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 1, 0, 0, 0 } } } },
- { MN_vpmovsxwq, 0x24, 2, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 3, 1, 0, 0, 2, 1, 0, 0, 0, 2, 0, 0, 0, 0, 0,
- 0 },
- { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0 } },
- { { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0,
- 1, 0, 0, 0, 1, 0 } },
- { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 1, 0, 0, 0, 0, 0 } } } },
- { MN_vpmovsxwq, 0x24, 2, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 3, 1, 0, 0, 3, 1, 0, 0, 0, 3, 0, 0, 0, 0, 0,
- 0 },
- { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0 } },
- { { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 1, 0,
- 1, 0, 0, 0, 1, 0 } },
- { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 1, 0, 0, 0, 0 } } } },
{ MN_vpmovzxbd, 0x31, 2, SPACE_0F38, None,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 1, 0, 3, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 1, 0, 3, 1, 0, 0, 2, 1, 0, 0, 0, 2, 0, 0, 0, 0, 0,
0 },
- { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0 } },
{ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0,
1, 0, 0, 0, 1, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1, 0, 0, 0, 0, 0 } } } },
{ MN_vpmovzxbd, 0x31, 2, SPACE_0F38, None,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 2, 0, 3, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 2, 0, 3, 1, 0, 0, 3, 1, 0, 0, 0, 3, 0, 0, 0, 0, 0,
0 },
- { { 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+ { { 30, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0 } },
{ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 1, 0,
1, 0, 0, 0, 1, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -20645,38 +20502,20 @@ static const insn_template i386_optab[] =
1, 0, 0, 0, 1, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 1, 0, 0, 0 } } } },
- { MN_vpmovzxbd, 0x31, 2, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 3, 1, 0, 0, 2, 1, 0, 0, 0, 2, 0, 0, 0, 0, 0,
- 0 },
- { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0 } },
- { { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0,
- 1, 0, 0, 0, 1, 0 } },
- { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 1, 0, 0, 0, 0, 0 } } } },
- { MN_vpmovzxbd, 0x31, 2, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 3, 1, 0, 0, 3, 1, 0, 0, 0, 3, 0, 0, 0, 0, 0,
- 0 },
- { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0 } },
- { { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 1, 0,
- 1, 0, 0, 0, 1, 0 } },
- { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 1, 0, 0, 0, 0 } } } },
{ MN_vpmovzxbq, 0x32, 2, SPACE_0F38, None,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 1, 0, 3, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 1, 0, 3, 1, 0, 0, 2, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0,
0 },
- { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0 } },
{ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 1, 0, 0, 0, 0,
1, 0, 0, 0, 1, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1, 0, 0, 0, 0, 0 } } } },
{ MN_vpmovzxbq, 0x32, 2, SPACE_0F38, None,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 2, 0, 3, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 2, 0, 3, 1, 0, 0, 3, 1, 0, 0, 0, 2, 0, 0, 0, 0, 0,
0 },
- { { 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+ { { 30, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0 } },
{ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0,
1, 0, 0, 0, 1, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -20690,24 +20529,6 @@ static const insn_template i386_optab[] =
1, 0, 0, 0, 1, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 1, 0, 0, 0 } } } },
- { MN_vpmovzxbq, 0x32, 2, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 3, 1, 0, 0, 2, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0,
- 0 },
- { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0 } },
- { { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 1, 0, 0, 0, 0,
- 1, 0, 0, 0, 1, 0 } },
- { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 1, 0, 0, 0, 0, 0 } } } },
- { MN_vpmovzxbq, 0x32, 2, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 3, 1, 0, 0, 3, 1, 0, 0, 0, 2, 0, 0, 0, 0, 0,
- 0 },
- { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0 } },
- { { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0,
- 1, 0, 0, 0, 1, 0 } },
- { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 1, 0, 0, 0, 0 } } } },
{ MN_vpmovzxbw, 0x30, 2, SPACE_0F38, None,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 1, 0, 3, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -20800,18 +20621,18 @@ static const insn_template i386_optab[] =
0, 1, 0, 0, 0, 0 } } } },
{ MN_vpmovzxwd, 0x33, 2, SPACE_0F38, None,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 1, 0, 3, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 1, 0, 3, 1, 0, 0, 2, 1, 0, 0, 0, 3, 0, 0, 0, 0, 0,
0 },
- { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0 } },
{ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 1, 0,
1, 0, 0, 0, 1, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1, 0, 0, 0, 0, 0 } } } },
{ MN_vpmovzxwd, 0x33, 2, SPACE_0F38, None,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 2, 0, 3, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 2, 0, 3, 1, 0, 0, 3, 1, 0, 0, 0, 4, 0, 0, 0, 0, 0,
0 },
- { { 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+ { { 30, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0 } },
{ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0,
1, 0, 0, 0, 1, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -20825,38 +20646,20 @@ static const insn_template i386_optab[] =
0, 1, 0, 0, 1, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 1, 0, 0, 0 } } } },
- { MN_vpmovzxwd, 0x33, 2, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 3, 1, 0, 0, 2, 1, 0, 0, 0, 3, 0, 0, 0, 0, 0,
- 0 },
- { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0 } },
- { { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 1, 0,
- 1, 0, 0, 0, 1, 0 } },
- { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 1, 0, 0, 0, 0, 0 } } } },
- { MN_vpmovzxwd, 0x33, 2, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 3, 1, 0, 0, 3, 1, 0, 0, 0, 4, 0, 0, 0, 0, 0,
- 0 },
- { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0 } },
- { { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0,
- 1, 0, 0, 0, 1, 0 } },
- { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 1, 0, 0, 0, 0 } } } },
{ MN_vpmovzxwq, 0x34, 2, SPACE_0F38, None,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 1, 0, 3, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 1, 0, 3, 1, 0, 0, 2, 1, 0, 0, 0, 2, 0, 0, 0, 0, 0,
0 },
- { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } },
+ { { 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0 } },
{ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0,
1, 0, 0, 0, 1, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1, 0, 0, 0, 0, 0 } } } },
{ MN_vpmovzxwq, 0x34, 2, SPACE_0F38, None,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 2, 0, 3, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 2, 0, 3, 1, 0, 0, 3, 1, 0, 0, 0, 3, 0, 0, 0, 0, 0,
0 },
- { { 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+ { { 30, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0 } },
{ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 1, 0,
1, 0, 0, 0, 1, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -20870,24 +20673,6 @@ static const insn_template i386_optab[] =
1, 0, 0, 0, 1, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 1, 0, 0, 0 } } } },
- { MN_vpmovzxwq, 0x34, 2, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 3, 1, 0, 0, 2, 1, 0, 0, 0, 2, 0, 0, 0, 0, 0,
- 0 },
- { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0 } },
- { { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0,
- 1, 0, 0, 0, 1, 0 } },
- { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 1, 0, 0, 0, 0, 0 } } } },
- { MN_vpmovzxwq, 0x34, 2, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 3, 1, 0, 0, 3, 1, 0, 0, 0, 3, 0, 0, 0, 0, 0,
- 0 },
- { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0 } },
- { { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 1, 0,
- 1, 0, 0, 0, 1, 0 } },
- { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 1, 0, 0, 0, 0 } } } },
{ MN_vpmuldq, 0x28, 3, SPACE_0F38, None,
{ 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 1, 1, 3, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -22555,20 +22340,11 @@ static const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1, 1, 1, 0, 0, 0 } } } },
- { MN_vpbroadcastd, 0x58 | 0, 2, SPACE_0F38, None,
+ { MN_vpbroadcastd, 0x58, 2, SPACE_0F38, None,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
+ 0, 0, 0, 1, 0, 1, 1, 0, 0, 5, 1, 0, 0, 0, 2, 0, 0, 0, 0, 0,
0 },
- { { 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
- { { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0,
- 1, 0, 0, 0, 1, 0 } },
- { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 1, 1, 0, 0, 0, 0 } } } },
- { MN_vpbroadcastd, 0x58 | 0, 2, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 2, 0, 0, 0, 0, 0,
- 0 },
- { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } },
+ { { 30, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } },
{ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0,
1, 0, 0, 0, 1, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -22582,7 +22358,7 @@ static const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1, 1, 1, 0, 0, 0 } } } },
- { MN_vpbroadcastq, 0x58 | 1, 2, SPACE_0F38, None,
+ { MN_vpbroadcastq, 0x59, 2, SPACE_0F38, None,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
0 },
@@ -22591,7 +22367,7 @@ static const insn_template i386_optab[] =
1, 0, 0, 0, 1, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1, 1, 0, 0, 0, 0 } } } },
- { MN_vpbroadcastq, 0x58 | 1, 2, SPACE_0F38, None,
+ { MN_vpbroadcastq, 0x59, 2, SPACE_0F38, None,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 2, 1, 0, 0, 0, 1, 0, 0, 0, 3, 0, 0, 0, 0, 0,
0 },
@@ -22622,44 +22398,22 @@ static const insn_template i386_optab[] =
0, 1, 0, 0, 0, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 1, 0, 0, 0, 0 } } } },
- { MN_vpermd, 0x36, 3, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 2, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0 },
- { { 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
- { { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0,
- 0, 1, 0, 0, 1, 0 } },
- { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 1, 0, 0, 0, 0 } },
- { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 1, 0, 0, 0, 0 } } } },
{ MN_vpermd, 0x36, 3, SPACE_0F38, None,
{ 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 1, 3, 0, 0, 7, 0, 0, 0, 0, 0,
+ 0, 0, 0, 2, 1, 1, 1, 0, 0, 5, 1, 3, 0, 0, 7, 0, 0, 0, 0, 0,
0 },
- { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } },
+ { { 30, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } },
{ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0,
0, 1, 1, 0, 1, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 1, 1, 0, 0, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 1, 1, 0, 0, 0 } } } },
- { MN_vpermpd, 0x01, 3, SPACE_0F3A, None,
- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 2, 0, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0 },
- { { 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
- { { { 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0 } },
- { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0,
- 0, 1, 0, 0, 1, 0 } },
- { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 1, 0, 0, 0, 0 } } } },
{ MN_vpermpd, 0x01, 3, SPACE_0F3A, None,
{ 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 2, 1, 0, 0, 0, 1, 4, 0, 0, 7, 0, 0, 0, 0, 0,
+ 0, 0, 0, 2, 0, 2, 1, 0, 0, 5, 1, 4, 0, 0, 7, 0, 0, 0, 0, 0,
0 },
- { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } },
+ { { 30, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } },
{ { { 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 1, 0,
@@ -22677,44 +22431,22 @@ static const insn_template i386_optab[] =
0, 1, 1, 0, 0, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 1, 1, 0, 0, 0 } } } },
- { MN_vpermps, 0x16, 3, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 2, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0 },
- { { 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
- { { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0,
- 0, 1, 0, 0, 1, 0 } },
- { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 1, 0, 0, 0, 0 } },
- { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 1, 0, 0, 0, 0 } } } },
{ MN_vpermps, 0x16, 3, SPACE_0F38, None,
{ 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 1, 3, 0, 0, 7, 0, 0, 0, 0, 0,
+ 0, 0, 0, 2, 1, 1, 1, 0, 0, 5, 1, 3, 0, 0, 7, 0, 0, 0, 0, 0,
0 },
- { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } },
+ { { 30, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } },
{ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0,
0, 1, 1, 0, 1, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 1, 1, 0, 0, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 1, 1, 0, 0, 0 } } } },
- { MN_vpermq, 0x00, 3, SPACE_0F3A, None,
- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 2, 0, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0 },
- { { 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
- { { { 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0 } },
- { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0,
- 0, 1, 0, 0, 1, 0 } },
- { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 1, 0, 0, 0, 0 } } } },
{ MN_vpermq, 0x00, 3, SPACE_0F3A, None,
{ 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 2, 1, 0, 0, 0, 1, 4, 0, 0, 7, 0, 0, 0, 0, 0,
+ 0, 0, 0, 2, 0, 2, 1, 0, 0, 5, 1, 4, 0, 0, 7, 0, 0, 0, 0, 0,
0 },
- { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } },
+ { { 30, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } },
{ { { 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 1, 0,
@@ -22802,20 +22534,9 @@ static const insn_template i386_optab[] =
1, 1, 0, 0, 0, 0 } } } },
{ MN_vpsllvd, 0x47, 3, SPACE_0F38, None,
{ 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 1, 1, 1, 1, 0, 0, 5, 1, 3, 0, 0, 7, 0, 0, 0, 0, 0,
0 },
- { { 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
- { { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0,
- 1, 1, 0, 0, 1, 0 } },
- { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 1, 1, 0, 0, 0, 0 } },
- { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 1, 1, 0, 0, 0, 0 } } } },
- { MN_vpsllvd, 0x47, 3, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 1, 3, 0, 0, 7, 0, 0, 0, 0, 0,
- 0 },
- { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } },
+ { { 30, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } },
{ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0,
1, 1, 1, 0, 1, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -22824,20 +22545,9 @@ static const insn_template i386_optab[] =
1, 1, 1, 0, 0, 0 } } } },
{ MN_vpsllvq, 0x47, 3, SPACE_0F38, None,
{ 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 1, 1, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0 },
- { { 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
- { { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0,
- 1, 1, 0, 0, 1, 0 } },
- { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 1, 1, 0, 0, 0, 0 } },
- { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 1, 1, 0, 0, 0, 0 } } } },
- { MN_vpsllvq, 0x47, 3, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 1, 2, 1, 0, 0, 0, 1, 4, 0, 0, 7, 0, 0, 0, 0, 0,
+ 0, 0, 0, 1, 1, 2, 1, 0, 0, 5, 1, 4, 0, 0, 7, 0, 0, 0, 0, 0,
0 },
- { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } },
+ { { 30, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } },
{ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 1, 0,
1, 1, 1, 0, 1, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -22846,20 +22556,9 @@ static const insn_template i386_optab[] =
1, 1, 1, 0, 0, 0 } } } },
{ MN_vpsravd, 0x46, 3, SPACE_0F38, None,
{ 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 1, 1, 1, 1, 0, 0, 5, 1, 3, 0, 0, 7, 0, 0, 0, 0, 0,
0 },
- { { 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
- { { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0,
- 1, 1, 0, 0, 1, 0 } },
- { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 1, 1, 0, 0, 0, 0 } },
- { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 1, 1, 0, 0, 0, 0 } } } },
- { MN_vpsravd, 0x46, 3, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 1, 3, 0, 0, 7, 0, 0, 0, 0, 0,
- 0 },
- { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } },
+ { { 30, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } },
{ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0,
1, 1, 1, 0, 1, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -22868,20 +22567,9 @@ static const insn_template i386_optab[] =
1, 1, 1, 0, 0, 0 } } } },
{ MN_vpsrlvd, 0x45, 3, SPACE_0F38, None,
{ 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0 },
- { { 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
- { { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0,
- 1, 1, 0, 0, 1, 0 } },
- { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 1, 1, 0, 0, 0, 0 } },
- { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 1, 1, 0, 0, 0, 0 } } } },
- { MN_vpsrlvd, 0x45, 3, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 1, 3, 0, 0, 7, 0, 0, 0, 0, 0,
+ 0, 0, 0, 1, 1, 1, 1, 0, 0, 5, 1, 3, 0, 0, 7, 0, 0, 0, 0, 0,
0 },
- { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } },
+ { { 30, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } },
{ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0,
1, 1, 1, 0, 1, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -22890,20 +22578,9 @@ static const insn_template i386_optab[] =
1, 1, 1, 0, 0, 0 } } } },
{ MN_vpsrlvq, 0x45, 3, SPACE_0F38, None,
{ 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 1, 1, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0 },
- { { 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
- { { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0,
- 1, 1, 0, 0, 1, 0 } },
- { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 1, 1, 0, 0, 0, 0 } },
- { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 1, 1, 0, 0, 0, 0 } } } },
- { MN_vpsrlvq, 0x45, 3, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 1, 2, 1, 0, 0, 0, 1, 4, 0, 0, 7, 0, 0, 0, 0, 0,
+ 0, 0, 0, 1, 1, 2, 1, 0, 0, 5, 1, 4, 0, 0, 7, 0, 0, 0, 0, 0,
0 },
- { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } },
+ { { 30, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } },
{ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 1, 0,
1, 1, 1, 0, 1, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -23639,20 +23316,9 @@ static const insn_template i386_optab[] =
1, 1, 1, 0, 0, 0 } } } },
{ MN_vgf2p8mulb, 0xcf, 3, SPACE_0F38, None,
{ 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0 },
- { { 110, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } },
- { { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0,
- 1, 1, 0, 0, 1, 0 } },
- { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 1, 1, 0, 0, 0, 0 } },
- { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 1, 1, 0, 0, 0, 0 } } } },
- { MN_vgf2p8mulb, 0xcf, 3, SPACE_0F38, None,
- { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 7, 0, 0, 0, 0, 0,
+ 0, 0, 0, 1, 1, 1, 1, 0, 0, 5, 1, 0, 0, 0, 7, 0, 0, 0, 0, 0,
0 },
- { { 110, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } },
+ { { 110, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0 } },
{ { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0,
1, 1, 1, 0, 1, 0 } },
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -37772,392 +37438,408 @@ static const insn_template *const i386_op_sets[] =
i386_optab + 1492,
i386_optab + 1493,
i386_optab + 1496,
- i386_optab + 1499,
- i386_optab + 1501,
- i386_optab + 1503,
- i386_optab + 1505,
- i386_optab + 1507,
- i386_optab + 1509,
- i386_optab + 1511,
- i386_optab + 1513,
- i386_optab + 1515,
- i386_optab + 1517,
- i386_optab + 1519,
- i386_optab + 1521,
- i386_optab + 1523,
- i386_optab + 1525,
- i386_optab + 1527,
- i386_optab + 1529,
- i386_optab + 1531,
- i386_optab + 1533,
- i386_optab + 1535,
- i386_optab + 1537,
- i386_optab + 1539,
- i386_optab + 1541,
- i386_optab + 1543,
- i386_optab + 1545,
- i386_optab + 1547,
- i386_optab + 1549,
- i386_optab + 1551,
- i386_optab + 1553,
- i386_optab + 1555,
- i386_optab + 1557,
- i386_optab + 1559,
- i386_optab + 1561,
- i386_optab + 1563,
- i386_optab + 1565,
- i386_optab + 1567,
- i386_optab + 1569,
- i386_optab + 1571,
- i386_optab + 1573,
- i386_optab + 1575,
- i386_optab + 1577,
- i386_optab + 1579,
- i386_optab + 1581,
- i386_optab + 1583,
- i386_optab + 1585,
- i386_optab + 1587,
- i386_optab + 1589,
- i386_optab + 1591,
- i386_optab + 1593,
- i386_optab + 1595,
- i386_optab + 1597,
- i386_optab + 1599,
- i386_optab + 1601,
- i386_optab + 1603,
- i386_optab + 1605,
- i386_optab + 1607,
- i386_optab + 1609,
- i386_optab + 1611,
- i386_optab + 1613,
- i386_optab + 1615,
- i386_optab + 1617,
- i386_optab + 1619,
- i386_optab + 1621,
- i386_optab + 1623,
- i386_optab + 1625,
- i386_optab + 1627,
- i386_optab + 1629,
- i386_optab + 1631,
- i386_optab + 1633,
- i386_optab + 1635,
- i386_optab + 1637,
- i386_optab + 1639,
- i386_optab + 1641,
- i386_optab + 1643,
- i386_optab + 1645,
- i386_optab + 1647,
- i386_optab + 1649,
- i386_optab + 1651,
- i386_optab + 1653,
- i386_optab + 1655,
- i386_optab + 1657,
- i386_optab + 1659,
- i386_optab + 1661,
- i386_optab + 1663,
- i386_optab + 1665,
- i386_optab + 1667,
- i386_optab + 1669,
- i386_optab + 1671,
- i386_optab + 1673,
- i386_optab + 1675,
- i386_optab + 1677,
- i386_optab + 1679,
- i386_optab + 1681,
- i386_optab + 1683,
- i386_optab + 1685,
- i386_optab + 1687,
- i386_optab + 1689,
- i386_optab + 1691,
- i386_optab + 1693,
- i386_optab + 1695,
- i386_optab + 1697,
- i386_optab + 1699,
- i386_optab + 1701,
- i386_optab + 1703,
- i386_optab + 1705,
- i386_optab + 1707,
- i386_optab + 1709,
- i386_optab + 1711,
- i386_optab + 1713,
- i386_optab + 1715,
- i386_optab + 1717,
- i386_optab + 1719,
- i386_optab + 1721,
- i386_optab + 1723,
- i386_optab + 1725,
- i386_optab + 1727,
- i386_optab + 1729,
- i386_optab + 1731,
- i386_optab + 1733,
- i386_optab + 1735,
- i386_optab + 1737,
- i386_optab + 1739,
- i386_optab + 1741,
- i386_optab + 1743,
- i386_optab + 1745,
- i386_optab + 1747,
- i386_optab + 1749,
- i386_optab + 1751,
- i386_optab + 1753,
- i386_optab + 1755,
- i386_optab + 1757,
- i386_optab + 1759,
- i386_optab + 1761,
- i386_optab + 1763,
- i386_optab + 1765,
- i386_optab + 1767,
- i386_optab + 1769,
- i386_optab + 1771,
- i386_optab + 1773,
- i386_optab + 1775,
- i386_optab + 1777,
- i386_optab + 1779,
- i386_optab + 1781,
- i386_optab + 1783,
- i386_optab + 1785,
- i386_optab + 1787,
- i386_optab + 1789,
- i386_optab + 1791,
- i386_optab + 1793,
- i386_optab + 1795,
- i386_optab + 1797,
- i386_optab + 1799,
- i386_optab + 1801,
- i386_optab + 1803,
- i386_optab + 1805,
- i386_optab + 1807,
- i386_optab + 1809,
- i386_optab + 1811,
- i386_optab + 1813,
- i386_optab + 1815,
- i386_optab + 1817,
- i386_optab + 1819,
- i386_optab + 1821,
- i386_optab + 1823,
- i386_optab + 1825,
- i386_optab + 1827,
- i386_optab + 1829,
- i386_optab + 1831,
- i386_optab + 1833,
- i386_optab + 1835,
- i386_optab + 1837,
- i386_optab + 1839,
- i386_optab + 1841,
- i386_optab + 1843,
- i386_optab + 1845,
- i386_optab + 1847,
- i386_optab + 1849,
- i386_optab + 1851,
- i386_optab + 1853,
- i386_optab + 1855,
- i386_optab + 1857,
- i386_optab + 1859,
- i386_optab + 1861,
- i386_optab + 1863,
- i386_optab + 1865,
- i386_optab + 1867,
- i386_optab + 1869,
- i386_optab + 1871,
- i386_optab + 1873,
- i386_optab + 1875,
- i386_optab + 1877,
- i386_optab + 1879,
- i386_optab + 1884,
- i386_optab + 1886,
- i386_optab + 1891,
- i386_optab + 1893,
- i386_optab + 1895,
- i386_optab + 1900,
- i386_optab + 1902,
- i386_optab + 1904,
- i386_optab + 1906,
- i386_optab + 1911,
- i386_optab + 1913,
- i386_optab + 1915,
- i386_optab + 1917,
- i386_optab + 1921,
- i386_optab + 1927,
- i386_optab + 1929,
- i386_optab + 1934,
- i386_optab + 1936,
- i386_optab + 1938,
- i386_optab + 1940,
- i386_optab + 1942,
- i386_optab + 1944,
- i386_optab + 1946,
- i386_optab + 1948,
- i386_optab + 1950,
+ i386_optab + 1498,
+ i386_optab + 1500,
+ i386_optab + 1502,
+ i386_optab + 1504,
+ i386_optab + 1506,
+ i386_optab + 1508,
+ i386_optab + 1510,
+ i386_optab + 1512,
+ i386_optab + 1514,
+ i386_optab + 1516,
+ i386_optab + 1518,
+ i386_optab + 1520,
+ i386_optab + 1522,
+ i386_optab + 1524,
+ i386_optab + 1526,
+ i386_optab + 1528,
+ i386_optab + 1530,
+ i386_optab + 1532,
+ i386_optab + 1534,
+ i386_optab + 1536,
+ i386_optab + 1538,
+ i386_optab + 1540,
+ i386_optab + 1542,
+ i386_optab + 1544,
+ i386_optab + 1546,
+ i386_optab + 1548,
+ i386_optab + 1550,
+ i386_optab + 1552,
+ i386_optab + 1554,
+ i386_optab + 1556,
+ i386_optab + 1558,
+ i386_optab + 1560,
+ i386_optab + 1562,
+ i386_optab + 1564,
+ i386_optab + 1566,
+ i386_optab + 1568,
+ i386_optab + 1570,
+ i386_optab + 1572,
+ i386_optab + 1574,
+ i386_optab + 1576,
+ i386_optab + 1578,
+ i386_optab + 1580,
+ i386_optab + 1582,
+ i386_optab + 1584,
+ i386_optab + 1586,
+ i386_optab + 1588,
+ i386_optab + 1590,
+ i386_optab + 1592,
+ i386_optab + 1594,
+ i386_optab + 1596,
+ i386_optab + 1598,
+ i386_optab + 1600,
+ i386_optab + 1602,
+ i386_optab + 1604,
+ i386_optab + 1606,
+ i386_optab + 1608,
+ i386_optab + 1610,
+ i386_optab + 1612,
+ i386_optab + 1614,
+ i386_optab + 1616,
+ i386_optab + 1618,
+ i386_optab + 1620,
+ i386_optab + 1622,
+ i386_optab + 1624,
+ i386_optab + 1626,
+ i386_optab + 1628,
+ i386_optab + 1630,
+ i386_optab + 1632,
+ i386_optab + 1634,
+ i386_optab + 1636,
+ i386_optab + 1638,
+ i386_optab + 1640,
+ i386_optab + 1642,
+ i386_optab + 1644,
+ i386_optab + 1646,
+ i386_optab + 1648,
+ i386_optab + 1650,
+ i386_optab + 1652,
+ i386_optab + 1654,
+ i386_optab + 1656,
+ i386_optab + 1658,
+ i386_optab + 1660,
+ i386_optab + 1662,
+ i386_optab + 1664,
+ i386_optab + 1666,
+ i386_optab + 1668,
+ i386_optab + 1670,
+ i386_optab + 1672,
+ i386_optab + 1674,
+ i386_optab + 1676,
+ i386_optab + 1678,
+ i386_optab + 1680,
+ i386_optab + 1682,
+ i386_optab + 1684,
+ i386_optab + 1686,
+ i386_optab + 1688,
+ i386_optab + 1690,
+ i386_optab + 1692,
+ i386_optab + 1694,
+ i386_optab + 1696,
+ i386_optab + 1698,
+ i386_optab + 1700,
+ i386_optab + 1702,
+ i386_optab + 1704,
+ i386_optab + 1706,
+ i386_optab + 1708,
+ i386_optab + 1710,
+ i386_optab + 1712,
+ i386_optab + 1714,
+ i386_optab + 1716,
+ i386_optab + 1718,
+ i386_optab + 1720,
+ i386_optab + 1722,
+ i386_optab + 1724,
+ i386_optab + 1726,
+ i386_optab + 1728,
+ i386_optab + 1730,
+ i386_optab + 1732,
+ i386_optab + 1734,
+ i386_optab + 1736,
+ i386_optab + 1738,
+ i386_optab + 1740,
+ i386_optab + 1742,
+ i386_optab + 1744,
+ i386_optab + 1746,
+ i386_optab + 1748,
+ i386_optab + 1750,
+ i386_optab + 1752,
+ i386_optab + 1754,
+ i386_optab + 1756,
+ i386_optab + 1758,
+ i386_optab + 1760,
+ i386_optab + 1762,
+ i386_optab + 1764,
+ i386_optab + 1766,
+ i386_optab + 1768,
+ i386_optab + 1770,
+ i386_optab + 1772,
+ i386_optab + 1774,
+ i386_optab + 1776,
+ i386_optab + 1778,
+ i386_optab + 1780,
+ i386_optab + 1782,
+ i386_optab + 1784,
+ i386_optab + 1786,
+ i386_optab + 1788,
+ i386_optab + 1790,
+ i386_optab + 1792,
+ i386_optab + 1794,
+ i386_optab + 1796,
+ i386_optab + 1798,
+ i386_optab + 1800,
+ i386_optab + 1802,
+ i386_optab + 1804,
+ i386_optab + 1806,
+ i386_optab + 1808,
+ i386_optab + 1810,
+ i386_optab + 1812,
+ i386_optab + 1814,
+ i386_optab + 1816,
+ i386_optab + 1818,
+ i386_optab + 1820,
+ i386_optab + 1822,
+ i386_optab + 1824,
+ i386_optab + 1826,
+ i386_optab + 1828,
+ i386_optab + 1830,
+ i386_optab + 1832,
+ i386_optab + 1834,
+ i386_optab + 1836,
+ i386_optab + 1838,
+ i386_optab + 1840,
+ i386_optab + 1842,
+ i386_optab + 1844,
+ i386_optab + 1846,
+ i386_optab + 1848,
+ i386_optab + 1850,
+ i386_optab + 1852,
+ i386_optab + 1854,
+ i386_optab + 1856,
+ i386_optab + 1858,
+ i386_optab + 1860,
+ i386_optab + 1862,
+ i386_optab + 1864,
+ i386_optab + 1866,
+ i386_optab + 1868,
+ i386_optab + 1870,
+ i386_optab + 1872,
+ i386_optab + 1874,
+ i386_optab + 1876,
+ i386_optab + 1878,
+ i386_optab + 1883,
+ i386_optab + 1885,
+ i386_optab + 1890,
+ i386_optab + 1892,
+ i386_optab + 1894,
+ i386_optab + 1899,
+ i386_optab + 1901,
+ i386_optab + 1903,
+ i386_optab + 1905,
+ i386_optab + 1910,
+ i386_optab + 1912,
+ i386_optab + 1914,
+ i386_optab + 1916,
+ i386_optab + 1920,
+ i386_optab + 1926,
+ i386_optab + 1928,
+ i386_optab + 1933,
+ i386_optab + 1935,
+ i386_optab + 1937,
+ i386_optab + 1939,
+ i386_optab + 1941,
+ i386_optab + 1943,
+ i386_optab + 1945,
+ i386_optab + 1947,
+ i386_optab + 1949,
+ i386_optab + 1951,
i386_optab + 1952,
i386_optab + 1953,
i386_optab + 1954,
- i386_optab + 1955,
+ i386_optab + 1956,
+ i386_optab + 1957,
+ i386_optab + 1958,
i386_optab + 1959,
i386_optab + 1960,
i386_optab + 1961,
- i386_optab + 1962,
i386_optab + 1963,
i386_optab + 1964,
+ i386_optab + 1965,
i386_optab + 1966,
- i386_optab + 1967,
i386_optab + 1968,
- i386_optab + 1969,
- i386_optab + 1971,
- i386_optab + 1973,
- i386_optab + 1975,
- i386_optab + 1977,
- i386_optab + 1979,
- i386_optab + 1981,
- i386_optab + 1983,
- i386_optab + 1985,
- i386_optab + 1987,
- i386_optab + 1989,
- i386_optab + 1991,
- i386_optab + 1993,
+ i386_optab + 1970,
+ i386_optab + 1972,
+ i386_optab + 1974,
+ i386_optab + 1976,
+ i386_optab + 1978,
+ i386_optab + 1980,
+ i386_optab + 1982,
+ i386_optab + 1984,
+ i386_optab + 1986,
+ i386_optab + 1988,
+ i386_optab + 1990,
+ i386_optab + 1992,
i386_optab + 1996,
+ i386_optab + 1997,
+ i386_optab + 1998,
i386_optab + 2000,
- i386_optab + 2001,
- i386_optab + 2002,
i386_optab + 2004,
i386_optab + 2008,
- i386_optab + 2012,
+ i386_optab + 2010,
i386_optab + 2014,
i386_optab + 2018,
+ i386_optab + 2019,
+ i386_optab + 2020,
i386_optab + 2022,
- i386_optab + 2023,
i386_optab + 2024,
i386_optab + 2026,
i386_optab + 2028,
- i386_optab + 2030,
- i386_optab + 2032,
- i386_optab + 2038,
- i386_optab + 2042,
- i386_optab + 2046,
- i386_optab + 2048,
+ i386_optab + 2033,
+ i386_optab + 2037,
+ i386_optab + 2041,
+ i386_optab + 2043,
+ i386_optab + 2045,
+ i386_optab + 2047,
+ i386_optab + 2049,
i386_optab + 2050,
i386_optab + 2052,
i386_optab + 2054,
- i386_optab + 2055,
- i386_optab + 2057,
- i386_optab + 2059,
- i386_optab + 2061,
- i386_optab + 2063,
- i386_optab + 2065,
- i386_optab + 2067,
- i386_optab + 2069,
- i386_optab + 2071,
- i386_optab + 2073,
- i386_optab + 2075,
- i386_optab + 2077,
- i386_optab + 2079,
- i386_optab + 2081,
- i386_optab + 2083,
- i386_optab + 2085,
- i386_optab + 2087,
- i386_optab + 2089,
- i386_optab + 2091,
- i386_optab + 2093,
+ i386_optab + 2056,
+ i386_optab + 2058,
+ i386_optab + 2060,
+ i386_optab + 2062,
+ i386_optab + 2064,
+ i386_optab + 2066,
+ i386_optab + 2068,
+ i386_optab + 2070,
+ i386_optab + 2072,
+ i386_optab + 2074,
+ i386_optab + 2076,
+ i386_optab + 2078,
+ i386_optab + 2080,
+ i386_optab + 2082,
+ i386_optab + 2084,
+ i386_optab + 2086,
+ i386_optab + 2088,
+ i386_optab + 2090,
+ i386_optab + 2092,
+ i386_optab + 2094,
i386_optab + 2095,
- i386_optab + 2097,
- i386_optab + 2099,
+ i386_optab + 2096,
+ i386_optab + 2098,
i386_optab + 2100,
i386_optab + 2101,
- i386_optab + 2103,
+ i386_optab + 2102,
i386_optab + 2105,
- i386_optab + 2106,
- i386_optab + 2107,
- i386_optab + 2110,
- i386_optab + 2113,
+ i386_optab + 2108,
+ i386_optab + 2111,
+ i386_optab + 2114,
i386_optab + 2116,
- i386_optab + 2119,
- i386_optab + 2121,
- i386_optab + 2123,
- i386_optab + 2125,
+ i386_optab + 2118,
+ i386_optab + 2120,
+ i386_optab + 2122,
+ i386_optab + 2124,
+ i386_optab + 2126,
i386_optab + 2127,
+ i386_optab + 2128,
i386_optab + 2129,
i386_optab + 2131,
- i386_optab + 2132,
- i386_optab + 2133,
- i386_optab + 2134,
- i386_optab + 2138,
- i386_optab + 2142,
- i386_optab + 2144,
- i386_optab + 2146,
+ i386_optab + 2135,
+ i386_optab + 2137,
+ i386_optab + 2139,
+ i386_optab + 2145,
+ i386_optab + 2149,
+ i386_optab + 2150,
+ i386_optab + 2151,
i386_optab + 2152,
+ i386_optab + 2153,
+ i386_optab + 2154,
+ i386_optab + 2155,
i386_optab + 2156,
- i386_optab + 2157,
- i386_optab + 2158,
- i386_optab + 2159,
i386_optab + 2160,
- i386_optab + 2161,
i386_optab + 2162,
- i386_optab + 2163,
- i386_optab + 2167,
- i386_optab + 2169,
- i386_optab + 2171,
- i386_optab + 2175,
- i386_optab + 2177,
- i386_optab + 2179,
- i386_optab + 2181,
- i386_optab + 2183,
- i386_optab + 2185,
- i386_optab + 2187,
- i386_optab + 2189,
- i386_optab + 2191,
- i386_optab + 2193,
- i386_optab + 2195,
+ i386_optab + 2164,
+ i386_optab + 2168,
+ i386_optab + 2170,
+ i386_optab + 2172,
+ i386_optab + 2174,
+ i386_optab + 2176,
+ i386_optab + 2178,
+ i386_optab + 2180,
+ i386_optab + 2182,
+ i386_optab + 2184,
+ i386_optab + 2186,
+ i386_optab + 2188,
+ i386_optab + 2190,
+ i386_optab + 2192,
+ i386_optab + 2194,
+ i386_optab + 2196,
i386_optab + 2197,
- i386_optab + 2199,
- i386_optab + 2201,
+ i386_optab + 2200,
i386_optab + 2203,
- i386_optab + 2204,
- i386_optab + 2209,
- i386_optab + 2214,
+ i386_optab + 2208,
+ i386_optab + 2213,
+ i386_optab + 2216,
i386_optab + 2219,
- i386_optab + 2224,
- i386_optab + 2229,
- i386_optab + 2234,
- i386_optab + 2239,
- i386_optab + 2244,
+ i386_optab + 2222,
+ i386_optab + 2225,
+ i386_optab + 2230,
+ i386_optab + 2235,
+ i386_optab + 2238,
+ i386_optab + 2241,
+ i386_optab + 2243,
+ i386_optab + 2245,
+ i386_optab + 2247,
i386_optab + 2249,
- i386_optab + 2254,
- i386_optab + 2259,
+ i386_optab + 2251,
+ i386_optab + 2253,
+ i386_optab + 2255,
+ i386_optab + 2256,
+ i386_optab + 2258,
+ i386_optab + 2260,
+ i386_optab + 2262,
i386_optab + 2264,
i386_optab + 2266,
+ i386_optab + 2267,
i386_optab + 2268,
- i386_optab + 2270,
- i386_optab + 2272,
- i386_optab + 2274,
- i386_optab + 2276,
- i386_optab + 2278,
+ i386_optab + 2269,
+ i386_optab + 2273,
+ i386_optab + 2277,
i386_optab + 2279,
- i386_optab + 2281,
i386_optab + 2283,
- i386_optab + 2285,
i386_optab + 2287,
- i386_optab + 2289,
- i386_optab + 2290,
i386_optab + 2291,
- i386_optab + 2292,
- i386_optab + 2296,
- i386_optab + 2300,
- i386_optab + 2302,
- i386_optab + 2306,
- i386_optab + 2310,
- i386_optab + 2314,
- i386_optab + 2318,
+ i386_optab + 2295,
+ i386_optab + 2299,
+ i386_optab + 2301,
+ i386_optab + 2305,
+ i386_optab + 2307,
+ i386_optab + 2309,
+ i386_optab + 2311,
+ i386_optab + 2313,
+ i386_optab + 2315,
+ i386_optab + 2317,
+ i386_optab + 2319,
+ i386_optab + 2321,
i386_optab + 2322,
i386_optab + 2324,
+ i386_optab + 2326,
i386_optab + 2328,
i386_optab + 2330,
i386_optab + 2332,
i386_optab + 2334,
i386_optab + 2336,
i386_optab + 2338,
+ i386_optab + 2339,
i386_optab + 2340,
+ i386_optab + 2341,
i386_optab + 2342,
+ i386_optab + 2343,
i386_optab + 2344,
i386_optab + 2345,
+ i386_optab + 2346,
i386_optab + 2347,
i386_optab + 2349,
i386_optab + 2351,
@@ -38165,13 +37847,10 @@ static const insn_template *const i386_op_sets[] =
i386_optab + 2355,
i386_optab + 2357,
i386_optab + 2359,
- i386_optab + 2361,
+ i386_optab + 2360,
i386_optab + 2362,
- i386_optab + 2363,
i386_optab + 2364,
- i386_optab + 2365,
i386_optab + 2366,
- i386_optab + 2367,
i386_optab + 2368,
i386_optab + 2369,
i386_optab + 2370,
@@ -38181,71 +37860,75 @@ static const insn_template *const i386_op_sets[] =
i386_optab + 2378,
i386_optab + 2380,
i386_optab + 2382,
- i386_optab + 2383,
- i386_optab + 2385,
+ i386_optab + 2384,
+ i386_optab + 2386,
i386_optab + 2387,
+ i386_optab + 2388,
i386_optab + 2389,
- i386_optab + 2391,
- i386_optab + 2392,
+ i386_optab + 2390,
i386_optab + 2393,
- i386_optab + 2395,
- i386_optab + 2397,
- i386_optab + 2399,
+ i386_optab + 2396,
+ i386_optab + 2398,
i386_optab + 2401,
+ i386_optab + 2402,
i386_optab + 2403,
i386_optab + 2405,
- i386_optab + 2407,
+ i386_optab + 2406,
+ i386_optab + 2408,
i386_optab + 2409,
i386_optab + 2410,
- i386_optab + 2411,
i386_optab + 2412,
- i386_optab + 2413,
+ i386_optab + 2414,
+ i386_optab + 2415,
i386_optab + 2416,
+ i386_optab + 2417,
+ i386_optab + 2418,
i386_optab + 2419,
i386_optab + 2422,
- i386_optab + 2425,
- i386_optab + 2426,
- i386_optab + 2428,
- i386_optab + 2431,
- i386_optab + 2433,
- i386_optab + 2436,
+ i386_optab + 2427,
+ i386_optab + 2432,
i386_optab + 2437,
- i386_optab + 2438,
- i386_optab + 2440,
i386_optab + 2442,
- i386_optab + 2444,
- i386_optab + 2446,
- i386_optab + 2448,
+ i386_optab + 2445,
i386_optab + 2450,
- i386_optab + 2452,
i386_optab + 2455,
- i386_optab + 2460,
- i386_optab + 2465,
- i386_optab + 2470,
+ i386_optab + 2458,
+ i386_optab + 2461,
+ i386_optab + 2464,
+ i386_optab + 2467,
+ i386_optab + 2468,
+ i386_optab + 2469,
+ i386_optab + 2472,
i386_optab + 2475,
i386_optab + 2478,
- i386_optab + 2483,
+ i386_optab + 2481,
+ i386_optab + 2484,
+ i386_optab + 2486,
i386_optab + 2488,
+ i386_optab + 2489,
+ i386_optab + 2490,
i386_optab + 2491,
+ i386_optab + 2492,
+ i386_optab + 2493,
i386_optab + 2494,
- i386_optab + 2497,
- i386_optab + 2500,
- i386_optab + 2501,
- i386_optab + 2502,
- i386_optab + 2505,
+ i386_optab + 2499,
+ i386_optab + 2504,
+ i386_optab + 2506,
i386_optab + 2508,
- i386_optab + 2511,
+ i386_optab + 2510,
+ i386_optab + 2512,
i386_optab + 2514,
- i386_optab + 2517,
- i386_optab + 2519,
- i386_optab + 2521,
- i386_optab + 2523,
+ i386_optab + 2516,
+ i386_optab + 2518,
+ i386_optab + 2520,
+ i386_optab + 2522,
i386_optab + 2524,
- i386_optab + 2525,
i386_optab + 2526,
- i386_optab + 2527,
i386_optab + 2528,
- i386_optab + 2533,
+ i386_optab + 2530,
+ i386_optab + 2532,
+ i386_optab + 2534,
+ i386_optab + 2536,
i386_optab + 2538,
i386_optab + 2540,
i386_optab + 2542,
@@ -38290,22 +37973,39 @@ static const insn_template *const i386_op_sets[] =
i386_optab + 2620,
i386_optab[...]
[diff truncated at 100000 bytes]
More information about the Binutils-cvs
mailing list