[binutils-gdb] x86: limit use of XOP2SOURCES

[Jan Beulich]

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=ba3ffa6de0510892bf8020188d834f24ea8b7f75

commit ba3ffa6de0510892bf8020188d834f24ea8b7f75
Author: Jan Beulich <jbeulich@suse.com>
Date:   Fri Feb 10 08:14:27 2023 +0100

    x86: limit use of XOP2SOURCES
    
    The VPROT* forms with an immediate operand are entirely standard in the
    way their ModR/M bytes are built. There's no reason to invoke special
    case code. With that the handling of an immediate there can also be
    dropped; it was partially bogus anyway, as in its "no memory operands"
    portion it ignores the possibility of an immediate operand (which was
    okay only because that case was already handled by more generic code).

Diff:
---
 gas/config/tc-i386.c | 14 ++++----------
 opcodes/i386-opc.tbl |  2 +-
 opcodes/i386-tbl.h   |  8 ++++----
 3 files changed, 9 insertions(+), 15 deletions(-)

diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 79ca9e1006a..01b10c1f190 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -8620,17 +8620,11 @@ build_modrm_byte (void)
 
       if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
 	{
-	  if (operand_type_check (i.types[0], imm))
-	    i.vex.register_specifier = NULL;
+	  /* VEX.vvvv encodes one of the sources.  */
+	  if (i.tm.opcode_modifier.vexw == VEXW0)
+	    i.vex.register_specifier = i.op[0].regs;
 	  else
-	    {
-	      /* VEX.vvvv encodes one of the sources when the first
-		 operand is not an immediate.  */
-	      if (i.tm.opcode_modifier.vexw == VEXW0)
-		i.vex.register_specifier = i.op[0].regs;
-	      else
-		i.vex.register_specifier = i.op[1].regs;
-	    }
+	    i.vex.register_specifier = i.op[1].regs;
 
 	  /* Destination is a XMM register encoded in the ModRM.reg
 	     and VEX.R bit.  */
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index bf55fbcd002..48ccca05882 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -1877,7 +1877,7 @@ vpmadcsswd, 0xa6, XOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex,
 vpmadcswd, 0xb6, XOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
 vpperm, 0xa3, XOP, D|Modrm|SpaceXOP08|VexSources=2|VexVVVV|VexW0|NoSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
 vprot<xop>, 0x90 | <xop:opc>, XOP, D|Modrm|Vex128|SpaceXOP09|VexW0|VexSources=1|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM }
-vprot<xop>, 0xc0 | <xop:opc>, XOP, Modrm|Vex128|SpaceXOP08|VexW0|VexSources=1|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
+vprot<xop>, 0xc0 | <xop:opc>, XOP, Modrm|Vex128|SpaceXOP08|VexW0|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM }
 vpsha<xop>, 0x98 | <xop:opc>, XOP, D|Modrm|Vex128|SpaceXOP09|VexW0|VexSources=1|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM }
 vpshl<xop>, 0x94 | <xop:opc>, XOP, D|Modrm|Vex128|SpaceXOP09|VexW0|VexSources=1|NoSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM }
 
diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index 29fad3fab11..b6823f8eb59 100644
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -43457,7 +43457,7 @@ static const insn_template i386_optab[] =
 	  1, 0, 0, 0, 0, 0 } } } },
   { MN_vprotb, 0xc0 | 0, 3, SPACE_XOP08, None,
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
-      0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+      0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
       0 },
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -43491,7 +43491,7 @@ static const insn_template i386_optab[] =
 	  1, 0, 0, 0, 0, 0 } } } },
   { MN_vprotw, 0xc0 | 1, 3, SPACE_XOP08, None,
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
-      0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+      0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
       0 },
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -43525,7 +43525,7 @@ static const insn_template i386_optab[] =
 	  1, 0, 0, 0, 0, 0 } } } },
   { MN_vprotd, 0xc0 | 2, 3, SPACE_XOP08, None,
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
-      0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+      0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
       0 },
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -43559,7 +43559,7 @@ static const insn_template i386_optab[] =
 	  1, 0, 0, 0, 0, 0 } } } },
   { MN_vprotq, 0xc0 | 3, 3, SPACE_XOP08, None,
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
-      0, 0, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+      0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
       0 },
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,