[binutils-gdb] RISC-V: Cache management instructions
Nelson Chu
nelsonc1225@sourceware.org
Fri Mar 18 07:46:05 GMT 2022
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=41d6ac5da655a2e78109848f2db47e53552fd61a
commit 41d6ac5da655a2e78109848f2db47e53552fd61a
Author: Tsukasa OI <research_trasio@irq.a4lg.com>
Date: Tue Jan 11 19:14:02 2022 +0900
RISC-V: Cache management instructions
This commit adds 'Zicbom' / 'Zicboz' instructions.
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Add handling for
new instruction classes.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_CBO_CLEAN, MASK_CBO_CLEAN,
MATCH_CBO_FLUSH, MASK_CBO_FLUSH, MATCH_CBO_INVAL,
MASK_CBO_INVAL, MATCH_CBO_ZERO, MASK_CBO_ZERO): New macros.
* opcode/riscv.h (enum riscv_insn_class): Add new instruction
classes INSN_CLASS_ZICBOM and INSN_CLASS_ZICBOZ.
opcodes/ChangeLog:
* riscv-opc.c (riscv_opcodes): Add cache-block management
instructions.
Diff:
---
bfd/elfxx-riscv.c | 6 ++++++
gas/testsuite/gas/riscv/zicbom-fail.d | 3 +++
gas/testsuite/gas/riscv/zicbom-fail.l | 7 +++++++
gas/testsuite/gas/riscv/zicbom-fail.s | 7 +++++++
gas/testsuite/gas/riscv/zicbom.d | 15 +++++++++++++++
gas/testsuite/gas/riscv/zicbom.s | 7 +++++++
gas/testsuite/gas/riscv/zicboz-fail.d | 3 +++
gas/testsuite/gas/riscv/zicboz-fail.l | 5 +++++
gas/testsuite/gas/riscv/zicboz-fail.s | 5 +++++
gas/testsuite/gas/riscv/zicboz.d | 13 +++++++++++++
gas/testsuite/gas/riscv/zicboz.s | 5 +++++
include/opcode/riscv-opc.h | 9 +++++++++
include/opcode/riscv.h | 2 ++
opcodes/riscv-opc.c | 6 ++++++
14 files changed, 93 insertions(+)
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 185bab7d819..cb2cc146c04 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1172,7 +1172,9 @@ static struct riscv_supported_ext riscv_supported_std_ext[] =
static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{
+ {"zicbom", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zicbop", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zicboz", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zicsr", ISA_SPEC_CLASS_20191213, 2, 0, 0 },
{"zicsr", ISA_SPEC_CLASS_20190608, 2, 0, 0 },
{"zifencei", ISA_SPEC_CLASS_20191213, 2, 0, 0 },
@@ -2317,8 +2319,12 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
{
case INSN_CLASS_I:
return riscv_subset_supports (rps, "i");
+ case INSN_CLASS_ZICBOM:
+ return riscv_subset_supports (rps, "zicbom");
case INSN_CLASS_ZICBOP:
return riscv_subset_supports (rps, "zicbop");
+ case INSN_CLASS_ZICBOZ:
+ return riscv_subset_supports (rps, "zicboz");
case INSN_CLASS_ZICSR:
return riscv_subset_supports (rps, "zicsr");
case INSN_CLASS_ZIFENCEI:
diff --git a/gas/testsuite/gas/riscv/zicbom-fail.d b/gas/testsuite/gas/riscv/zicbom-fail.d
new file mode 100644
index 00000000000..a6a61dfd37e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicbom-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv64g_zicbom
+#source: zicbom-fail.s
+#error_output: zicbom-fail.l
diff --git a/gas/testsuite/gas/riscv/zicbom-fail.l b/gas/testsuite/gas/riscv/zicbom-fail.l
new file mode 100644
index 00000000000..2cf76356d2b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicbom-fail.l
@@ -0,0 +1,7 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cbo.clean 1\(x1\)'
+.*: Error: illegal operands `cbo.clean x30'
+.*: Error: illegal operands `cbo.flush \(0\+1\)\(x1\)'
+.*: Error: illegal operands `cbo.flush x30'
+.*: Error: illegal operands `cbo.inval 3\*2\+5\(x1\)'
+.*: Error: illegal operands `cbo.inval x30'
diff --git a/gas/testsuite/gas/riscv/zicbom-fail.s b/gas/testsuite/gas/riscv/zicbom-fail.s
new file mode 100644
index 00000000000..5fa22749b3a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicbom-fail.s
@@ -0,0 +1,7 @@
+target:
+ cbo.clean 1(x1)
+ cbo.clean x30
+ cbo.flush (0+1)(x1)
+ cbo.flush x30
+ cbo.inval 3*2+5(x1)
+ cbo.inval x30
diff --git a/gas/testsuite/gas/riscv/zicbom.d b/gas/testsuite/gas/riscv/zicbom.d
new file mode 100644
index 00000000000..edd8a7079f4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicbom.d
@@ -0,0 +1,15 @@
+#as: -march=rv64g_zicbom
+#source: zicbom.s
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+0010a00f[ ]+cbo\.clean[ ]+\(ra\)
+[ ]+[0-9a-f]+:[ ]+001f200f[ ]+cbo\.clean[ ]+\(t5\)
+[ ]+[0-9a-f]+:[ ]+0020a00f[ ]+cbo\.flush[ ]+\(ra\)
+[ ]+[0-9a-f]+:[ ]+002f200f[ ]+cbo\.flush[ ]+\(t5\)
+[ ]+[0-9a-f]+:[ ]+0000a00f[ ]+cbo\.inval[ ]+\(ra\)
+[ ]+[0-9a-f]+:[ ]+000f200f[ ]+cbo\.inval[ ]+\(t5\)
diff --git a/gas/testsuite/gas/riscv/zicbom.s b/gas/testsuite/gas/riscv/zicbom.s
new file mode 100644
index 00000000000..6a306b931ed
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicbom.s
@@ -0,0 +1,7 @@
+target:
+ cbo.clean (x1)
+ cbo.clean 0(x30)
+ cbo.flush (x1)
+ cbo.flush (2-2)(x30)
+ cbo.inval (x1)
+ cbo.inval 3*4-12(x30)
diff --git a/gas/testsuite/gas/riscv/zicboz-fail.d b/gas/testsuite/gas/riscv/zicboz-fail.d
new file mode 100644
index 00000000000..74cfd2fc911
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicboz-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv64g_zicboz
+#source: zicboz-fail.s
+#error_output: zicboz-fail.l
diff --git a/gas/testsuite/gas/riscv/zicboz-fail.l b/gas/testsuite/gas/riscv/zicboz-fail.l
new file mode 100644
index 00000000000..ad8dcf54e00
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicboz-fail.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Error: illegal operands `cbo.zero x1'
+.*: Error: illegal operands `cbo.zero 1\(x30\)'
+.*: Error: illegal operands `cbo.zero 3\+5\(x1\)'
+.*: Error: illegal operands `cbo.zero \(2\*4\)\(x30\)'
diff --git a/gas/testsuite/gas/riscv/zicboz-fail.s b/gas/testsuite/gas/riscv/zicboz-fail.s
new file mode 100644
index 00000000000..0856ea85ab1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicboz-fail.s
@@ -0,0 +1,5 @@
+target:
+ cbo.zero x1
+ cbo.zero 1(x30)
+ cbo.zero 3+5(x1)
+ cbo.zero (2*4)(x30)
diff --git a/gas/testsuite/gas/riscv/zicboz.d b/gas/testsuite/gas/riscv/zicboz.d
new file mode 100644
index 00000000000..e04ab3491db
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicboz.d
@@ -0,0 +1,13 @@
+#as: -march=rv64g_zicboz
+#source: zicboz.s
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+0040a00f[ ]+cbo\.zero[ ]+\(ra\)
+[ ]+[0-9a-f]+:[ ]+004f200f[ ]+cbo\.zero[ ]+\(t5\)
+[ ]+[0-9a-f]+:[ ]+0040a00f[ ]+cbo\.zero[ ]+\(ra\)
+[ ]+[0-9a-f]+:[ ]+004f200f[ ]+cbo\.zero[ ]+\(t5\)
diff --git a/gas/testsuite/gas/riscv/zicboz.s b/gas/testsuite/gas/riscv/zicboz.s
new file mode 100644
index 00000000000..3830362c376
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zicboz.s
@@ -0,0 +1,5 @@
+target:
+ cbo.zero 0(x1)
+ cbo.zero (x30)
+ cbo.zero 2-2(x1)
+ cbo.zero (3*5-15)(x30)
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 1572c84f0be..3eea33a5dae 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2036,6 +2036,15 @@
#define MASK_PREFETCH_R 0x1f07fff
#define MATCH_PREFETCH_W 0x306013
#define MASK_PREFETCH_W 0x1f07fff
+/* Zicbom/Zicboz instructions. */
+#define MATCH_CBO_CLEAN 0x10200f
+#define MASK_CBO_CLEAN 0xfff07fff
+#define MATCH_CBO_FLUSH 0x20200f
+#define MASK_CBO_FLUSH 0xfff07fff
+#define MATCH_CBO_INVAL 0x200f
+#define MASK_CBO_INVAL 0xfff07fff
+#define MATCH_CBO_ZERO 0x40200f
+#define MASK_CBO_ZERO 0xfff07fff
/* Unprivileged Counter/Timers CSR addresses. */
#define CSR_CYCLE 0xc00
#define CSR_TIME 0xc01
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 5462b5eceab..b769769b4ec 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -388,7 +388,9 @@ enum riscv_insn_class
INSN_CLASS_V,
INSN_CLASS_ZVEF,
INSN_CLASS_SVINVAL,
+ INSN_CLASS_ZICBOM,
INSN_CLASS_ZICBOP,
+ INSN_CLASS_ZICBOZ,
};
/* This structure holds information for a particular instruction. */
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 6a288987358..523d1652267 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -852,6 +852,12 @@ const struct riscv_opcode riscv_opcodes[] =
{"sfence.vma", 0, INSN_CLASS_I, "s,t", MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 },
{"wfi", 0, INSN_CLASS_I, "", MATCH_WFI, MASK_WFI, match_opcode, 0 },
+/* Zicbom and Zicboz instructions. */
+{"cbo.clean", 0, INSN_CLASS_ZICBOM, "0(s)", MATCH_CBO_CLEAN, MASK_CBO_CLEAN, match_opcode, 0 },
+{"cbo.flush", 0, INSN_CLASS_ZICBOM, "0(s)", MATCH_CBO_FLUSH, MASK_CBO_FLUSH, match_opcode, 0 },
+{"cbo.inval", 0, INSN_CLASS_ZICBOM, "0(s)", MATCH_CBO_INVAL, MASK_CBO_INVAL, match_opcode, 0 },
+{"cbo.zero", 0, INSN_CLASS_ZICBOZ, "0(s)", MATCH_CBO_ZERO, MASK_CBO_ZERO, match_opcode, 0 },
+
/* Zbb or zbkb instructions. */
{"clz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CLZ, MASK_CLZ, match_opcode, 0 },
{"ctz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CTZ, MASK_CTZ, match_opcode, 0 },
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