[binutils-gdb] RISC-V : Support bitmanip-0.93 ZBA/ZBB/ZBC instructions
Kuan-Lin Chen
kuanlinchen@sourceware.org
Tue Mar 16 06:46:32 GMT 2021
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=80d49d6a1b865c84a8596da465db285cbbdfd1bb
commit 80d49d6a1b865c84a8596da465db285cbbdfd1bb
Author: Kuan-Lin Chen <kuanlinchentw@gmail.com>
Date: Wed Feb 24 13:26:29 2021 +0800
RISC-V : Support bitmanip-0.93 ZBA/ZBB/ZBC instructions
bfd/
* elfxx-riscv.c (riscv_std_z_ext_strtab): Add zba, zbb and zbc.
gas/
* config/tc-riscv.c (ext_version_table): Add b, zba, zbb and zbc.
(riscv_multi_subset_supports): Add INSN_CLASS_ZB*.
* testsuite/gas/riscv/b-ext-64.s: Bitmanip test case.
* testsuite/gas/riscv/b-ext-64.d: Likewise.
* testsuite/gas/riscv/b-ext.s: Likewise.
* testsuite/gas/riscv/b-ext.d: Likewise.
include/
* opcode/riscv-opc.h: Support zba, zbb and zbc extensions.
* opcode/riscv.h (riscv_insn_class): Add INSN_CLASS_ZB*.
opcodes/
* riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
Diff:
---
bfd/ChangeLog | 4 ++
bfd/elfxx-riscv.c | 2 +-
gas/ChangeLog | 9 ++++
gas/config/tc-riscv.c | 13 +++++
gas/testsuite/gas/riscv/b-ext-64.d | 48 +++++++++++++++++
gas/testsuite/gas/riscv/b-ext-64.s | 39 ++++++++++++++
gas/testsuite/gas/riscv/b-ext.d | 35 +++++++++++++
gas/testsuite/gas/riscv/b-ext.s | 26 ++++++++++
include/ChangeLog | 5 ++
include/opcode/riscv-opc.h | 104 +++++++++++++++++++++++++++++++++++++
include/opcode/riscv.h | 3 ++
opcodes/ChangeLog | 4 ++
opcodes/riscv-opc.c | 53 +++++++++++++++++--
13 files changed, 340 insertions(+), 5 deletions(-)
diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index 6d61abeb74b..70203b1254f 100644
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,7 @@
+2021-03-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
+
+ * elfxx-riscv.c (riscv_std_z_ext_strtab): Add zba, zbb and zbc.
+
2021-03-12 Clément Chigot <clement.chigot@atos.net>
* reloc.c (BFD_RELOC_PPC_TLS_LE, BFD_RELOC_PPC_TLS_IE,
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index fd0fb490347..966e142be4c 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1598,7 +1598,7 @@ riscv_parse_prefixed_ext (riscv_parse_subset_t *rps,
static const char * const riscv_std_z_ext_strtab[] =
{
- "zicsr", "zifencei", "zihintpause", NULL
+ "zba", "zbb", "zbc", "zicsr", "zifencei", "zihintpause", NULL
};
static const char * const riscv_std_s_ext_strtab[] =
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 79332f0f5dc..f759c934966 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,12 @@
+2021-03-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
+
+ * config/tc-riscv.c (ext_version_table): Add b, zba, zbb and zbc.
+ (riscv_multi_subset_supports): Add INSN_CLASS_ZB*.
+ * testsuite/gas/riscv/b-ext-64.s: Bitmanip test case.
+ * testsuite/gas/riscv/b-ext-64.d: Likewise.
+ * testsuite/gas/riscv/b-ext.s: Likewise.
+ * testsuite/gas/riscv/b-ext.d: Likewise.
+
2021-03-12 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* testsuite/gas/aarch64/illegal-sysreg-7.d: New test.
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index bbf705208a3..429732f5f1a 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -139,6 +139,10 @@ static const struct riscv_ext_version ext_version_table[] =
{"zihintpause", ISA_SPEC_CLASS_DRAFT, 1, 0},
+ {"zbb", ISA_SPEC_CLASS_DRAFT, 0, 93},
+ {"zba", ISA_SPEC_CLASS_DRAFT, 0, 93},
+ {"zbc", ISA_SPEC_CLASS_DRAFT, 0, 93},
+
/* Terminate the list. */
{NULL, 0, 0, 0}
};
@@ -330,6 +334,15 @@ riscv_multi_subset_supports (enum riscv_insn_class insn_class)
case INSN_CLASS_ZIHINTPAUSE:
return riscv_subset_supports ("zihintpause");
+ case INSN_CLASS_ZBB:
+ return riscv_subset_supports ("zbb");
+
+ case INSN_CLASS_ZBA:
+ return riscv_subset_supports ("zba");
+
+ case INSN_CLASS_ZBC:
+ return riscv_subset_supports ("zbc");
+
default:
as_fatal ("internal: unreachable");
return FALSE;
diff --git a/gas/testsuite/gas/riscv/b-ext-64.d b/gas/testsuite/gas/riscv/b-ext-64.d
new file mode 100644
index 00000000000..f4a7abf02d7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/b-ext-64.d
@@ -0,0 +1,48 @@
+#as: -march=rv64i_zba_zbb_zbc
+#source: b-ext-64.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+0:[ ]+60051513[ ]+clz[ ]+a0,a0
+[ ]+4:[ ]+60151513[ ]+ctz[ ]+a0,a0
+[ ]+8:[ ]+60251513[ ]+cpop[ ]+a0,a0
+[ ]+c:[ ]+0ac5c533[ ]+min[ ]+a0,a1,a2
+[ ]+10:[ ]+0ac5d533[ ]+minu[ ]+a0,a1,a2
+[ ]+14:[ ]+0ac5e533[ ]+max[ ]+a0,a1,a2
+[ ]+18:[ ]+0ac5f533[ ]+maxu[ ]+a0,a1,a2
+[ ]+1c:[ ]+60451513[ ]+sext.b[ ]+a0,a0
+[ ]+20:[ ]+60551513[ ]+sext.h[ ]+a0,a0
+[ ]+24:[ ]+0805453b[ ]+zext.h[ ]+a0,a0
+[ ]+28:[ ]+40c5f533[ ]+andn[ ]+a0,a1,a2
+[ ]+2c:[ ]+40c5e533[ ]+orn[ ]+a0,a1,a2
+[ ]+30:[ ]+40c5c533[ ]+xnor[ ]+a0,a1,a2
+[ ]+34:[ ]+60c59533[ ]+rol[ ]+a0,a1,a2
+[ ]+38:[ ]+60c5d533[ ]+ror[ ]+a0,a1,a2
+[ ]+3c:[ ]+6025d513[ ]+rori[ ]+a0,a1,0x2
+[ ]+40:[ ]+6025d513[ ]+rori[ ]+a0,a1,0x2
+[ ]+44:[ ]+6b855513[ ]+rev8[ ]+a0,a0
+[ ]+48:[ ]+28755513[ ]+orc.b[ ]+a0,a0
+[ ]+4c:[ ]+20c5a533[ ]+sh1add[ ]+a0,a1,a2
+[ ]+50:[ ]+20c5c533[ ]+sh2add[ ]+a0,a1,a2
+[ ]+54:[ ]+20c5e533[ ]+sh3add[ ]+a0,a1,a2
+[ ]+58:[ ]+0ac59533[ ]+clmul[ ]+a0,a1,a2
+[ ]+5c:[ ]+0ac5b533[ ]+clmulh[ ]+a0,a1,a2
+[ ]+60:[ ]+0ac5a533[ ]+clmulr[ ]+a0,a1,a2
+[ ]+64:[ ]+6005151b[ ]+clzw[ ]+a0,a0
+[ ]+68:[ ]+6015151b[ ]+ctzw[ ]+a0,a0
+[ ]+6c:[ ]+6025151b[ ]+cpopw[ ]+a0,a0
+[ ]+70:[ ]+60c5953b[ ]+rolw[ ]+a0,a1,a2
+[ ]+74:[ ]+60c5d53b[ ]+rorw[ ]+a0,a1,a2
+[ ]+78:[ ]+6025d51b[ ]+roriw[ ]+a0,a1,0x2
+[ ]+7c:[ ]+6025d51b[ ]+roriw[ ]+a0,a1,0x2
+[ ]+80:[ ]+20c5a53b[ ]+sh1add.uw[ ]+a0,a1,a2
+[ ]+84:[ ]+20c5c53b[ ]+sh2add.uw[ ]+a0,a1,a2
+[ ]+88:[ ]+20c5e53b[ ]+sh3add.uw[ ]+a0,a1,a2
+[ ]+8c:[ ]+08c5853b[ ]+add.uw[ ]+a0,a1,a2
+[ ]+90:[ ]+0805853b[ ]+zext.w[ ]+a0,a1
+[ ]+94:[ ]+0825951b[ ]+slli.uw[ ]+a0,a1,0x2
diff --git a/gas/testsuite/gas/riscv/b-ext-64.s b/gas/testsuite/gas/riscv/b-ext-64.s
new file mode 100644
index 00000000000..c3ac377f4bd
--- /dev/null
+++ b/gas/testsuite/gas/riscv/b-ext-64.s
@@ -0,0 +1,39 @@
+target:
+ clz a0, a0
+ ctz a0, a0
+ cpop a0, a0
+ min a0, a1, a2
+ minu a0, a1, a2
+ max a0, a1, a2
+ maxu a0, a1, a2
+ sext.b a0, a0
+ sext.h a0, a0
+ zext.h a0, a0
+ andn a0, a1, a2
+ orn a0, a1, a2
+ xnor a0, a1, a2
+ rol a0, a1, a2
+ ror a0, a1, a2
+ ror a0, a1, 2
+ rori a0, a1, 2
+ rev8 a0, a0
+ orc.b a0, a0
+ sh1add a0, a1, a2
+ sh2add a0, a1, a2
+ sh3add a0, a1, a2
+ clmul a0, a1, a2
+ clmulh a0, a1, a2
+ clmulr a0, a1, a2
+ clzw a0, a0
+ ctzw a0, a0
+ cpopw a0, a0
+ rolw a0, a1, a2
+ rorw a0, a1, a2
+ rorw a0, a1, 2
+ roriw a0, a1, 2
+ sh1add.uw a0, a1, a2
+ sh2add.uw a0, a1, a2
+ sh3add.uw a0, a1, a2
+ add.uw a0, a1, a2
+ zext.w a0, a1
+ slli.uw a0, a1, 2
diff --git a/gas/testsuite/gas/riscv/b-ext.d b/gas/testsuite/gas/riscv/b-ext.d
new file mode 100644
index 00000000000..7410796a3b7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/b-ext.d
@@ -0,0 +1,35 @@
+#as: -march=rv32i_zba_zbb_zbc
+#source: b-ext.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+0:[ ]+60051513[ ]+clz[ ]+a0,a0
+[ ]+4:[ ]+60151513[ ]+ctz[ ]+a0,a0
+[ ]+8:[ ]+60251513[ ]+cpop[ ]+a0,a0
+[ ]+c:[ ]+0ac5c533[ ]+min[ ]+a0,a1,a2
+[ ]+10:[ ]+0ac5d533[ ]+minu[ ]+a0,a1,a2
+[ ]+14:[ ]+0ac5e533[ ]+max[ ]+a0,a1,a2
+[ ]+18:[ ]+0ac5f533[ ]+maxu[ ]+a0,a1,a2
+[ ]+1c:[ ]+60451513[ ]+sext.b[ ]+a0,a0
+[ ]+20:[ ]+60551513[ ]+sext.h[ ]+a0,a0
+[ ]+24:[ ]+08054533[ ]+zext.h[ ]+a0,a0
+[ ]+28:[ ]+40c5f533[ ]+andn[ ]+a0,a1,a2
+[ ]+2c:[ ]+40c5e533[ ]+orn[ ]+a0,a1,a2
+[ ]+30:[ ]+40c5c533[ ]+xnor[ ]+a0,a1,a2
+[ ]+34:[ ]+60c59533[ ]+rol[ ]+a0,a1,a2
+[ ]+38:[ ]+60c5d533[ ]+ror[ ]+a0,a1,a2
+[ ]+3c:[ ]+6025d513[ ]+rori[ ]+a0,a1,0x2
+[ ]+40:[ ]+6025d513[ ]+rori[ ]+a0,a1,0x2
+[ ]+44:[ ]+69855513[ ]+rev8[ ]+a0,a0
+[ ]+48:[ ]+28755513[ ]+orc.b[ ]+a0,a0
+[ ]+4c:[ ]+20c5a533[ ]+sh1add[ ]+a0,a1,a2
+[ ]+50:[ ]+20c5c533[ ]+sh2add[ ]+a0,a1,a2
+[ ]+54:[ ]+20c5e533[ ]+sh3add[ ]+a0,a1,a2
+[ ]+58:[ ]+0ac59533[ ]+clmul[ ]+a0,a1,a2
+[ ]+5c:[ ]+0ac5b533[ ]+clmulh[ ]+a0,a1,a2
+[ ]+60:[ ]+0ac5a533[ ]+clmulr[ ]+a0,a1,a2
diff --git a/gas/testsuite/gas/riscv/b-ext.s b/gas/testsuite/gas/riscv/b-ext.s
new file mode 100644
index 00000000000..051dafd1719
--- /dev/null
+++ b/gas/testsuite/gas/riscv/b-ext.s
@@ -0,0 +1,26 @@
+target:
+ clz a0, a0
+ ctz a0, a0
+ cpop a0, a0
+ min a0, a1, a2
+ minu a0, a1, a2
+ max a0, a1, a2
+ maxu a0, a1, a2
+ sext.b a0, a0
+ sext.h a0, a0
+ zext.h a0, a0
+ andn a0, a1, a2
+ orn a0, a1, a2
+ xnor a0, a1, a2
+ rol a0, a1, a2
+ ror a0, a1, a2
+ ror a0, a1, 2
+ rori a0, a1, 2
+ rev8 a0, a0
+ orc.b a0, a0
+ sh1add a0, a1, a2
+ sh2add a0, a1, a2
+ sh3add a0, a1, a2
+ clmul a0, a1, a2
+ clmulh a0, a1, a2
+ clmulr a0, a1, a2
diff --git a/include/ChangeLog b/include/ChangeLog
index b1f7e6321ae..9712268bae4 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,8 @@
+2021-03-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
+
+ * opcode/riscv-opc.h: Support zba, zbb and zbc extensions.
+ * opcode/riscv.h (riscv_insn_class): Add INSN_CLASS_ZB*.
+
2021-03-12 Frederic Cambus <fred@statdns.com>
* elf/common.h (NT_NETBSD_PAX, NT_NETBSD_PAX_MPROTECT)
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 03c3ad69944..9999da6241a 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -423,6 +423,78 @@
#define MASK_FCVT_Q_LU 0xfff0007f
#define MATCH_FMV_Q_X 0xf6000053
#define MASK_FMV_Q_X 0xfff0707f
+#define MATCH_CLZ 0x60001013
+#define MASK_CLZ 0xfff0707f
+#define MATCH_CTZ 0x60101013
+#define MASK_CTZ 0xfff0707f
+#define MATCH_CPOP 0x60201013
+#define MASK_CPOP 0xfff0707f
+#define MATCH_MIN 0xa004033
+#define MASK_MIN 0xfe00707f
+#define MATCH_MINU 0xa005033
+#define MASK_MINU 0xfe00707f
+#define MATCH_MAX 0xa006033
+#define MASK_MAX 0xfe00707f
+#define MATCH_MAXU 0xa007033
+#define MASK_MAXU 0xfe00707f
+#define MATCH_SEXT_B 0x60401013
+#define MASK_SEXT_B 0xfff0707f
+#define MATCH_SEXT_H 0x60501013
+#define MASK_SEXT_H 0xfff0707f
+#define MATCH_PACK 0x8004033
+#define MASK_PACK 0xfe00707f
+#define MATCH_PACKW 0x800403b
+#define MASK_PACKW 0xfe00707f
+#define MATCH_ANDN 0x40007033
+#define MASK_ANDN 0xfe00707f
+#define MATCH_ORN 0x40006033
+#define MASK_ORN 0xfe00707f
+#define MATCH_XNOR 0x40004033
+#define MASK_XNOR 0xfe00707f
+#define MATCH_ROL 0x60001033
+#define MASK_ROL 0xfe00707f
+#define MATCH_ROR 0x60005033
+#define MASK_ROR 0xfe00707f
+#define MATCH_RORI 0x60005013
+#define MASK_RORI 0xfc00707f
+#define MATCH_GREVI 0x68005013
+#define MASK_GREVI 0xfc00707f
+#define MATCH_GORCI 0x28005013
+#define MASK_GORCI 0xfc00707f
+#define MATCH_CLZW 0x6000101b
+#define MASK_CLZW 0xfff0707f
+#define MATCH_CTZW 0x6010101b
+#define MASK_CTZW 0xfff0707f
+#define MATCH_CPOPW 0x6020101b
+#define MASK_CPOPW 0xfff0707f
+#define MATCH_ROLW 0x6000103b
+#define MASK_ROLW 0xfe00707f
+#define MATCH_RORW 0x6000503b
+#define MASK_RORW 0xfe00707f
+#define MATCH_RORIW 0x6000501b
+#define MASK_RORIW 0xfe00707f
+#define MATCH_SH1ADD 0x20002033
+#define MASK_SH1ADD 0xfe00707f
+#define MATCH_SH2ADD 0x20004033
+#define MASK_SH2ADD 0xfe00707f
+#define MATCH_SH3ADD 0x20006033
+#define MASK_SH3ADD 0xfe00707f
+#define MATCH_SH1ADD_UW 0x2000203b
+#define MASK_SH1ADD_UW 0xfe00707f
+#define MATCH_SH2ADD_UW 0x2000403b
+#define MASK_SH2ADD_UW 0xfe00707f
+#define MATCH_SH3ADD_UW 0x2000603b
+#define MASK_SH3ADD_UW 0xfe00707f
+#define MATCH_ADD_UW 0x800003b
+#define MASK_ADD_UW 0xfe00707f
+#define MATCH_SLLI_UW 0x800101b
+#define MASK_SLLI_UW 0xfc00707f
+#define MATCH_CLMUL 0xa001033
+#define MASK_CLMUL 0xfe00707f
+#define MATCH_CLMULH 0xa003033
+#define MASK_CLMULH 0xfe00707f
+#define MATCH_CLMULR 0xa002033
+#define MASK_CLMULR 0xfe00707f
#define MATCH_FLW 0x2007
#define MASK_FLW 0x707f
#define MATCH_FLD 0x3007
@@ -998,6 +1070,38 @@ DECLARE_INSN(fcvt_q_wu, MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU)
DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L)
DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU)
DECLARE_INSN(fmv_q_x, MATCH_FMV_Q_X, MASK_FMV_Q_X)
+DECLARE_INSN(clz, MATCH_CLZ, MASK_CLZ)
+DECLARE_INSN(ctz, MATCH_CTZ, MASK_CTZ)
+DECLARE_INSN(cpop, MATCH_CPOP, MASK_CPOP)
+DECLARE_INSN(min, MATCH_MIN, MASK_MIN)
+DECLARE_INSN(minu, MATCH_MINU, MASK_MINU)
+DECLARE_INSN(max, MATCH_MAX, MASK_MAX)
+DECLARE_INSN(maxu, MATCH_MAXU, MASK_MAXU)
+DECLARE_INSN(sext_b, MATCH_SEXT_B, MASK_SEXT_B)
+DECLARE_INSN(sext_h, MATCH_SEXT_H, MASK_SEXT_H)
+DECLARE_INSN(andn, MATCH_ANDN, MASK_ANDN)
+DECLARE_INSN(orn, MATCH_ORN, MASK_ORN)
+DECLARE_INSN(xnor, MATCH_XNOR, MASK_XNOR)
+DECLARE_INSN(rol, MATCH_ROL, MASK_ROL)
+DECLARE_INSN(ror, MATCH_ROR, MASK_ROR)
+DECLARE_INSN(rori, MATCH_RORI, MASK_RORI)
+DECLARE_INSN(clzw, MATCH_CLZW, MASK_CLZW)
+DECLARE_INSN(ctzw, MATCH_CTZW, MASK_CTZW)
+DECLARE_INSN(cpopw, MATCH_CPOPW, MASK_CPOPW)
+DECLARE_INSN(rolw, MATCH_ROLW, MASK_ROLW)
+DECLARE_INSN(rorw, MATCH_RORW, MASK_RORW)
+DECLARE_INSN(roriw, MATCH_RORIW, MASK_RORIW)
+DECLARE_INSN(sh1add, MATCH_SH1ADD, MASK_SH1ADD)
+DECLARE_INSN(sh2add, MATCH_SH2ADD, MASK_SH2ADD)
+DECLARE_INSN(sh3add, MATCH_SH3ADD, MASK_SH3ADD)
+DECLARE_INSN(sh1add_uw, MATCH_SH1ADD_UW, MASK_SH1ADD_UW)
+DECLARE_INSN(sh2add_uw, MATCH_SH2ADD_UW, MASK_SH2ADD_UW)
+DECLARE_INSN(sh3add_uw, MATCH_SH3ADD_UW, MASK_SH3ADD_UW)
+DECLARE_INSN(add_uw, MATCH_ADD_UW, MASK_ADD_UW)
+DECLARE_INSN(slli_uw, MATCH_SLLI_UW, MASK_SLLI_UW)
+DECLARE_INSN(clmul, MATCH_CLMUL, MASK_CLMUL)
+DECLARE_INSN(clmulh, MATCH_CLMULH, MASK_CLMULH)
+DECLARE_INSN(clmulr, MATCH_CLMULR, MASK_CLMULR)
DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)
DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)
DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ)
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index e790723640b..fdf3df4f5c1 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -316,6 +316,9 @@ enum riscv_insn_class
INSN_CLASS_ZICSR,
INSN_CLASS_ZIFENCEI,
INSN_CLASS_ZIHINTPAUSE,
+ INSN_CLASS_ZBA,
+ INSN_CLASS_ZBB,
+ INSN_CLASS_ZBC,
};
/* This structure holds information for a particular instruction. */
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index b3390e30bad..ee67cb57de3 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2021-03-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
+
+ * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
+
2021-03-12 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index e0552db272a..1348ec78c76 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -81,6 +81,10 @@ const char * const riscv_fpr_names_abi[NFPR] =
#define MASK_AQ (OP_MASK_AQ << OP_SH_AQ)
#define MASK_RL (OP_MASK_RL << OP_SH_RL)
#define MASK_AQRL (MASK_AQ | MASK_RL)
+#define MASK_SHAMT (OP_MASK_SHAMT << OP_SH_SHAMT)
+#define MATCH_SHAMT_REV8_32 (0b11000 << OP_SH_SHAMT)
+#define MATCH_SHAMT_REV8_64 (0b111000 << OP_SH_SHAMT)
+#define MATCH_SHAMT_ORC_B (0b00111 << OP_SH_SHAMT)
static int
match_opcode (const struct riscv_opcode *op, insn_t insn)
@@ -239,10 +243,7 @@ const struct riscv_opcode riscv_opcodes[] =
{"mv", 0, INSN_CLASS_I, "d,s", MATCH_ADDI, MASK_ADDI|MASK_IMM, match_opcode, INSN_ALIAS },
{"move", 0, INSN_CLASS_C, "d,CV", MATCH_C_MV, MASK_C_MV, match_c_add, INSN_ALIAS },
{"move", 0, INSN_CLASS_I, "d,s", MATCH_ADDI, MASK_ADDI|MASK_IMM, match_opcode, INSN_ALIAS },
-{"sext.b", 0, INSN_CLASS_I, "d,s", 0, (int) M_SEXTB, match_never, INSN_MACRO },
-{"sext.h", 0, INSN_CLASS_I, "d,s", 0, (int) M_SEXTH, match_never, INSN_MACRO },
{"zext.b", 0, INSN_CLASS_I, "d,s", MATCH_ANDI|ENCODE_ITYPE_IMM (255), MASK_ANDI | MASK_IMM, match_opcode, INSN_ALIAS },
-{"zext.h", 0, INSN_CLASS_I, "d,s", 0, (int) M_ZEXTH, match_never, INSN_MACRO },
{"andi", 0, INSN_CLASS_C, "Cs,Cw,Co", MATCH_C_ANDI, MASK_C_ANDI, match_opcode, INSN_ALIAS },
{"andi", 0, INSN_CLASS_I, "d,s,j", MATCH_ANDI, MASK_ANDI, match_opcode, 0 },
{"and", 0, INSN_CLASS_C, "Cs,Cw,Ct", MATCH_C_AND, MASK_C_AND, match_opcode, INSN_ALIAS },
@@ -374,7 +375,6 @@ const struct riscv_opcode riscv_opcodes[] =
{"sd", 64, INSN_CLASS_C, "Ct,Cl(Cs)", MATCH_C_SD, MASK_C_SD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
{"sd", 64, INSN_CLASS_I, "t,q(s)", MATCH_SD, MASK_SD, match_opcode, INSN_DREF|INSN_8_BYTE },
{"sd", 64, INSN_CLASS_I, "t,A,s", 0, (int) M_SD, match_never, INSN_MACRO },
-{"zext.w", 64, INSN_CLASS_I, "d,s", 0, (int) M_ZEXTW, match_never, INSN_MACRO },
{"sext.w", 64, INSN_CLASS_C, "d,CU", MATCH_C_ADDIW, MASK_C_ADDIW|MASK_RVC_IMM, match_rd_nonzero, INSN_ALIAS },
{"sext.w", 64, INSN_CLASS_I, "d,s", MATCH_ADDIW, MASK_ADDIW|MASK_IMM, match_opcode, INSN_ALIAS },
{"addiw", 64, INSN_CLASS_C, "d,CU,Co", MATCH_C_ADDIW, MASK_C_ADDIW, match_rd_nonzero, INSN_ALIAS },
@@ -781,6 +781,51 @@ const struct riscv_opcode riscv_opcodes[] =
{"sfence.vma", 0, INSN_CLASS_I, "s", MATCH_SFENCE_VMA, MASK_SFENCE_VMA|MASK_RS2, match_opcode, INSN_ALIAS },
{"sfence.vma", 0, INSN_CLASS_I, "s,t", MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 },
{"wfi", 0, INSN_CLASS_I, "", MATCH_WFI, MASK_WFI, match_opcode, 0 },
+{"clz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CLZ, MASK_CLZ, match_opcode, 0 },
+{"ctz", 0, INSN_CLASS_ZBB, "d,s", MATCH_CTZ, MASK_CTZ, match_opcode, 0 },
+{"cpop", 0, INSN_CLASS_ZBB, "d,s", MATCH_CPOP, MASK_CPOP, match_opcode, 0 },
+{"min", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_MIN, MASK_MIN, match_opcode, 0 },
+{"max", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_MAX, MASK_MAX, match_opcode, 0 },
+{"minu", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_MINU, MASK_MINU, match_opcode, 0 },
+{"maxu", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_MAXU, MASK_MAXU, match_opcode, 0 },
+{"sext.b", 0, INSN_CLASS_ZBB, "d,s", MATCH_SEXT_B, MASK_SEXT_B, match_opcode, 0 },
+{"sext.b", 0, INSN_CLASS_I, "d,s", 0, (int) M_SEXTB, match_never, INSN_MACRO },
+{"sext.h", 0, INSN_CLASS_ZBB, "d,s", MATCH_SEXT_H, MASK_SEXT_H, match_opcode, 0 },
+{"sext.h", 0, INSN_CLASS_I, "d,s", 0, (int) M_SEXTH, match_never, INSN_MACRO },
+{"zext.h", 32, INSN_CLASS_ZBB, "d,s", MATCH_PACK, MASK_PACK | MASK_RS2, match_opcode, 0 },
+{"zext.h", 64, INSN_CLASS_ZBB, "d,s", MATCH_PACKW, MASK_PACKW | MASK_RS2, match_opcode, 0 },
+{"zext.h", 0, INSN_CLASS_I, "d,s", 0, (int) M_ZEXTH, match_never, INSN_MACRO },
+{"andn", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_ANDN, MASK_ANDN, match_opcode, 0 },
+{"orn", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_ORN, MASK_ORN, match_opcode, 0 },
+{"xnor", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_XNOR, MASK_XNOR, match_opcode, 0 },
+{"rol", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_ROL, MASK_ROL, match_opcode, 0 },
+{"rori", 0, INSN_CLASS_ZBB, "d,s,>", MATCH_RORI, MASK_RORI, match_opcode, 0 },
+{"ror", 0, INSN_CLASS_ZBB, "d,s,t", MATCH_ROR, MASK_ROR, match_opcode, 0 },
+{"ror", 0, INSN_CLASS_ZBB, "d,s,>", MATCH_RORI, MASK_RORI, match_opcode, INSN_ALIAS },
+{"rev8", 32, INSN_CLASS_ZBB, "d,s", MATCH_GREVI | MATCH_SHAMT_REV8_32 , MASK_GREVI | MASK_SHAMT, match_opcode, 0 },
+{"rev8", 64, INSN_CLASS_ZBB, "d,s", MATCH_GREVI | MATCH_SHAMT_REV8_64 , MASK_GREVI | MASK_SHAMT, match_opcode, 0 },
+{"orc.b", 0, INSN_CLASS_ZBB, "d,s", MATCH_GORCI | MATCH_SHAMT_ORC_B, MASK_GORCI | MASK_SHAMT, match_opcode, 0 },
+{"clzw", 64, INSN_CLASS_ZBB, "d,s", MATCH_CLZW, MASK_CLZW, match_opcode, 0 },
+{"ctzw", 64, INSN_CLASS_ZBB, "d,s", MATCH_CTZW, MASK_CTZW, match_opcode, 0 },
+{"cpopw", 64, INSN_CLASS_ZBB, "d,s", MATCH_CPOPW, MASK_CPOPW, match_opcode, 0 },
+{"rolw", 64, INSN_CLASS_ZBB, "d,s,t", MATCH_ROLW, MASK_ROLW, match_opcode, 0 },
+{"roriw", 64, INSN_CLASS_ZBB, "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, 0 },
+{"rorw", 64, INSN_CLASS_ZBB, "d,s,t", MATCH_RORW, MASK_RORW, match_opcode, 0 },
+{"rorw", 64, INSN_CLASS_ZBB, "d,s,<", MATCH_RORIW, MASK_RORIW, match_opcode, 0 },
+{"sh1add", 0, INSN_CLASS_ZBA, "d,s,t", MATCH_SH1ADD, MASK_SH1ADD, match_opcode, 0 },
+{"sh2add", 0, INSN_CLASS_ZBA, "d,s,t", MATCH_SH2ADD, MASK_SH2ADD, match_opcode, 0 },
+{"sh3add", 0, INSN_CLASS_ZBA, "d,s,t", MATCH_SH3ADD, MASK_SH3ADD, match_opcode, 0 },
+{"sh1add.uw", 64, INSN_CLASS_ZBA, "d,s,t", MATCH_SH1ADD_UW, MASK_SH1ADD_UW, match_opcode, 0 },
+{"sh2add.uw", 64, INSN_CLASS_ZBA, "d,s,t", MATCH_SH2ADD_UW, MASK_SH2ADD_UW, match_opcode, 0 },
+{"sh3add.uw", 64, INSN_CLASS_ZBA, "d,s,t", MATCH_SH3ADD_UW, MASK_SH3ADD_UW, match_opcode, 0 },
+{"zext.w", 64, INSN_CLASS_ZBA, "d,s", MATCH_ADD_UW, MASK_ADD_UW | MASK_RS2, match_opcode, INSN_ALIAS },
+{"zext.w", 64, INSN_CLASS_I, "d,s", 0, (int) M_ZEXTW, match_never, INSN_MACRO },
+{"add.uw", 64, INSN_CLASS_ZBA, "d,s,t", MATCH_ADD_UW, MASK_ADD_UW, match_opcode, 0 },
+{"slli.uw", 64, INSN_CLASS_ZBA, "d,s,>", MATCH_SLLI_UW, MASK_SLLI_UW, match_opcode, 0 },
+{"clmul", 0, INSN_CLASS_ZBC, "d,s,t", MATCH_CLMUL, MASK_CLMUL, match_opcode, 0 },
+{"clmulh", 0, INSN_CLASS_ZBC, "d,s,t", MATCH_CLMULH, MASK_CLMULH, match_opcode, 0 },
+{"clmulr", 0, INSN_CLASS_ZBC, "d,s,t", MATCH_CLMULR, MASK_CLMULR, match_opcode, 0 },
+
/* Terminate the list. */
{0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}
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