[binutils-gdb] ld: tests: add -msim when testing bfin targets
Michael Frysinger
vapier@sourceware.org
Thu Jan 14 06:09:56 GMT 2021
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=271bea6acd3759db96b33a30f110ee5e1f8146fc
commit 271bea6acd3759db96b33a30f110ee5e1f8146fc
Author: Mike Frysinger <vapier@gentoo.org>
Date: Thu Dec 9 12:06:34 2010 -0500
ld: tests: add -msim when testing bfin targets
The Blackfin ELF compiler requires the user to explicitly select a CPU
target else it will fail:
bfin-elf-gcc: error: no processor type specified for linking
Select the sim target for these tests since we should (hopefully) have
access to the simulator. At least, it's more likely than having access
to a real development board.
This makes the pass/fail numbers increase by a lot:
-# of expected passes 398
-# of unexpected failures 6
+# of expected passes 587
+# of unexpected failures 109
It looks like the vast majority of new failures are due to our omission
of COPY relocations:
/* Bfin does not currently have a COPY reloc. */
if ((h->root.u.def.section->flags & SEC_ALLOC) != 0)
{
_bfd_error_handler (_("the bfin target does not currently support the generation of copy relocations"));
return FALSE;
}
There doesn't seem to be a way to easily disable tests that cause copy
relocations though, lets just take the hit for now.
* testsuite/config/default.exp [bfin*-elf*] (gcc_B_opt): Append -msim.
Diff:
---
ld/ChangeLog | 4 ++++
ld/testsuite/config/default.exp | 5 +++++
2 files changed, 9 insertions(+)
diff --git a/ld/ChangeLog b/ld/ChangeLog
index 60a31032b77..cbcda0a4112 100644
--- a/ld/ChangeLog
+++ b/ld/ChangeLog
@@ -1,3 +1,7 @@
+2021-01-14 Mike Frysinger <vapier@gentoo.org>
+
+ * testsuite/config/default.exp [bfin*-elf*] (gcc_B_opt): Add -msim.
+
2021-01-14 Alan Modra <amodra@gmail.com>
PR 27160
diff --git a/ld/testsuite/config/default.exp b/ld/testsuite/config/default.exp
index af313bb7dc6..4090f1287c4 100644
--- a/ld/testsuite/config/default.exp
+++ b/ld/testsuite/config/default.exp
@@ -157,6 +157,11 @@ if { [istarget rx-*-*] } {
set ASFLAGS "-muse-conventional-section-names"
}
+# Blackfin ELF targets require selection of an explicit CPU. Use the sim.
+if {[istarget bfin*-elf*]} {
+ append gcc_B_opt " -msim"
+}
+
# load the utility procedures
load_lib ld-lib.exp
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