[binutils-gdb] RISC-V: Hypervisor ext: support Privileged Spec 1.12
Nelson Chu
nelsonc1225@sourceware.org
Fri Dec 24 08:21:59 GMT 2021
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=a63375ac337903d4394b2d88788353d06cf7a086
commit a63375ac337903d4394b2d88788353d06cf7a086
Author: Vineet Gupta <vineetg@rivosinc.com>
Date: Mon Dec 20 18:34:13 2021 -0800
RISC-V: Hypervisor ext: support Privileged Spec 1.12
This is the Hypervisor Extension 1.0
- Hypervisor Memory-Management Instructions
HFENCE.VVMA, HFENCE.GVMA,
- Hypervisor Virtual Machine Load and Store Instructions
HLV.B, HLV.BU, HSV.B,
HLV.H, HLV.HU, HLVX.HU, HSB.H,
HLV.W, HLV.WU, HLVX.WU, HSV.W,
HLV.D, HSV.D
- Hypervisor CSRs (some new, some address changed)
hstatus, hedeleg, hideleg, hie, hcounteren, hgeie, htval, hip, hvip,
htinst, hgeip, henvcfg, henvcfgh, hgatp, hcontext, htimedelta, htimedeltah,
vsstatus, vsie, vstvec, vsscratch, vsepc, vscause, vstval, vsip, vsatp,
Note that following were added already as part of svinval extension
support:
HINVAL.GVMA, HINVAL.VVMA
Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
Reviewed-by: Nelson Chu <nelson.chu@sifive.com>
bfd/
* cpu-riscv.c (riscv_priv_specs): Added entry for 1.12.
* cpu-riscv.h (enum riscv_spec_class): Added PRIV_SPEC_CLASS_1P12.
gas/
* config/tc-riscv.c (abort_version): Updated comment.
(validate_riscv_insn): Annotate switch-break.
* testsuite/gas/riscv/h-ext-32.d: New testcase for hypervisor.
* testsuite/gas/riscv/h-ext-32.s: Likewise.
* testsuite/gas/riscv/h-ext-64.d: Likewise.
* testsuite/gas/riscv/h-ext-64.s: Likewise.
include/
* opcode/riscv-opc.h: Added encodings for hypervisor csrs and
instrcutions.
opcodes/
* riscv-opc.c (riscv_opcodes): Added hypervisor instrcutions.
Diff:
---
bfd/cpu-riscv.c | 1 +
bfd/cpu-riscv.h | 1 +
gas/config/tc-riscv.c | 10 ++--
gas/testsuite/gas/riscv/h-ext-32.d | 82 ++++++++++++++++++++++++++++++
gas/testsuite/gas/riscv/h-ext-32.s | 73 +++++++++++++++++++++++++++
gas/testsuite/gas/riscv/h-ext-64.d | 81 ++++++++++++++++++++++++++++++
gas/testsuite/gas/riscv/h-ext-64.s | 72 ++++++++++++++++++++++++++
include/opcode/riscv-opc.h | 100 +++++++++++++++++++++++++++++++++++++
opcodes/riscv-opc.c | 21 ++++++++
9 files changed, 436 insertions(+), 5 deletions(-)
diff --git a/bfd/cpu-riscv.c b/bfd/cpu-riscv.c
index 813f2c3df8d..5038029ce01 100644
--- a/bfd/cpu-riscv.c
+++ b/bfd/cpu-riscv.c
@@ -117,6 +117,7 @@ const struct riscv_spec riscv_priv_specs[] =
{"1.9.1", PRIV_SPEC_CLASS_1P9P1},
{"1.10", PRIV_SPEC_CLASS_1P10},
{"1.11", PRIV_SPEC_CLASS_1P11},
+ {"1.12", PRIV_SPEC_CLASS_1P12},
};
/* Get the corresponding CSR version class by giving privilege
diff --git a/bfd/cpu-riscv.h b/bfd/cpu-riscv.h
index ed5ee7e60d5..b251d6312b8 100644
--- a/bfd/cpu-riscv.h
+++ b/bfd/cpu-riscv.h
@@ -32,6 +32,7 @@ enum riscv_spec_class
PRIV_SPEC_CLASS_1P9P1,
PRIV_SPEC_CLASS_1P10,
PRIV_SPEC_CLASS_1P11,
+ PRIV_SPEC_CLASS_1P12,
PRIV_SPEC_CLASS_DRAFT,
};
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index e8061217e7c..dbf0e23c456 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -82,7 +82,7 @@ struct riscv_csr_extra
enum riscv_spec_class define_version;
/* Record the CSR is aborted/invalid from which versions. If it isn't
- aborted in the current version, then it should be CSR_CLASS_VDRAFT. */
+ aborted in the current version, then it should be PRIV_SPEC_CLASS_DRAFT. */
enum riscv_spec_class abort_version;
/* The CSR may have more than one setting. */
@@ -1104,7 +1104,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
default:
goto unknown_validate_operand;
}
- break;
+ break; /* end RVC */
case 'V': /* RVV */
switch (*++oparg)
{
@@ -1128,7 +1128,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
default:
goto unknown_validate_operand;
}
- break;
+ break; /* end RVV */
case ',': break;
case '(': break;
case ')': break;
@@ -2605,7 +2605,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
default:
goto unknown_riscv_ip_operand;
}
- break;
+ break; /* end RVC */
case 'V': /* RVV */
switch (*++oparg)
@@ -2771,7 +2771,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
default:
goto unknown_riscv_ip_operand;
}
- break;
+ break; /* end RVV */
case ',':
++argnum;
diff --git a/gas/testsuite/gas/riscv/h-ext-32.d b/gas/testsuite/gas/riscv/h-ext-32.d
new file mode 100644
index 00000000000..870b847adf9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/h-ext-32.d
@@ -0,0 +1,82 @@
+#as: -march=rv32i -mpriv-spec=1.12
+#source: h-ext-32.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <.text>:
+[ ]+[0-9a-f]+:[ ]+22000073[ ]+hfence.vvma
+[ ]+[0-9a-f]+:[ ]+22050073[ ]+hfence.vvma[ ]+a0
+[ ]+[0-9a-f]+:[ ]+22b00073[ ]+hfence.vvma[ ]+zero,a1
+[ ]+[0-9a-f]+:[ ]+22c58073[ ]+hfence.vvma[ ]+a1,a2
+[ ]+[0-9a-f]+:[ ]+62000073[ ]+hfence.gvma
+[ ]+[0-9a-f]+:[ ]+62050073[ ]+hfence.gvma[ ]+a0
+[ ]+[0-9a-f]+:[ ]+62b00073[ ]+hfence.gvma[ ]+zero,a1
+[ ]+[0-9a-f]+:[ ]+62c58073[ ]+hfence.gvma[ ]+a1,a2
+[ ]+[0-9a-f]+:[ ]+6005c573[ ]+hlv.b[ ]+a0,\(a1\)
+[ ]+[0-9a-f]+:[ ]+6005c573[ ]+hlv.b[ ]+a0,\(a1\)
+[ ]+[0-9a-f]+:[ ]+6015c573[ ]+hlv.bu[ ]+a0,\(a1\)
+[ ]+[0-9a-f]+:[ ]+640645f3[ ]+hlv.h[ ]+a1,\(a2\)
+[ ]+[0-9a-f]+:[ ]+6415c5f3[ ]+hlv.hu[ ]+a1,\(a1\)
+[ ]+[0-9a-f]+:[ ]+643645f3[ ]+hlvx.hu[ ]+a1,\(a2\)
+[ ]+[0-9a-f]+:[ ]+68064673[ ]+hlv.w[ ]+a2,\(a2\)
+[ ]+[0-9a-f]+:[ ]+6836c673[ ]+hlvx.wu[ ]+a2,\(a3\)
+[ ]+[0-9a-f]+:[ ]+62a5c073[ ]+hsv.b[ ]+a0,\(a1\)
+[ ]+[0-9a-f]+:[ ]+62a5c073[ ]+hsv.b[ ]+a0,\(a1\)
+[ ]+[0-9a-f]+:[ ]+66a5c073[ ]+hsv.h[ ]+a0,\(a1\)
+[ ]+[0-9a-f]+:[ ]+6aa5c073[ ]+hsv.w[ ]+a0,\(a1\)
+[ ]+[0-9a-f]+:[ ]+60002573[ ]+csrr[ ]+a0,hstatus
+[ ]+[0-9a-f]+:[ ]+60059073[ ]+csrw[ ]+hstatus,a1
+[ ]+[0-9a-f]+:[ ]+60202573[ ]+csrr[ ]+a0,hedeleg
+[ ]+[0-9a-f]+:[ ]+60259073[ ]+csrw[ ]+hedeleg,a1
+[ ]+[0-9a-f]+:[ ]+60302573[ ]+csrr[ ]+a0,hideleg
+[ ]+[0-9a-f]+:[ ]+60359073[ ]+csrw[ ]+hideleg,a1
+[ ]+[0-9a-f]+:[ ]+60402573[ ]+csrr[ ]+a0,hie
+[ ]+[0-9a-f]+:[ ]+60459073[ ]+csrw[ ]+hie,a1
+[ ]+[0-9a-f]+:[ ]+60602573[ ]+csrr[ ]+a0,hcounteren
+[ ]+[0-9a-f]+:[ ]+60659073[ ]+csrw[ ]+hcounteren,a1
+[ ]+[0-9a-f]+:[ ]+60702573[ ]+csrr[ ]+a0,hgeie
+[ ]+[0-9a-f]+:[ ]+60759073[ ]+csrw[ ]+hgeie,a1
+[ ]+[0-9a-f]+:[ ]+64302573[ ]+csrr[ ]+a0,htval
+[ ]+[0-9a-f]+:[ ]+64359073[ ]+csrw[ ]+htval,a1
+[ ]+[0-9a-f]+:[ ]+64402573[ ]+csrr[ ]+a0,hip
+[ ]+[0-9a-f]+:[ ]+64459073[ ]+csrw[ ]+hip,a1
+[ ]+[0-9a-f]+:[ ]+64502573[ ]+csrr[ ]+a0,hvip
+[ ]+[0-9a-f]+:[ ]+64559073[ ]+csrw[ ]+hvip,a1
+[ ]+[0-9a-f]+:[ ]+64a02573[ ]+csrr[ ]+a0,htinst
+[ ]+[0-9a-f]+:[ ]+64a59073[ ]+csrw[ ]+htinst,a1
+[ ]+[0-9a-f]+:[ ]+e1202573[ ]+csrr[ ]+a0,hgeip
+[ ]+[0-9a-f]+:[ ]+e1259073[ ]+csrw[ ]+hgeip,a1
+[ ]+[0-9a-f]+:[ ]+60a02573[ ]+csrr[ ]+a0,henvcfg
+[ ]+[0-9a-f]+:[ ]+60a59073[ ]+csrw[ ]+henvcfg,a1
+[ ]+[0-9a-f]+:[ ]+61a02573[ ]+csrr[ ]+a0,henvcfgh
+[ ]+[0-9a-f]+:[ ]+61a59073[ ]+csrw[ ]+henvcfgh,a1
+[ ]+[0-9a-f]+:[ ]+68002573[ ]+csrr[ ]+a0,hgatp
+[ ]+[0-9a-f]+:[ ]+68059073[ ]+csrw[ ]+hgatp,a1
+[ ]+[0-9a-f]+:[ ]+6a802573[ ]+csrr[ ]+a0,hcontext
+[ ]+[0-9a-f]+:[ ]+6a859073[ ]+csrw[ ]+hcontext,a1
+[ ]+[0-9a-f]+:[ ]+60502573[ ]+csrr[ ]+a0,htimedelta
+[ ]+[0-9a-f]+:[ ]+60559073[ ]+csrw[ ]+htimedelta,a1
+[ ]+[0-9a-f]+:[ ]+61502573[ ]+csrr[ ]+a0,htimedeltah
+[ ]+[0-9a-f]+:[ ]+61559073[ ]+csrw[ ]+htimedeltah,a1
+[ ]+[0-9a-f]+:[ ]+20002573[ ]+csrr[ ]+a0,vsstatus
+[ ]+[0-9a-f]+:[ ]+20059073[ ]+csrw[ ]+vsstatus,a1
+[ ]+[0-9a-f]+:[ ]+20402573[ ]+csrr[ ]+a0,vsie
+[ ]+[0-9a-f]+:[ ]+20459073[ ]+csrw[ ]+vsie,a1
+[ ]+[0-9a-f]+:[ ]+20502573[ ]+csrr[ ]+a0,vstvec
+[ ]+[0-9a-f]+:[ ]+20559073[ ]+csrw[ ]+vstvec,a1
+[ ]+[0-9a-f]+:[ ]+24002573[ ]+csrr[ ]+a0,vsscratch
+[ ]+[0-9a-f]+:[ ]+24059073[ ]+csrw[ ]+vsscratch,a1
+[ ]+[0-9a-f]+:[ ]+24102573[ ]+csrr[ ]+a0,vsepc
+[ ]+[0-9a-f]+:[ ]+24159073[ ]+csrw[ ]+vsepc,a1
+[ ]+[0-9a-f]+:[ ]+24202573[ ]+csrr[ ]+a0,vscause
+[ ]+[0-9a-f]+:[ ]+24259073[ ]+csrw[ ]+vscause,a1
+[ ]+[0-9a-f]+:[ ]+24302573[ ]+csrr[ ]+a0,vstval
+[ ]+[0-9a-f]+:[ ]+24359073[ ]+csrw[ ]+vstval,a1
+[ ]+[0-9a-f]+:[ ]+24402573[ ]+csrr[ ]+a0,vsip
+[ ]+[0-9a-f]+:[ ]+24459073[ ]+csrw[ ]+vsip,a1
+[ ]+[0-9a-f]+:[ ]+28002573[ ]+csrr[ ]+a0,vsatp
+[ ]+[0-9a-f]+:[ ]+28059073[ ]+csrw[ ]+vsatp,a1
diff --git a/gas/testsuite/gas/riscv/h-ext-32.s b/gas/testsuite/gas/riscv/h-ext-32.s
new file mode 100644
index 00000000000..63b0c9a22e0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/h-ext-32.s
@@ -0,0 +1,73 @@
+ hfence.vvma
+ hfence.vvma a0
+ hfence.vvma x0, a1
+ hfence.vvma a1, a2
+ hfence.gvma
+ hfence.gvma a0
+ hfence.gvma x0, a1
+ hfence.gvma a1, a2
+
+ hlv.b a0, (a1)
+ hlv.b a0,0(a1)
+ hlv.bu a0, (a1)
+ hlv.h a1, (a2)
+ hlv.hu a1, (a1)
+ hlvx.hu a1, (a2)
+ hlv.w a2, (a2)
+ hlvx.wu a2, (a3)
+ hsv.b a0, (a1)
+ hsv.b a0,0(a1)
+ hsv.h a0, (a1)
+ hsv.w a0, (a1)
+ csrr a0, hstatus
+ csrw hstatus, a1
+ csrr a0, hedeleg
+ csrw hedeleg, a1
+ csrr a0, hideleg
+ csrw hideleg, a1
+ csrr a0, hie
+ csrw hie, a1
+ csrr a0, hcounteren
+ csrw hcounteren, a1
+ csrr a0, hgeie
+ csrw hgeie, a1
+ csrr a0, htval
+ csrw htval, a1
+ csrr a0, hip
+ csrw hip, a1
+ csrr a0, hvip
+ csrw hvip, a1
+ csrr a0, htinst
+ csrw htinst, a1
+ csrr a0, hgeip
+ csrw hgeip, a1
+ csrr a0, henvcfg
+ csrw henvcfg, a1
+ csrr a0, henvcfgh
+ csrw henvcfgh, a1
+ csrr a0, hgatp
+ csrw hgatp, a1
+ csrr a0, hcontext
+ csrw hcontext, a1
+ csrr a0, htimedelta
+ csrw htimedelta, a1
+ csrr a0, htimedeltah
+ csrw htimedeltah, a1
+ csrr a0, vsstatus
+ csrw vsstatus, a1
+ csrr a0, vsie
+ csrw vsie, a1
+ csrr a0, vstvec
+ csrw vstvec, a1
+ csrr a0, vsscratch
+ csrw vsscratch, a1
+ csrr a0, vsepc
+ csrw vsepc, a1
+ csrr a0, vscause
+ csrw vscause, a1
+ csrr a0, vstval
+ csrw vstval, a1
+ csrr a0, vsip
+ csrw vsip, a1
+ csrr a0, vsatp
+ csrw vsatp, a1
diff --git a/gas/testsuite/gas/riscv/h-ext-64.d b/gas/testsuite/gas/riscv/h-ext-64.d
new file mode 100644
index 00000000000..f948c4dc3bd
--- /dev/null
+++ b/gas/testsuite/gas/riscv/h-ext-64.d
@@ -0,0 +1,81 @@
+#as: -march=rv64i -mpriv-spec=1.12
+#source: h-ext-64.s
+#objdump: -d
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <.text>:
+[ ]+[0-9a-f]+:[ ]+22000073[ ]+hfence.vvma
+[ ]+[0-9a-f]+:[ ]+22050073[ ]+hfence.vvma[ ]+a0
+[ ]+[0-9a-f]+:[ ]+22b00073[ ]+hfence.vvma[ ]+zero,a1
+[ ]+[0-9a-f]+:[ ]+22c58073[ ]+hfence.vvma[ ]+a1,a2
+[ ]+[0-9a-f]+:[ ]+62000073[ ]+hfence.gvma
+[ ]+[0-9a-f]+:[ ]+62050073[ ]+hfence.gvma[ ]+a0
+[ ]+[0-9a-f]+:[ ]+62b00073[ ]+hfence.gvma[ ]+zero,a1
+[ ]+[0-9a-f]+:[ ]+62c58073[ ]+hfence.gvma[ ]+a1,a2
+[ ]+[0-9a-f]+:[ ]+6005c573[ ]+hlv.b[ ]+a0,\(a1\)
+[ ]+[0-9a-f]+:[ ]+6005c573[ ]+hlv.b[ ]+a0,\(a1\)
+[ ]+[0-9a-f]+:[ ]+6015c573[ ]+hlv.bu[ ]+a0,\(a1\)
+[ ]+[0-9a-f]+:[ ]+640645f3[ ]+hlv.h[ ]+a1,\(a2\)
+[ ]+[0-9a-f]+:[ ]+6415c5f3[ ]+hlv.hu[ ]+a1,\(a1\)
+[ ]+[0-9a-f]+:[ ]+643645f3[ ]+hlvx.hu[ ]+a1,\(a2\)
+[ ]+[0-9a-f]+:[ ]+68064673[ ]+hlv.w[ ]+a2,\(a2\)
+[ ]+[0-9a-f]+:[ ]+6816c673[ ]+hlv.wu[ ]+a2,\(a3\)
+[ ]+[0-9a-f]+:[ ]+6836c673[ ]+hlvx.wu[ ]+a2,\(a3\)
+[ ]+[0-9a-f]+:[ ]+6c0746f3[ ]+hlv.d[ ]+a3,\(a4\)
+[ ]+[0-9a-f]+:[ ]+62a5c073[ ]+hsv.b[ ]+a0,\(a1\)
+[ ]+[0-9a-f]+:[ ]+62a5c073[ ]+hsv.b[ ]+a0,\(a1\)
+[ ]+[0-9a-f]+:[ ]+66a5c073[ ]+hsv.h[ ]+a0,\(a1\)
+[ ]+[0-9a-f]+:[ ]+6aa5c073[ ]+hsv.w[ ]+a0,\(a1\)
+[ ]+[0-9a-f]+:[ ]+6ea5c073[ ]+hsv.d[ ]+a0,\(a1\)
+[ ]+[0-9a-f]+:[ ]+60002573[ ]+csrr[ ]+a0,hstatus
+[ ]+[0-9a-f]+:[ ]+60059073[ ]+csrw[ ]+hstatus,a1
+[ ]+[0-9a-f]+:[ ]+60202573[ ]+csrr[ ]+a0,hedeleg
+[ ]+[0-9a-f]+:[ ]+60259073[ ]+csrw[ ]+hedeleg,a1
+[ ]+[0-9a-f]+:[ ]+60302573[ ]+csrr[ ]+a0,hideleg
+[ ]+[0-9a-f]+:[ ]+60359073[ ]+csrw[ ]+hideleg,a1
+[ ]+[0-9a-f]+:[ ]+60402573[ ]+csrr[ ]+a0,hie
+[ ]+[0-9a-f]+:[ ]+60459073[ ]+csrw[ ]+hie,a1
+[ ]+[0-9a-f]+:[ ]+60602573[ ]+csrr[ ]+a0,hcounteren
+[ ]+[0-9a-f]+:[ ]+60659073[ ]+csrw[ ]+hcounteren,a1
+[ ]+[0-9a-f]+:[ ]+60702573[ ]+csrr[ ]+a0,hgeie
+[ ]+[0-9a-f]+:[ ]+60759073[ ]+csrw[ ]+hgeie,a1
+[ ]+[0-9a-f]+:[ ]+64302573[ ]+csrr[ ]+a0,htval
+[ ]+[0-9a-f]+:[ ]+64359073[ ]+csrw[ ]+htval,a1
+[ ]+[0-9a-f]+:[ ]+64402573[ ]+csrr[ ]+a0,hip
+[ ]+[0-9a-f]+:[ ]+64459073[ ]+csrw[ ]+hip,a1
+[ ]+[0-9a-f]+:[ ]+64502573[ ]+csrr[ ]+a0,hvip
+[ ]+[0-9a-f]+:[ ]+64559073[ ]+csrw[ ]+hvip,a1
+[ ]+[0-9a-f]+:[ ]+64a02573[ ]+csrr[ ]+a0,htinst
+[ ]+[0-9a-f]+:[ ]+64a59073[ ]+csrw[ ]+htinst,a1
+[ ]+[0-9a-f]+:[ ]+e1202573[ ]+csrr[ ]+a0,hgeip
+[ ]+[0-9a-f]+:[ ]+e1259073[ ]+csrw[ ]+hgeip,a1
+[ ]+[0-9a-f]+:[ ]+60a02573[ ]+csrr[ ]+a0,henvcfg
+[ ]+[0-9a-f]+:[ ]+60a59073[ ]+csrw[ ]+henvcfg,a1
+[ ]+[0-9a-f]+:[ ]+68002573[ ]+csrr[ ]+a0,hgatp
+[ ]+[0-9a-f]+:[ ]+68059073[ ]+csrw[ ]+hgatp,a1
+[ ]+[0-9a-f]+:[ ]+6a802573[ ]+csrr[ ]+a0,hcontext
+[ ]+[0-9a-f]+:[ ]+6a859073[ ]+csrw[ ]+hcontext,a1
+[ ]+[0-9a-f]+:[ ]+60502573[ ]+csrr[ ]+a0,htimedelta
+[ ]+[0-9a-f]+:[ ]+60559073[ ]+csrw[ ]+htimedelta,a1
+[ ]+[0-9a-f]+:[ ]+20002573[ ]+csrr[ ]+a0,vsstatus
+[ ]+[0-9a-f]+:[ ]+20059073[ ]+csrw[ ]+vsstatus,a1
+[ ]+[0-9a-f]+:[ ]+20402573[ ]+csrr[ ]+a0,vsie
+[ ]+[0-9a-f]+:[ ]+20459073[ ]+csrw[ ]+vsie,a1
+[ ]+[0-9a-f]+:[ ]+20502573[ ]+csrr[ ]+a0,vstvec
+[ ]+[0-9a-f]+:[ ]+20559073[ ]+csrw[ ]+vstvec,a1
+[ ]+[0-9a-f]+:[ ]+24002573[ ]+csrr[ ]+a0,vsscratch
+[ ]+[0-9a-f]+:[ ]+24059073[ ]+csrw[ ]+vsscratch,a1
+[ ]+[0-9a-f]+:[ ]+24102573[ ]+csrr[ ]+a0,vsepc
+[ ]+[0-9a-f]+:[ ]+24159073[ ]+csrw[ ]+vsepc,a1
+[ ]+[0-9a-f]+:[ ]+24202573[ ]+csrr[ ]+a0,vscause
+[ ]+[0-9a-f]+:[ ]+24259073[ ]+csrw[ ]+vscause,a1
+[ ]+[0-9a-f]+:[ ]+24302573[ ]+csrr[ ]+a0,vstval
+[ ]+[0-9a-f]+:[ ]+24359073[ ]+csrw[ ]+vstval,a1
+[ ]+[0-9a-f]+:[ ]+24402573[ ]+csrr[ ]+a0,vsip
+[ ]+[0-9a-f]+:[ ]+24459073[ ]+csrw[ ]+vsip,a1
+[ ]+[0-9a-f]+:[ ]+28002573[ ]+csrr[ ]+a0,vsatp
+[ ]+[0-9a-f]+:[ ]+28059073[ ]+csrw[ ]+vsatp,a1
diff --git a/gas/testsuite/gas/riscv/h-ext-64.s b/gas/testsuite/gas/riscv/h-ext-64.s
new file mode 100644
index 00000000000..3f7a5b7667d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/h-ext-64.s
@@ -0,0 +1,72 @@
+ hfence.vvma
+ hfence.vvma a0
+ hfence.vvma x0, a1
+ hfence.vvma a1, a2
+ hfence.gvma
+ hfence.gvma a0
+ hfence.gvma x0, a1
+ hfence.gvma a1, a2
+
+ hlv.b a0, (a1)
+ hlv.b a0,0(a1)
+ hlv.bu a0, (a1)
+ hlv.h a1, (a2)
+ hlv.hu a1, (a1)
+ hlvx.hu a1, (a2)
+ hlv.w a2, (a2)
+ hlv.wu a2, (a3)
+ hlvx.wu a2, (a3)
+ hlv.d a3, (a4)
+ hsv.b a0, (a1)
+ hsv.b a0,0(a1)
+ hsv.h a0, (a1)
+ hsv.w a0, (a1)
+ hsv.d a0, (a1)
+ csrr a0, hstatus
+ csrw hstatus, a1
+ csrr a0, hedeleg
+ csrw hedeleg, a1
+ csrr a0, hideleg
+ csrw hideleg, a1
+ csrr a0, hie
+ csrw hie, a1
+ csrr a0, hcounteren
+ csrw hcounteren, a1
+ csrr a0, hgeie
+ csrw hgeie, a1
+ csrr a0, htval
+ csrw htval, a1
+ csrr a0, hip
+ csrw hip, a1
+ csrr a0, hvip
+ csrw hvip, a1
+ csrr a0, htinst
+ csrw htinst, a1
+ csrr a0, hgeip
+ csrw hgeip, a1
+ csrr a0, henvcfg
+ csrw henvcfg, a1
+ csrr a0, hgatp
+ csrw hgatp, a1
+ csrr a0, hcontext
+ csrw hcontext, a1
+ csrr a0, htimedelta
+ csrw htimedelta, a1
+ csrr a0, vsstatus
+ csrw vsstatus, a1
+ csrr a0, vsie
+ csrw vsie, a1
+ csrr a0, vstvec
+ csrw vstvec, a1
+ csrr a0, vsscratch
+ csrw vsscratch, a1
+ csrr a0, vsepc
+ csrw vsepc, a1
+ csrr a0, vscause
+ csrw vscause, a1
+ csrr a0, vstval
+ csrw vstval, a1
+ csrr a0, vsip
+ csrw vsip, a1
+ csrr a0, vsatp
+ csrw vsatp, a1
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 2486f13c9fd..6ca2f8d9309 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -1998,6 +1998,37 @@
#define MASK_HINVAL_VVMA 0xfe007fff
#define MATCH_HINVAL_GVMA 0x66000073
#define MASK_HINVAL_GVMA 0xfe007fff
+/* Hypervisor instruction. */
+#define MATCH_HFENCE_VVMA 0x22000073
+#define MASK_HFENCE_VVMA 0xfe007fff
+#define MATCH_HFENCE_GVMA 0x62000073
+#define MASK_HFENCE_GVMA 0xfe007fff
+#define MATCH_HLV_B 0x60004073
+#define MASK_HLV_B 0xfff0707f
+#define MATCH_HLV_H 0x64004073
+#define MASK_HLV_H 0xfff0707f
+#define MATCH_HLV_W 0x68004073
+#define MASK_HLV_W 0xfff0707f
+#define MATCH_HLV_D 0x6c004073
+#define MASK_HLV_D 0xfff0707f
+#define MATCH_HLV_BU 0x60104073
+#define MASK_HLV_BU 0xfff0707f
+#define MATCH_HLV_HU 0x64104073
+#define MASK_HLV_HU 0xfff0707f
+#define MATCH_HLV_WU 0x68104073
+#define MASK_HLV_WU 0xfff0707f
+#define MATCH_HLVX_HU 0x64304073
+#define MASK_HLVX_HU 0xfff0707f
+#define MATCH_HLVX_WU 0x68304073
+#define MASK_HLVX_WU 0xfff0707f
+#define MATCH_HSV_B 0x62004073
+#define MASK_HSV_B 0xfe007fff
+#define MATCH_HSV_H 0x66004073
+#define MASK_HSV_H 0xfe007fff
+#define MATCH_HSV_W 0x6a004073
+#define MASK_HSV_W 0xfe007fff
+#define MATCH_HSV_D 0x6e004073
+#define MASK_HSV_D 0xfe007fff
/* Privileged CSR addresses. */
#define CSR_USTATUS 0x0
#define CSR_UIE 0x4
@@ -2211,6 +2242,33 @@
#define CSR_MHPMEVENT29 0x33d
#define CSR_MHPMEVENT30 0x33e
#define CSR_MHPMEVENT31 0x33f
+/* Hypervisor Extension v1.0 (Privileged spec 1.12). */
+#define CSR_HSTATUS 0x600
+#define CSR_HEDELEG 0x602
+#define CSR_HIDELEG 0x603
+#define CSR_HIE 0x604
+#define CSR_HCOUNTEREN 0x606
+#define CSR_HGEIE 0x607
+#define CSR_HTVAL 0x643
+#define CSR_HIP 0x644
+#define CSR_HVIP 0x645
+#define CSR_HTINST 0x64a
+#define CSR_HGEIP 0xe12
+#define CSR_HENVCFG 0x60a
+#define CSR_HENVCFGH 0x61a
+#define CSR_HGATP 0x680
+#define CSR_HCONTEXT 0x6a8
+#define CSR_HTIMEDELTA 0x605
+#define CSR_HTIMEDELTAH 0x615
+#define CSR_VSSTATUS 0x200
+#define CSR_VSIE 0x204
+#define CSR_VSTVEC 0x205
+#define CSR_VSSCRATCH 0x240
+#define CSR_VSEPC 0x241
+#define CSR_VSCAUSE 0x242
+#define CSR_VSTVAL 0x243
+#define CSR_VSIP 0x244
+#define CSR_VSATP 0x280
#define CSR_MBASE 0x380
#define CSR_MBOUND 0x381
#define CSR_MIBASE 0x382
@@ -2555,6 +2613,21 @@ DECLARE_INSN(sfence_w_inval, MATCH_SFENCE_W_INVAL, MASK_SFENCE_W_INVAL)
DECLARE_INSN(sfence_inval_ir, MATCH_SFENCE_INVAL_IR, MASK_SFENCE_INVAL_IR)
DECLARE_INSN(hinval_vvma, MATCH_HINVAL_VVMA, MASK_HINVAL_VVMA)
DECLARE_INSN(hinval_gvma, MATCH_HINVAL_GVMA, MASK_HINVAL_GVMA)
+DECLARE_INSN(hfence_vvma, MATCH_HFENCE_VVMA, MASK_HFENCE_VVMA)
+DECLARE_INSN(hfence_gvma, MATCH_HFENCE_GVMA, MASK_HFENCE_GVMA)
+DECLARE_INSN(hlv_b, MATCH_HLV_B, MASK_HLV_B)
+DECLARE_INSN(hlv_h, MATCH_HLV_H, MASK_HLV_H)
+DECLARE_INSN(hlv_w, MATCH_HLV_W, MASK_HLV_W)
+DECLARE_INSN(hlv_d, MATCH_HLV_D, MASK_HLV_D)
+DECLARE_INSN(hlv_bu, MATCH_HLV_BU, MASK_HLV_BU)
+DECLARE_INSN(hlv_hu, MATCH_HLV_HU, MASK_HLV_HU)
+DECLARE_INSN(hlv_wu, MATCH_HLV_WU, MASK_HLV_WU)
+DECLARE_INSN(hlvx_hu, MATCH_HLVX_HU, MASK_HLVX_HU)
+DECLARE_INSN(hlvx_wu, MATCH_HLVX_WU, MASK_HLVX_WU)
+DECLARE_INSN(hsv_b, MATCH_HSV_B, MASK_HSV_B)
+DECLARE_INSN(hsv_h, MATCH_HSV_H, MASK_HSV_H)
+DECLARE_INSN(hsv_w, MATCH_HSV_W, MASK_HSV_W)
+DECLARE_INSN(hsv_d, MATCH_HSV_D, MASK_HSV_D)
#endif /* DECLARE_INSN */
#ifdef DECLARE_CSR
/* Privileged CSRs. */
@@ -2770,6 +2843,33 @@ DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PR
DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_DRAFT)
+/* Hypervisor Ext v1.0 (Privileged spec 1.12). */
+DECLARE_CSR(hstatus, CSR_HSTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hedeleg, CSR_HEDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hideleg, CSR_HIDELEG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hie, CSR_HIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hcounteren, CSR_HCOUNTEREN, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hgeie, CSR_HGEIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(htval, CSR_HTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hip, CSR_HIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hvip, CSR_HVIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(htinst, CSR_HTINST, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hgeip, CSR_HGEIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(henvcfg, CSR_HENVCFG, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(henvcfgh, CSR_HENVCFGH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hgatp, CSR_HGATP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(hcontext, CSR_HCONTEXT, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(htimedelta, CSR_HTIMEDELTA, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(htimedeltah, CSR_HTIMEDELTAH, CSR_CLASS_I_32, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(vsstatus, CSR_VSSTATUS, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(vsie, CSR_VSIE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(vstvec, CSR_VSTVEC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(vsscratch, CSR_VSSCRATCH, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(vsepc, CSR_VSEPC, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(vscause, CSR_VSCAUSE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(vstval, CSR_VSTVAL, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(vsip, CSR_VSIP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
+DECLARE_CSR(vsatp, CSR_VSATP, CSR_CLASS_I, PRIV_SPEC_CLASS_1P12, PRIV_SPEC_CLASS_DRAFT)
/* Dropped CSRs. */
DECLARE_CSR(mbase, CSR_MBASE, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
DECLARE_CSR(mbound, CSR_MBOUND, CSR_CLASS_I, PRIV_SPEC_CLASS_1P9P1, PRIV_SPEC_CLASS_1P10)
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index f220006fc93..4735b90fccf 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -1732,6 +1732,27 @@ const struct riscv_opcode riscv_opcodes[] =
{"hinval.vvma", 0, INSN_CLASS_SVINVAL, "s,t", MATCH_HINVAL_VVMA, MASK_HINVAL_VVMA, match_opcode, 0 },
{"hinval.gvma", 0, INSN_CLASS_SVINVAL, "s,t", MATCH_HINVAL_GVMA, MASK_HINVAL_GVMA, match_opcode, 0 },
+/* Hypervisor instructions. */
+{"hfence.vvma", 0, INSN_CLASS_I, "", MATCH_HFENCE_VVMA, MASK_HFENCE_VVMA|MASK_RS1|MASK_RS2, match_opcode, INSN_ALIAS },
+{"hfence.vvma", 0, INSN_CLASS_I, "s", MATCH_HFENCE_VVMA, MASK_HFENCE_VVMA|MASK_RS2, match_opcode, INSN_ALIAS },
+{"hfence.vvma", 0, INSN_CLASS_I, "s,t", MATCH_HFENCE_VVMA, MASK_HFENCE_VVMA, match_opcode, 0 },
+{"hfence.gvma", 0, INSN_CLASS_I, "", MATCH_HFENCE_GVMA, MASK_HFENCE_GVMA|MASK_RS1|MASK_RS2, match_opcode, INSN_ALIAS },
+{"hfence.gvma", 0, INSN_CLASS_I, "s", MATCH_HFENCE_GVMA, MASK_HFENCE_GVMA|MASK_RS2, match_opcode, INSN_ALIAS },
+{"hfence.gvma", 0, INSN_CLASS_I, "s,t", MATCH_HFENCE_GVMA, MASK_HFENCE_GVMA, match_opcode, 0 },
+{"hlv.b", 0, INSN_CLASS_I, "d,0(s)", MATCH_HLV_B, MASK_HLV_B, match_opcode, INSN_DREF|INSN_1_BYTE },
+{"hlv.bu", 0, INSN_CLASS_I, "d,0(s)", MATCH_HLV_BU, MASK_HLV_BU, match_opcode, INSN_DREF|INSN_1_BYTE },
+{"hlv.h", 0, INSN_CLASS_I, "d,0(s)", MATCH_HLV_H, MASK_HLV_H, match_opcode, INSN_DREF|INSN_2_BYTE },
+{"hlv.hu", 0, INSN_CLASS_I, "d,0(s)", MATCH_HLV_HU, MASK_HLV_HU, match_opcode, INSN_DREF|INSN_2_BYTE },
+{"hlvx.hu", 0, INSN_CLASS_I, "d,0(s)", MATCH_HLVX_HU, MASK_HLVX_HU, match_opcode, INSN_DREF|INSN_2_BYTE },
+{"hlv.w", 0, INSN_CLASS_I, "d,0(s)", MATCH_HLV_W, MASK_HLV_W, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"hlv.wu", 64, INSN_CLASS_I, "d,0(s)", MATCH_HLV_WU, MASK_HLV_WU, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"hlvx.wu", 0, INSN_CLASS_I, "d,0(s)", MATCH_HLVX_WU, MASK_HLVX_WU, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"hlv.d", 64, INSN_CLASS_I, "d,0(s)", MATCH_HLV_D, MASK_HLV_D, match_opcode, INSN_DREF|INSN_8_BYTE },
+{"hsv.b", 0, INSN_CLASS_I, "t,0(s)", MATCH_HSV_B, MASK_HSV_B, match_opcode, INSN_DREF|INSN_1_BYTE },
+{"hsv.h", 0, INSN_CLASS_I, "t,0(s)", MATCH_HSV_H, MASK_HSV_H, match_opcode, INSN_DREF|INSN_2_BYTE },
+{"hsv.w", 0, INSN_CLASS_I, "t,0(s)", MATCH_HSV_W, MASK_HSV_W, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"hsv.d", 64, INSN_CLASS_I, "t,0(s)", MATCH_HSV_D, MASK_HSV_D, match_opcode, INSN_DREF|INSN_8_BYTE },
+
/* Terminate the list. */
{0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}
};
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