[binutils-gdb] AArch64: Fix Diagnostic messaging for LD/ST Exclusive.
Tamar Christina
tnfchris@sourceware.org
Fri Apr 9 11:37:20 GMT 2021
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=dd17020328b4ebf45be26eed156fba3d269096f6
commit dd17020328b4ebf45be26eed156fba3d269096f6
Author: Tejas Belagod <tejas.belagod@arm.com>
Date: Fri Apr 9 12:29:32 2021 +0100
AArch64: Fix Diagnostic messaging for LD/ST Exclusive.
A summary of what this patch set fixes:
For instructions
STXR w0,x2,[x0]
STLXR w0,x2,[x0]
The warning we emit currently is misleading:
Warning: unpredictable: identical transfer and status registers --`stlxr w0,x2,[x0]'
Warning: unpredictable: identical transfer and status registers --`stxr w0,x2,[x0]'
it ought to be:
Warning: unpredictable: identical base and status registers --`stlxr w0,x2,[x0]'
Warning: unpredictable: identical base and status registers --`stxr w0,x2,[x0]'
For instructions:
ldaxp x0,x0,[x0]
ldxp x0,x0,[x0]
The warning we emit is incorrect
Warning: unpredictable: identical transfer and status registers --`ldaxp x0,x0,[x0]'
Warning: unpredictable: identical transfer and status registers --`ldxp x0,x0,[x0]'
it ought to be:
Warning: unpredictable load of register pair -- `ldaxp x0,x0,[x0]'
Warning: unpredictable load of register pair -- `ldxp x0,x0,[x0]'
For instructions
stlxp w0, x2, x2, [x0]
stxp w0, x2, x2, [x0]
We don't emit any warning when it ought to be:
Warning: unpredictable: identical base and status registers --`stlxp w0,x2,x2,[x0]'
Warning: unpredictable: identical base and status registers --`stxp w0,x2,x2,[x0]'
gas/ChangeLog:
2021-04-09 Tejas Belagod <tejas.belagod@arm.com>
* config/tc-aarch64.c (warn_unpredictable_ldst): Clean-up diagnostic messages
for LD/ST Exclusive instructions.
* testsuite/gas/aarch64/diagnostic.s: Add a diagnostic test for STLXP.
* testsuite/gas/aarch64/diagnostic.l: Fix-up test after message clean-up.
Diff:
---
gas/ChangeLog | 7 +++++
gas/config/tc-aarch64.c | 47 ++++++++++++++++++++++++++++------
gas/testsuite/gas/aarch64/diagnostic.l | 12 ++++-----
gas/testsuite/gas/aarch64/diagnostic.s | 1 +
4 files changed, 53 insertions(+), 14 deletions(-)
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 4efdc333174..13e427284ec 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,10 @@
+2021-04-09 Tejas Belagod <tejas.belagod@arm.com>
+
+ * config/tc-aarch64.c (warn_unpredictable_ldst): Clean-up diagnostic messages
+ for LD/ST Exclusive instructions.
+ * testsuite/gas/aarch64/diagnostic.s: Add a diagnostic test for STLXP.
+ * testsuite/gas/aarch64/diagnostic.l: Fix-up test after message clean-up.
+
2021-04-09 Alan Modra <amodra@gmail.com>
* testsuite/gas/ppc/prefix-pcrel.d: Update expected output.
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index f67ee1e8139..69705521f00 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -7156,18 +7156,49 @@ warn_unpredictable_ldst (aarch64_instruction *instr, char *str)
break;
case ldstexcl:
- /* It is unpredictable if the destination and status registers are the
- same. */
if ((aarch64_get_operand_class (opnds[0].type)
== AARCH64_OPND_CLASS_INT_REG)
&& (aarch64_get_operand_class (opnds[1].type)
- == AARCH64_OPND_CLASS_INT_REG)
- && (opnds[0].reg.regno == opnds[1].reg.regno
- || opnds[0].reg.regno == opnds[2].reg.regno))
- as_warn (_("unpredictable: identical transfer and status registers"
- " --`%s'"),
- str);
+ == AARCH64_OPND_CLASS_INT_REG))
+ {
+ if ((opcode->opcode & (1 << 22)))
+ {
+ /* It is unpredictable if load-exclusive pair with Rt == Rt2. */
+ if ((opcode->opcode & (1 << 21))
+ && opnds[0].reg.regno == opnds[1].reg.regno)
+ as_warn (_("unpredictable load of register pair -- `%s'"), str);
+ }
+ else
+ {
+ /* Store-Exclusive is unpredictable if Rt == Rs. */
+ if (opnds[0].reg.regno == opnds[1].reg.regno)
+ as_warn
+ (_("unpredictable: identical transfer and status registers"
+ " --`%s'"),str);
+ if (opnds[0].reg.regno == opnds[2].reg.regno)
+ {
+ if (!(opcode->opcode & (1 << 21)))
+ /* Store-Exclusive is unpredictable if Rn == Rs. */
+ as_warn
+ (_("unpredictable: identical base and status registers"
+ " --`%s'"),str);
+ else
+ /* Store-Exclusive pair is unpredictable if Rt2 == Rs. */
+ as_warn
+ (_("unpredictable: "
+ "identical transfer and status registers"
+ " --`%s'"),str);
+ }
+
+ /* Store-Exclusive pair is unpredictable if Rn == Rs. */
+ if ((opcode->opcode & (1 << 21))
+ && opnds[0].reg.regno == opnds[3].reg.regno
+ && opnds[3].reg.regno != REG_SP)
+ as_warn (_("unpredictable: identical base and status registers"
+ " --`%s'"),str);
+ }
+ }
break;
default:
diff --git a/gas/testsuite/gas/aarch64/diagnostic.l b/gas/testsuite/gas/aarch64/diagnostic.l
index b5f304af70b..5158d41cd43 100644
--- a/gas/testsuite/gas/aarch64/diagnostic.l
+++ b/gas/testsuite/gas/aarch64/diagnostic.l
@@ -175,11 +175,11 @@
[^:]*:304: Warning: unpredictable: identical transfer and status registers --`stlxrb w26,w26,\[x0\]'
[^:]*:305: Warning: unpredictable: identical transfer and status registers --`stlxrh w26,w26,\[x1\]'
[^:]*:306: Warning: unpredictable: identical transfer and status registers --`stlxr w26,w26,\[x2\]'
-[^:]*:307: Warning: unpredictable: identical transfer and status registers --`stlxrb w26,w27,\[x26\]'
-[^:]*:308: Warning: unpredictable: identical transfer and status registers --`stlxrh w26,w27,\[x26\]'
-[^:]*:309: Warning: unpredictable: identical transfer and status registers --`stlxr w26,w27,\[x26\]'
-[^:]*:310: Warning: unpredictable: identical transfer and status registers --`stlxr w26,x27,\[x26\]'
+[^:]*:307: Warning: unpredictable: identical base and status registers --`stlxrb w26,w27,\[x26\]'
+[^:]*:308: Warning: unpredictable: identical base and status registers --`stlxrh w26,w27,\[x26\]'
+[^:]*:309: Warning: unpredictable: identical base and status registers --`stlxr w26,w27,\[x26\]'
+[^:]*:310: Warning: unpredictable: identical base and status registers --`stlxr w26,x27,\[x26\]'
[^:]*:311: Warning: unpredictable: identical transfer and status registers --`stlxr w26,x26,\[x3\]'
-[^:]*:312: Warning: unpredictable: identical transfer and status registers --`ldxp x26,x26,\[x5\]'
-[^:]*:313: Warning: unpredictable: identical transfer and status registers --`ldxp x26,x1,\[x26\]'
+[^:]*:312: Warning: unpredictable load of register pair -- `ldxp x26,x26,\[x5\]'
[^:]*:314: Error: expected element type rather than vector type at operand 1 -- `st4 {v0\.16b-v3\.16b}\[4\],\[x0\]'
+[^:]*:315: Warning: unpredictable: identical base and status registers --`stlxp w3,w26,w26,\[x3\]'
diff --git a/gas/testsuite/gas/aarch64/diagnostic.s b/gas/testsuite/gas/aarch64/diagnostic.s
index 21cbc53d897..0ebe85ac59d 100644
--- a/gas/testsuite/gas/aarch64/diagnostic.s
+++ b/gas/testsuite/gas/aarch64/diagnostic.s
@@ -312,3 +312,4 @@
ldxp x26, x26, [x5]
ldxp x26, x1, [x26]
st4 {v0.16b-v3.16b}[4], [x0]
+ stlxp w3, w26, w26, [x3]
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