https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=fd195909ce14c7e852319613e7ec6a9a6e7b99ea
commit fd195909ce14c7e852319613e7ec6a9a6e7b99ea
Author: Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
Date: Wed Oct 28 14:01:36 2020 +0000
aarch64: Add DSB instruction Armv8.7-a variant
This patch adds new variant (nXS) of DSB memory barrier instruction
available in Armv8.7-a. New nXS variant has different encoding in
comparison with pre Armv8.7-a DSB memory barrier variant thus new
instruction and new operand was added.
DSB memory nXS barrier variant specifies the limitation on the barrier
operation. Allowed values are:
DSB SYnXS|#28
DSB ISHnXS|#24
DSB NSHnXS|#20
DSB OSHnXS|#16
Please note that till now, for barriers, barrier operation was encoded in
4-bit unsigned immediate CRm field (in the range 0 to 15).
For DSB memory nXS barrier variant, barrier operation is a 5-bit unsigned
assembly instruction immediate, encoded in instruction in two bits CRm<3:2>:
CRm<3:2> #imm
00 16
01 20
10 24
11 28
This patch extends current AArch64 barrier instructions with above mapping.
Notable patch changes include:
+ New DSB memory barrier variant encoding for Armv8.7-a.
+ New operand BARRIER_DSB_NXS for above instruction in order to
distinguish between existing and new DSB instruction flavour.
+ New set of DSB nXS barrier options.
+ New instruction inserter and extractor map between instruction
immediate 5-bit value and 2-bit CRm field of the instruction itself (see
FLD_CRm_dsb_nxs).
+ Regeneration of aarch64-[asm|dis|opc]-2.c files.
+ Test cases to cover new instruction assembling and disassembling.
For more details regarding DSB memory barrier instruction and its
Armv8.7-a flavour please refer to Arm A64 Instruction set documentation
for Armv8-A architecture profile, see document pages 132-133 of [0].
[0]: https://developer.arm.com/docs/ddi0596/i
gas/ChangeLog:
2020-10-23 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* NEWS: Docs update.
* config/tc-aarch64.c (parse_operands): Add
AARCH64_OPND_BARRIER_DSB_NXS handler.
(md_begin): Add content of aarch64_barrier_dsb_nxs_options to
aarch64_barrier_opt_hsh hash.
* testsuite/gas/aarch64/system-4-invalid.d: New test.
* testsuite/gas/aarch64/system-4-invalid.l: New test.
* testsuite/gas/aarch64/system-4-invalid.s: New test.
* testsuite/gas/aarch64/system-4.d: New test.
* testsuite/gas/aarch64/system-4.s: New test.
include/ChangeLog:
2020-10-23 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): New operand
AARCH64_OPND_BARRIER_DSB_NXS.
(aarch64_barrier_dsb_nxs_options): Declare DSB nXS options.
opcodes/ChangeLog:
2020-10-23 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* aarch64-asm.c (aarch64_ins_barrier_dsb_nxs): New inserter.
* aarch64-asm.h (AARCH64_DECL_OPD_INSERTER): New inserter
ins_barrier_dsb_nx.
* aarch64-dis.c (aarch64_ext_barrier_dsb_nxs): New extractor.
* aarch64-dis.h (AARCH64_DECL_OPD_EXTRACTOR): New extractor
ext_barrier_dsb_nx.
* aarch64-opc.c (aarch64_print_operand): New options table
aarch64_barrier_dsb_nxs_options.
* aarch64-opc.h (enum aarch64_field_kind): New field name FLD_CRm_dsb_nxs.
* aarch64-tbl.h (struct aarch64_opcode): Define DSB nXS barrier
Armv8.7-a instruction.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
Diff:
---
gas/NEWS | 2 +
gas/config/tc-aarch64.c | 47 +
gas/testsuite/gas/aarch64/system-4-invalid.d | 3 +
gas/testsuite/gas/aarch64/system-4-invalid.l | 11 +
gas/testsuite/gas/aarch64/system-4-invalid.s | 16 +
gas/testsuite/gas/aarch64/system-4.d | 16 +
gas/testsuite/gas/aarch64/system-4.s | 12 +
include/opcode/aarch64.h | 2 +
opcodes/aarch64-asm-2.c | 287 +--
opcodes/aarch64-asm.c | 15 +
opcodes/aarch64-asm.h | 1 +
opcodes/aarch64-dis-2.c | 2614 +++++++++++++-------------
opcodes/aarch64-dis.c | 15 +
opcodes/aarch64-dis.h | 1 +
opcodes/aarch64-opc-2.c | 17 +-
opcodes/aarch64-opc.c | 10 +
opcodes/aarch64-opc.h | 3 +-
opcodes/aarch64-tbl.h | 5 +
18 files changed, 1622 insertions(+), 1455 deletions(-)
diff --git a/gas/NEWS b/gas/NEWS
index 07fe535900c..b993464a67c 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -21,6 +21,8 @@
* Add support for Armv8-R and Armv8.7-A AArch64.
+* Add support for DSB memory nXS barrier instruction for Armv8.7 AArch64.
+
* Add support for Intel TDX instructions.
* Add support for Intel Key Locker instructions.
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index d17d118cc69..2ec1af4de15 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -6686,12 +6686,49 @@ parse_operands (char *str, const aarch64_opcode *opcode)
backtrack_pos = 0;
goto failure;
}
+ if (val != PARSE_FAIL
+ && operands[i] == AARCH64_OPND_BARRIER)
+ {
+ /* Regular barriers accept options CRm (C0-C15).
+ DSB nXS barrier variant accepts values > 15. */
+ po_imm_or_fail (0, 15);
+ }
/* This is an extension to accept a 0..15 immediate. */
if (val == PARSE_FAIL)
po_imm_or_fail (0, 15);
info->barrier = aarch64_barrier_options + val;
break;
+ case AARCH64_OPND_BARRIER_DSB_NXS:
+ val = parse_barrier (&str);
+ if (val != PARSE_FAIL)
+ {
+ /* DSB nXS barrier variant accept only <option>nXS qualifiers. */
+ if (!(val == 16 || val == 20 || val == 24 || val == 28))
+ {
+ set_syntax_error (_("the specified option is not accepted in DSB"));
+ /* Turn off backtrack as this optional operand is present. */
+ backtrack_pos = 0;
+ goto failure;
+ }
+ }
+ else
+ {
+ /* DSB nXS barrier variant accept 5-bit unsigned immediate, with
+ possible values 16, 20, 24 or 28 , encoded as val<3:2>. */
+ if (! parse_constant_immediate (&str, &val, imm_reg_type))
+ goto failure;
+ if (!(val == 16 || val == 20 || val == 24 || val == 28))
+ {
+ set_syntax_error (_("immediate value must be 16, 20, 24, 28"));
+ goto failure;
+ }
+ }
+ /* Option index is encoded as 2-bit value in val<3:2>. */
+ val = (val >> 2) - 4;
+ info->barrier = aarch64_barrier_dsb_nxs_options + val;
+ break;
+
case AARCH64_OPND_PRFOP:
val = parse_pldop (&str);
/* This is an extension to accept a 0..31 immediate. */
@@ -8782,6 +8819,16 @@ md_begin (void)
(void *) (aarch64_barrier_options + i));
}
+ for (i = 0; i < ARRAY_SIZE (aarch64_barrier_dsb_nxs_options); i++)
+ {
+ const char *name = aarch64_barrier_dsb_nxs_options[i].name;
+ checked_hash_insert (aarch64_barrier_opt_hsh, name,
+ (void *) (aarch64_barrier_dsb_nxs_options + i));
+ /* Also hash the name in the upper case. */
+ checked_hash_insert (aarch64_barrier_opt_hsh, get_upper_str (name),
+ (void *) (aarch64_barrier_dsb_nxs_options + i));
+ }
+
for (i = 0; i < ARRAY_SIZE (aarch64_prfops); i++)
{
const char* name = aarch64_prfops[i].name;
diff --git a/gas/testsuite/gas/aarch64/system-4-invalid.d b/gas/testsuite/gas/aarch64/system-4-invalid.d
new file mode 100644
index 00000000000..62d38eb324c
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/system-4-invalid.d
@@ -0,0 +1,3 @@
+#name: Invalid DSB memory nXS barrier variant
+#source: system-4-invalid.s
+#error_output: system-4-invalid.l
diff --git a/gas/testsuite/gas/aarch64/system-4-invalid.l b/gas/testsuite/gas/aarch64/system-4-invalid.l
new file mode 100644
index 00000000000..5a01e39ef73
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/system-4-invalid.l
@@ -0,0 +1,11 @@
+.*: Assembler messages:
+.*: Error: immediate value out of range 0 to 15 at operand 1 -- `dsb #17'
+.*: Error: immediate value out of range 0 to 15 at operand 1 -- `dsb #18'
+.*: Error: immediate value out of range 0 to 15 at operand 1 -- `dsb #19'
+.*: Error: immediate value out of range 0 to 15 at operand 1 -- `dsb #21'
+.*: Error: immediate value out of range 0 to 15 at operand 1 -- `dsb #22'
+.*: Error: immediate value out of range 0 to 15 at operand 1 -- `dsb #23'
+.*: Error: immediate value out of range 0 to 15 at operand 1 -- `dsb #25'
+.*: Error: immediate value out of range 0 to 15 at operand 1 -- `dsb #26'
+.*: Error: immediate value out of range 0 to 15 at operand 1 -- `dsb #27'
+.*: Error: immediate value out of range 0 to 15 at operand 1 -- `dsb #29'
diff --git a/gas/testsuite/gas/aarch64/system-4-invalid.s b/gas/testsuite/gas/aarch64/system-4-invalid.s
new file mode 100644
index 00000000000..cadad584f1f
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/system-4-invalid.s
@@ -0,0 +1,16 @@
+/* Armv8.7-a DSB memory nXS barrier variant. */
+.arch armv8.7-a
+
+ dsb #17
+ dsb #18
+ dsb #19
+
+ dsb #21
+ dsb #22
+ dsb #23
+
+ dsb #25
+ dsb #26
+ dsb #27
+
+ dsb #29
diff --git a/gas/testsuite/gas/aarch64/system-4.d b/gas/testsuite/gas/aarch64/system-4.d
new file mode 100644
index 00000000000..0f600f80abd
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/system-4.d
@@ -0,0 +1,16 @@
+#name: DSB memory nXS barrier variant
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+.*: d503323f dsb oshnxs
+.*: d503363f dsb nshnxs
+.*: d5033a3f dsb ishnxs
+.*: d5033e3f dsb synxs
+.*: d503323f dsb oshnxs
+.*: d503363f dsb nshnxs
+.*: d5033a3f dsb ishnxs
+.*: d5033e3f dsb synxs
diff --git a/gas/testsuite/gas/aarch64/system-4.s b/gas/testsuite/gas/aarch64/system-4.s
new file mode 100644
index 00000000000..f95eb35df56
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/system-4.s
@@ -0,0 +1,12 @@
+/* Armv8.7-a DSB memory nXS barrier variant. */
+.arch armv8.7-a
+
+ dsb #16
+ dsb #20
+ dsb #24
+ dsb #28
+
+ dsb oshnxs
+ dsb nshnxs
+ dsb ishnxs
+ dsb synxs
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index a5f9e717161..6ddcaf98ca2 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -317,6 +317,7 @@ enum aarch64_opnd
AARCH64_OPND_SYSREG_TLBI, /* System register <tlbi_op> operand. */
AARCH64_OPND_SYSREG_SR, /* System register RCTX operand. */
AARCH64_OPND_BARRIER, /* Barrier operand. */
+ AARCH64_OPND_BARRIER_DSB_NXS, /* Barrier operand for DSB nXS variant. */
AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */
AARCH64_OPND_PRFOP, /* Prefetch operation. */
AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */
@@ -949,6 +950,7 @@ struct aarch64_name_value_pair
extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
+extern const struct aarch64_name_value_pair aarch64_barrier_dsb_nxs_options [4];
extern const struct aarch64_name_value_pair aarch64_prfops [32];
extern const struct aarch64_name_value_pair aarch64_hint_options [];
diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
index 20f2c6e6411..11bee7fb3fc 100644
--- a/opcodes/aarch64-asm-2.c
+++ b/opcodes/aarch64-asm-2.c
@@ -426,14 +426,14 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
case 1184: /* movz */
value = 1184; /* --> movz. */
break;
- case 1239: /* autibsp */
- case 1238: /* autibz */
- case 1237: /* autiasp */
- case 1236: /* autiaz */
- case 1235: /* pacibsp */
- case 1234: /* pacibz */
- case 1233: /* paciasp */
- case 1232: /* paciaz */
+ case 1240: /* autibsp */
+ case 1239: /* autibz */
+ case 1238: /* autiasp */
+ case 1237: /* autiaz */
+ case 1236: /* pacibsp */
+ case 1235: /* pacibz */
+ case 1234: /* paciasp */
+ case 1233: /* paciaz */
case 1211: /* tsb */
case 1210: /* psb */
case 1209: /* esb */
@@ -453,141 +453,144 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
case 1194: /* hint */
value = 1194; /* --> hint. */
break;
- case 1216: /* pssbb */
- case 1215: /* ssbb */
- case 1214: /* dfb */
+ case 1217: /* pssbb */
+ case 1216: /* ssbb */
+ case 1215: /* dfb */
case 1213: /* dsb */
value = 1213; /* --> dsb. */
break;
- case 1227: /* cpp */
- case 1226: /* dvp */
- case 1225: /* cfp */
- case 1224: /* tlbi */
- case 1223: /* ic */
- case 1222: /* dc */
- case 1221: /* at */
- case 1220: /* sys */
- value = 1220; /* --> sys. */
+ case 1214: /* dsb */
+ value = 1214; /* --> dsb. */
break;
- case 2037: /* bic */
- case 1287: /* and */
- value = 1287; /* --> and. */
+ case 1228: /* cpp */
+ case 1227: /* dvp */
+ case 1226: /* cfp */
+ case 1225: /* tlbi */
+ case 1224: /* ic */
+ case 1223: /* dc */
+ case 1222: /* at */
+ case 1221: /* sys */
+ value = 1221; /* --> sys. */
break;
- case 1270: /* mov */
- case 1289: /* and */
- value = 1289; /* --> and. */
+ case 2038: /* bic */
+ case 1288: /* and */
+ value = 1288; /* --> and. */
break;
- case 1274: /* movs */
- case 1290: /* ands */
- value = 1290; /* --> ands. */
+ case 1271: /* mov */
+ case 1290: /* and */
+ value = 1290; /* --> and. */
break;
- case 2038: /* cmple */
- case 1325: /* cmpge */
- value = 1325; /* --> cmpge. */
+ case 1275: /* movs */
+ case 1291: /* ands */
+ value = 1291; /* --> ands. */
break;
- case 2041: /* cmplt */
- case 1328: /* cmpgt */
- value = 1328; /* --> cmpgt. */
+ case 2039: /* cmple */
+ case 1326: /* cmpge */
+ value = 1326; /* --> cmpge. */
break;
- case 2039: /* cmplo */
- case 1330: /* cmphi */
- value = 1330; /* --> cmphi. */
+ case 2042: /* cmplt */
+ case 1329: /* cmpgt */
+ value = 1329; /* --> cmpgt. */
break;
- case 2040: /* cmpls */
- case 1333: /* cmphs */
- value = 1333; /* --> cmphs. */
+ case 2040: /* cmplo */
+ case 1331: /* cmphi */
+ value = 1331; /* --> cmphi. */
break;
- case 1267: /* mov */
- case 1355: /* cpy */
- value = 1355; /* --> cpy. */
+ case 2041: /* cmpls */
+ case 1334: /* cmphs */
+ value = 1334; /* --> cmphs. */
break;
- case 1269: /* mov */
+ case 1268: /* mov */
case 1356: /* cpy */
value = 1356; /* --> cpy. */
break;
- case 2048: /* fmov */
- case 1272: /* mov */
+ case 1270: /* mov */
case 1357: /* cpy */
value = 1357; /* --> cpy. */
break;
- case 1262: /* mov */
- case 1369: /* dup */
- value = 1369; /* --> dup. */
+ case 2049: /* fmov */
+ case 1273: /* mov */
+ case 1358: /* cpy */
+ value = 1358; /* --> cpy. */
break;
- case 1264: /* mov */
- case 1261: /* mov */
+ case 1263: /* mov */
case 1370: /* dup */
value = 1370; /* --> dup. */
break;
- case 2047: /* fmov */
- case 1266: /* mov */
+ case 1265: /* mov */
+ case 1262: /* mov */
case 1371: /* dup */
value = 1371; /* --> dup. */
break;
- case 1265: /* mov */
- case 1372: /* dupm */
- value = 1372; /* --> dupm. */
+ case 2048: /* fmov */
+ case 1267: /* mov */
+ case 1372: /* dup */
+ value = 1372; /* --> dup. */
break;
- case 2042: /* eon */
- case 1374: /* eor */
- value = 1374; /* --> eor. */
+ case 1266: /* mov */
+ case 1373: /* dupm */
+ value = 1373; /* --> dupm. */
break;
- case 1275: /* not */
- case 1376: /* eor */
- value = 1376; /* --> eor. */
+ case 2043: /* eon */
+ case 1375: /* eor */
+ value = 1375; /* --> eor. */
break;
- case 1276: /* nots */
- case 1377: /* eors */
- value = 1377; /* --> eors. */
+ case 1276: /* not */
+ case 1377: /* eor */
+ value = 1377; /* --> eor. */
break;
- case 2043: /* facle */
- case 1382: /* facge */
- value = 1382; /* --> facge. */
+ case 1277: /* nots */
+ case 1378: /* eors */
+ value = 1378; /* --> eors. */
break;
- case 2044: /* faclt */
- case 1383: /* facgt */
- value = 1383; /* --> facgt. */
+ case 2044: /* facle */
+ case 1383: /* facge */
+ value = 1383; /* --> facge. */
break;
- case 2045: /* fcmle */
- case 1396: /* fcmge */
- value = 1396; /* --> fcmge. */
+ case 2045: /* faclt */
+ case 1384: /* facgt */
+ value = 1384; /* --> facgt. */
break;
- case 2046: /* fcmlt */
- case 1398: /* fcmgt */
- value = 1398; /* --> fcmgt. */
+ case 2046: /* fcmle */
+ case 1397: /* fcmge */
+ value = 1397; /* --> fcmge. */
break;
- case 1259: /* fmov */
- case 1404: /* fcpy */
- value = 1404; /* --> fcpy. */
+ case 2047: /* fcmlt */
+ case 1399: /* fcmgt */
+ value = 1399; /* --> fcmgt. */
break;
- case 1258: /* fmov */
- case 1427: /* fdup */
- value = 1427; /* --> fdup. */
+ case 1260: /* fmov */
+ case 1405: /* fcpy */
+ value = 1405; /* --> fcpy. */
break;
- case 1260: /* mov */
- case 1758: /* orr */
- value = 1758; /* --> orr. */
+ case 1259: /* fmov */
+ case 1428: /* fdup */
+ value = 1428; /* --> fdup. */
break;
- case 2049: /* orn */
+ case 1261: /* mov */
case 1759: /* orr */
value = 1759; /* --> orr. */
break;
- case 1263: /* mov */
- case 1761: /* orr */
- value = 1761; /* --> orr. */
+ case 2050: /* orn */
+ case 1760: /* orr */
+ value = 1760; /* --> orr. */
break;
- case 1273: /* movs */
- case 1762: /* orrs */
- value = 1762; /* --> orrs. */
+ case 1264: /* mov */
+ case 1762: /* orr */
+ value = 1762; /* --> orr. */
break;
- case 1268: /* mov */
- case 1824: /* sel */
- value = 1824; /* --> sel. */
+ case 1274: /* movs */
+ case 1763: /* orrs */
+ value = 1763; /* --> orrs. */
break;
- case 1271: /* mov */
+ case 1269: /* mov */
case 1825: /* sel */
value = 1825; /* --> sel. */
break;
+ case 1272: /* mov */
+ case 1826: /* sel */
+ value = 1826; /* --> sel. */
+ break;
default: return NULL;
}
@@ -630,7 +633,6 @@ aarch64_insert_operand (const aarch64_operand *self,
case 28:
case 29:
case 30:
- case 164:
case 165:
case 166:
case 167:
@@ -640,7 +642,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case 171:
case 172:
case 173:
- case 188:
+ case 174:
case 189:
case 190:
case 191:
@@ -649,8 +651,9 @@ aarch64_insert_operand (const aarch64_operand *self,
case 194:
case 195:
case 196:
- case 202:
- case 205:
+ case 197:
+ case 203:
+ case 206:
return aarch64_ins_regno (self, info, code, inst, errors);
case 14:
return aarch64_ins_reg_extended (self, info, code, inst, errors);
@@ -662,7 +665,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case 32:
case 33:
case 34:
- case 208:
+ case 209:
return aarch64_ins_reglane (self, info, code, inst, errors);
case 35:
return aarch64_ins_reglist (self, info, code, inst, errors);
@@ -697,9 +700,8 @@ aarch64_insert_operand (const aarch64_operand *self,
case 81:
case 82:
case 83:
- case 161:
- case 163:
- case 180:
+ case 162:
+ case 164:
case 181:
case 182:
case 183:
@@ -707,7 +709,8 @@ aarch64_insert_operand (const aarch64_operand *self,
case 185:
case 186:
case 187:
- case 207:
+ case 188:
+ case 208:
return aarch64_ins_imm (self, info, code, inst, errors);
case 43:
case 44:
@@ -717,10 +720,10 @@ aarch64_insert_operand (const aarch64_operand *self,
case 47:
return aarch64_ins_advsimd_imm_modified (self, info, code, inst, errors);
case 51:
- case 151:
+ case 152:
return aarch64_ins_fpimm (self, info, code, inst, errors);
case 69:
- case 159:
+ case 160:
return aarch64_ins_limm (self, info, code, inst, errors);
case 70:
return aarch64_ins_aimm (self, info, code, inst, errors);
@@ -730,11 +733,11 @@ aarch64_insert_operand (const aarch64_operand *self,
return aarch64_ins_fbits (self, info, code, inst, errors);
case 74:
case 75:
- case 156:
+ case 157:
return aarch64_ins_imm_rotate2 (self, info, code, inst, errors);
case 76:
- case 155:
- case 157:
+ case 156:
+ case 158:
return aarch64_ins_imm_rotate1 (self, info, code, inst, errors);
case 77:
case 78:
@@ -769,32 +772,33 @@ aarch64_insert_operand (const aarch64_operand *self,
case 102:
return aarch64_ins_sysins_op (self, info, code, inst, errors);
case 103:
- case 104:
- return aarch64_ins_barrier (self, info, code, inst, errors);
case 105:
- return aarch64_ins_prfop (self, info, code, inst, errors);
+ return aarch64_ins_barrier (self, info, code, inst, errors);
+ case 104:
+ return aarch64_ins_barrier_dsb_nxs (self, info, code, inst, errors);
case 106:
- return aarch64_ins_none (self, info, code, inst, errors);
+ return aarch64_ins_prfop (self, info, code, inst, errors);
case 107:
- return aarch64_ins_hint (self, info, code, inst, errors);
+ return aarch64_ins_none (self, info, code, inst, errors);
case 108:
+ return aarch64_ins_hint (self, info, code, inst, errors);
case 109:
- return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors);
case 110:
+ return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors);
case 111:
case 112:
case 113:
- return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors);
case 114:
- return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors);
+ return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors);
case 115:
- return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors);
+ return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors);
case 116:
+ return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors);
case 117:
case 118:
case 119:
- return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors);
case 120:
+ return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors);
case 121:
case 122:
case 123:
@@ -808,8 +812,8 @@ aarch64_insert_operand (const aarch64_operand *self,
case 131:
case 132:
case 133:
- return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors);
case 134:
+ return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors);
case 135:
case 136:
case 137:
@@ -817,52 +821,53 @@ aarch64_insert_operand (const aarch64_operand *self,
case 139:
case 140:
case 141:
- return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors);
case 142:
+ return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors);
case 143:
case 144:
case 145:
- return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors);
case 146:
- return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors);
+ return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors);
case 147:
- return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors);
+ return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors);
case 148:
- return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors);
+ return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors);
case 149:
- return aarch64_ins_sve_aimm (self, info, code, inst, errors);
+ return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors);
case 150:
+ return aarch64_ins_sve_aimm (self, info, code, inst, errors);
+ case 151:
return aarch64_ins_sve_asimm (self, info, code, inst, errors);
- case 152:
- return aarch64_ins_sve_float_half_one (self, info, code, inst, errors);
case 153:
- return aarch64_ins_sve_float_half_two (self, info, code, inst, errors);
+ return aarch64_ins_sve_float_half_one (self, info, code, inst, errors);
case 154:
+ return aarch64_ins_sve_float_half_two (self, info, code, inst, errors);
+ case 155:
return aarch64_ins_sve_float_zero_one (self, info, code, inst, errors);
- case 158:
+ case 159:
return aarch64_ins_inv_limm (self, info, code, inst, errors);
- case 160:
+ case 161:
return aarch64_ins_sve_limm_mov (self, info, code, inst, errors);
- case 162:
+ case 163:
return aarch64_ins_sve_scale (self, info, code, inst, errors);
- case 174:
case 175:
case 176:
- return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
case 177:
+ return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
case 178:
case 179:
+ case 180:
return aarch64_ins_sve_shrimm (self, info, code, inst, errors);
- case 197:
case 198:
case 199:
case 200:
case 201:
+ case 202:
return aarch64_ins_sve_quad_index (self, info, code, inst, errors);
- case 203:
- return aarch64_ins_sve_index (self, info, code, inst, errors);
case 204:
- case 206:
+ return aarch64_ins_sve_index (self, info, code, inst, errors);
+ case 205:
+ case 207:
return aarch64_ins_sve_reglist (self, info, code, inst, errors);
default: assert (0); abort ();
}
diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
index b4846bf986e..4b53c71a85a 100644
--- a/opcodes/aarch64-asm.c
+++ b/opcodes/aarch64-asm.c
@@ -876,6 +876,21 @@ aarch64_ins_barrier (const aarch64_operand *self ATTRIBUTE_UNUSED,
return TRUE;
}
+/* Encode the memory barrier option operand for DSB <option>nXS|#<imm>. */
+
+bfd_boolean
+aarch64_ins_barrier_dsb_nxs (const aarch64_operand *self ATTRIBUTE_UNUSED,
+ const aarch64_opnd_info *info, aarch64_insn *code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
+{
+ /* For the DSB nXS barrier variant: is a 5-bit unsigned immediate,
+ encoded in CRm<3:2>. */
+ aarch64_insn value = (info->barrier->value >> 2) - 4;
+ insert_field (FLD_CRm_dsb_nxs, code, value, 0);
+ return TRUE;
+}
+
/* Encode the prefetch operation option operand for e.g.
PRFM <prfop>, [<Xn|SP>{, #<pimm>}]. */
diff --git a/opcodes/aarch64-asm.h b/opcodes/aarch64-asm.h
index d36befefc20..635759536c3 100644
--- a/opcodes/aarch64-asm.h
+++ b/opcodes/aarch64-asm.h
@@ -71,6 +71,7 @@ AARCH64_DECL_OPD_INSERTER (ins_sysreg);
AARCH64_DECL_OPD_INSERTER (ins_pstatefield);
AARCH64_DECL_OPD_INSERTER (ins_sysins_op);
AARCH64_DECL_OPD_INSERTER (ins_barrier);
+AARCH64_DECL_OPD_INSERTER (ins_barrier_dsb_nxs);
AARCH64_DECL_OPD_INSERTER (ins_hint);
AARCH64_DECL_OPD_INSERTER (ins_prfop);
AARCH64_DECL_OPD_INSERTER (ins_reg_extended);
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index a35311c112f..f7eea5670c3 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -2379,7 +2379,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00011001000xxxxxxxxx00xxxxxxxxxx
stlurb. */
- return 2381;
+ return 2382;
}
else
{
@@ -2387,7 +2387,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
10011001000xxxxxxxxx00xxxxxxxxxx
stlur. */
- return 2389;
+ return 2390;
}
}
else
@@ -2398,7 +2398,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01011001000xxxxxxxxx00xxxxxxxxxx
stlurh. */
- return 2385;
+ return 2386;
}
else
{
@@ -2406,7 +2406,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
11011001000xxxxxxxxx00xxxxxxxxxx
stlur. */
- return 2392;
+ return 2393;
}
}
}
@@ -2486,7 +2486,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00011001010xxxxxxxxx00xxxxxxxxxx
ldapurb. */
- return 2382;
+ return 2383;
}
else
{
@@ -2494,7 +2494,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
10011001010xxxxxxxxx00xxxxxxxxxx
ldapur. */
- return 2390;
+ return 2391;
}
}
else
@@ -2505,7 +2505,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
01011001010xxxxxxxxx00xxxxxxxxxx
ldapurh. */
- return 2386;
+ return 2387;
}
else
{
@@ -2513,7 +2513,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
11011001010xxxxxxxxx00xxxxxxxxxx
ldapur. */
- return 2393;
+ return 2394;
}
}
}
@@ -2596,7 +2596,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
00011001100xxxxxxxxx00xxxxxxxxxx
ldapursb. */
- return 2384;
+ return 2385;
}
else
{
@@ -2604,7 +2604,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
10011001100xxxxxxxxx00xxxxxxxxxx
ldapursw. */
- return 2391;
+ return 2392;
}
}
else
@@ -2613,7 +2613,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1011001100xxxxxxxxx00xxxxxxxxxx
ldapursh. */
- return 2388;
+ return 2389;
}
}
else
@@ -2624,7 +2624,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x0011001110xxxxxxxxx00xxxxxxxxxx
ldapursb. */
- return 2383;
+ return 2384;
}
else
{
@@ -2632,7 +2632,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x1011001110xxxxxxxxx00xxxxxxxxxx
ldapursh. */
- return 2387;
+ return 2388;
}
}
}
@@ -3118,7 +3118,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx11010x00xxxxxx0xx10xxxxxxxxxx
setf8. */
- return 2379;
+ return 2380;
}
else
{
@@ -3126,7 +3126,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx11010x00xxxxxx1xx10xxxxxxxxxx
setf16. */
- return 2380;
+ return 2381;
}
}
else
@@ -3272,7 +3272,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx11010000xxxxxxxxx01xxxxxxxxxx
rmif. */
- return 2378;
+ return 2379;
}
else
{
@@ -3810,7 +3810,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx000000000xxxxxxxxxxxxx
add. */
- return 1280;
+ return 1281;
}
else
{
@@ -3818,7 +3818,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx010000000xxxxxxxxxxxxx
mul. */
- return 1749;
+ return 1750;
}
}
else
@@ -3829,7 +3829,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx001000000xxxxxxxxxxxxx
smax. */
- return 1828;
+ return 1829;
}
else
{
@@ -3837,7 +3837,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx011000000xxxxxxxxxxxxx
orr. */
- return 1760;
+ return 1761;
}
}
}
@@ -3849,7 +3849,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx0x0100000xxxxxxxxxxxxx
sdiv. */
- return 1819;
+ return 1820;
}
else
{
@@ -3857,7 +3857,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx0x1100000xxxxxxxxxxxxx
sabd. */
- return 1810;
+ return 1811;
}
}
}
@@ -3871,7 +3871,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx0x0010000xxxxxxxxxxxxx
smulh. */
- return 1833;
+ return 1834;
}
else
{
@@ -3881,7 +3881,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx001010000xxxxxxxxxxxxx
smin. */
- return 1831;
+ return 1832;
}
else
{
@@ -3889,7 +3889,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx011010000xxxxxxxxxxxxx
and. */
- return 1288;
+ return 1289;
}
}
}
@@ -3899,7 +3899,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx0xx110000xxxxxxxxxxxxx
sdivr. */
- return 1820;
+ return 1821;
}
}
}
@@ -3915,7 +3915,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx0x0001000xxxxxxxxxxxxx
sub. */
- return 1949;
+ return 1950;
}
else
{
@@ -3925,7 +3925,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx001001000xxxxxxxxxxxxx
umax. */
- return 1977;
+ return 1978;
}
else
{
@@ -3933,7 +3933,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx011001000xxxxxxxxxxxxx
eor. */
- return 1375;
+ return 1376;
}
}
}
@@ -3945,7 +3945,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx0x0101000xxxxxxxxxxxxx
udiv. */
- return 1971;
+ return 1972;
}
else
{
@@ -3953,7 +3953,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx0x1101000xxxxxxxxxxxxx
uabd. */
- return 1962;
+ return 1963;
}
}
}
@@ -3969,7 +3969,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx000011000xxxxxxxxxxxxx
subr. */
- return 1951;
+ return 1952;
}
else
{
@@ -3977,7 +3977,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx010011000xxxxxxxxxxxxx
umulh. */
- return 1982;
+ return 1983;
}
}
else
@@ -3988,7 +3988,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx001011000xxxxxxxxxxxxx
umin. */
- return 1980;
+ return 1981;
}
else
{
@@ -3996,7 +3996,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx011011000xxxxxxxxxxxxx
bic. */
- return 1300;
+ return 1301;
}
}
}
@@ -4006,7 +4006,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx0xx111000xxxxxxxxxxxxx
udivr. */
- return 1972;
+ return 1973;
}
}
}
@@ -4019,7 +4019,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
100001x00x0xxxxx000xxxxxxxxxxxxx
ld1sb. */
- return 1562;
+ return 1563;
}
else
{
@@ -4027,7 +4027,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
100001x01x0xxxxx000xxxxxxxxxxxxx
ld1sh. */
- return 1573;
+ return 1574;
}
}
}
@@ -4045,7 +4045,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx000000xxxxxxxxxx
sdot. */
- return 1821;
+ return 1822;
}
else
{
@@ -4053,7 +4053,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx000010xxxxxxxxxx
sqdmlalbt. */
- return 2171;
+ return 2172;
}
}
else
@@ -4064,7 +4064,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx000001xxxxxxxxxx
udot. */
- return 1973;
+ return 1974;
}
else
{
@@ -4072,7 +4072,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx000011xxxxxxxxxx
sqdmlslbt. */
- return 2178;
+ return 2179;
}
}
}
@@ -4082,7 +4082,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0xxxxx0001xxxxxxxxxxxx
cdot. */
- return 2060;
+ return 2061;
}
}
else
@@ -4093,7 +4093,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
110001x00x0xxxxx000xxxxxxxxxxxxx
ld1sb. */
- return 1566;
+ return 1567;
}
else
{
@@ -4101,7 +4101,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
110001x01x0xxxxx000xxxxxxxxxxxxx
ld1sh. */
- return 1577;
+ return 1578;
}
}
}
@@ -4122,7 +4122,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx1xxxxx000000xxxxxxxxxx
add. */
- return 1278;
+ return 1279;
}
else
{
@@ -4130,7 +4130,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx1xxxxx000100xxxxxxxxxx
sqadd. */
- return 1835;
+ return 1836;
}
}
else
@@ -4139,7 +4139,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx1xxxxx000x10xxxxxxxxxx
sqsub. */
- return 1865;
+ return 1866;
}
}
else
@@ -4152,7 +4152,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx1xxxxx000001xxxxxxxxxx
sub. */
- return 1947;
+ return 1948;
}
else
{
@@ -4160,7 +4160,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx1xxxxx000101xxxxxxxxxx
uqadd. */
- return 1983;
+ return 1984;
}
}
else
@@ -4169,7 +4169,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx1xxxxx000x11xxxxxxxxxx
uqsub. */
- return 2013;
+ return 2014;
}
}
}
@@ -4181,7 +4181,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
100001x00x1xxxxx000xxxxxxxxxxxxx
prfb. */
- return 1768;
+ return 1769;
}
else
{
@@ -4189,7 +4189,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
100001x01x1xxxxx000xxxxxxxxxxxxx
ld1sh. */
- return 1574;
+ return 1575;
}
}
}
@@ -4207,7 +4207,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x00x1xxxxx000x00xxxxxxxxxx
sqrdmlah. */
- return 2196;
+ return 2197;
}
else
{
@@ -4215,7 +4215,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x00x1xxxxx000x10xxxxxxxxxx
mla. */
- return 2103;
+ return 2104;
}
}
else
@@ -4226,7 +4226,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x00x1xxxxx000x01xxxxxxxxxx
sqrdmlsh. */
- return 2200;
+ return 2201;
}
else
{
@@ -4234,7 +4234,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x00x1xxxxx000x11xxxxxxxxxx
mls. */
- return 2106;
+ return 2107;
}
}
}
@@ -4244,7 +4244,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
110001x00x1xxxxx000xxxxxxxxxxxxx
prfb. */
- return 1769;
+ return 1770;
}
}
else
@@ -4263,7 +4263,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0101xxxxx000000xxxxxxxxxx
sdot. */
- return 1822;
+ return 1823;
}
else
{
@@ -4271,7 +4271,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0111xxxxx000000xxxxxxxxxx
sdot. */
- return 1823;
+ return 1824;
}
}
else
@@ -4282,7 +4282,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0101xxxxx000100xxxxxxxxxx
sqrdmlah. */
- return 2197;
+ return 2198;
}
else
{
@@ -4290,7 +4290,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0111xxxxx000100xxxxxxxxxx
sqrdmlah. */
- return 2198;
+ return 2199;
}
}
}
@@ -4304,7 +4304,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0101xxxxx000010xxxxxxxxxx
mla. */
- return 2104;
+ return 2105;
}
else
{
@@ -4312,7 +4312,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0111xxxxx000010xxxxxxxxxx
mla. */
- return 2105;
+ return 2106;
}
}
else
@@ -4321,7 +4321,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x01x1xxxxx000110xxxxxxxxxx
usdot. */
- return 2398;
+ return 2399;
}
}
}
@@ -4337,7 +4337,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0101xxxxx000001xxxxxxxxxx
udot. */
- return 1974;
+ return 1975;
}
else
{
@@ -4345,7 +4345,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0111xxxxx000001xxxxxxxxxx
udot. */
- return 1975;
+ return 1976;
}
}
else
@@ -4356,7 +4356,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0101xxxxx000101xxxxxxxxxx
sqrdmlsh. */
- return 2201;
+ return 2202;
}
else
{
@@ -4364,7 +4364,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0111xxxxx000101xxxxxxxxxx
sqrdmlsh. */
- return 2202;
+ return 2203;
}
}
}
@@ -4378,7 +4378,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0101xxxxx000011xxxxxxxxxx
mls. */
- return 2107;
+ return 2108;
}
else
{
@@ -4386,7 +4386,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0111xxxxx000011xxxxxxxxxx
mls. */
- return 2108;
+ return 2109;
}
}
else
@@ -4395,7 +4395,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x01x1xxxxx000111xxxxxxxxxx
sudot. */
- return 2399;
+ return 2400;
}
}
}
@@ -4406,7 +4406,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
110001x01x1xxxxx000xxxxxxxxxxxxx
ld1sh. */
- return 1578;
+ return 1579;
}
}
}
@@ -4432,7 +4432,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x0001x0xx000000100xxxxxxxxxxxxx
asr. */
- return 1296;
+ return 1297;
}
else
{
@@ -4442,7 +4442,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx010000100xxxxxxxxxxxxx
asr. */
- return 1294;
+ return 1295;
}
else
{
@@ -4450,7 +4450,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx010000100xxxxxxxxxxxxx
shadd. */
- return 2137;
+ return 2138;
}
}
}
@@ -4462,7 +4462,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x0001x0xx001000100xxxxxxxxxxxxx
sqshl. */
- return 2215;
+ return 2216;
}
else
{
@@ -4472,7 +4472,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx011000100xxxxxxxxxxxxx
asr. */
- return 1295;
+ return 1296;
}
else
{
@@ -4480,7 +4480,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx011000100xxxxxxxxxxxxx
sqadd. */
- return 2166;
+ return 2167;
}
}
}
@@ -4495,7 +4495,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x0001x0xx000100100xxxxxxxxxxxxx
asrd. */
- return 1297;
+ return 1298;
}
else
{
@@ -4505,7 +4505,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx010100100xxxxxxxxxxxxx
asrr. */
- return 1298;
+ return 1299;
}
else
{
@@ -4513,7 +4513,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx010100100xxxxxxxxxxxxx
srhadd. */
- return 2228;
+ return 2229;
}
}
}
@@ -4527,7 +4527,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx001100100xxxxxxxxxxxxx
srshr. */
- return 2232;
+ return 2233;
}
else
{
@@ -4535,7 +4535,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx001100100xxxxxxxxxxxxx
sqshlr. */
- return 2216;
+ return 2217;
}
}
else
@@ -4544,7 +4544,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x0001x0xx011100100xxxxxxxxxxxxx
suqadd. */
- return 2252;
+ return 2253;
}
}
}
@@ -4561,7 +4561,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x0001x0xx000010100xxxxxxxxxxxxx
srshl. */
- return 2230;
+ return 2231;
}
else
{
@@ -4569,7 +4569,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x0001x0xx010010100xxxxxxxxxxxxx
shsub. */
- return 2140;
+ return 2141;
}
}
else
@@ -4580,7 +4580,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x0001x0xx001010100xxxxxxxxxxxxx
sqrshl. */
- return 2208;
+ return 2209;
}
else
{
@@ -4588,7 +4588,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x0001x0xx011010100xxxxxxxxxxxxx
sqsub. */
- return 2222;
+ return 2223;
}
}
}
@@ -4604,7 +4604,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx000110100xxxxxxxxxxxxx
sqshl. */
- return 2214;
+ return 2215;
}
else
{
@@ -4612,7 +4612,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx000110100xxxxxxxxxxxxx
srshlr. */
- return 2231;
+ return 2232;
}
}
else
@@ -4621,7 +4621,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x0001x0xx010110100xxxxxxxxxxxxx
shsubr. */
- return 2141;
+ return 2142;
}
}
else
@@ -4632,7 +4632,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x0001x0xx001110100xxxxxxxxxxxxx
sqrshlr. */
- return 2209;
+ return 2210;
}
else
{
@@ -4640,7 +4640,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x0001x0xx011110100xxxxxxxxxxxxx
sqsubr. */
- return 2223;
+ return 2224;
}
}
}
@@ -4660,7 +4660,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x0001x0xx000001100xxxxxxxxxxxxx
lsr. */
- return 1740;
+ return 1741;
}
else
{
@@ -4670,7 +4670,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx010001100xxxxxxxxxxxxx
lsr. */
- return 1738;
+ return 1739;
}
else
{
@@ -4678,7 +4678,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx010001100xxxxxxxxxxxxx
uhadd. */
- return 2265;
+ return 2266;
}
}
}
@@ -4690,7 +4690,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x0001x0xx001001100xxxxxxxxxxxxx
uqshl. */
- return 2295;
+ return 2296;
}
else
{
@@ -4700,7 +4700,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx011001100xxxxxxxxxxxxx
lsr. */
- return 1739;
+ return 1740;
}
else
{
@@ -4708,7 +4708,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx011001100xxxxxxxxxxxxx
uqadd. */
- return 2289;
+ return 2290;
}
}
}
@@ -4723,7 +4723,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx0x0101100xxxxxxxxxxxxx
lsrr. */
- return 1741;
+ return 1742;
}
else
{
@@ -4731,7 +4731,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx0x0101100xxxxxxxxxxxxx
urhadd. */
- return 2304;
+ return 2305;
}
}
else
@@ -4744,7 +4744,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx001101100xxxxxxxxxxxxx
urshr. */
- return 2307;
+ return 2308;
}
else
{
@@ -4752,7 +4752,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx001101100xxxxxxxxxxxxx
uqshlr. */
- return 2296;
+ return 2297;
}
}
else
@@ -4761,7 +4761,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x0001x0xx011101100xxxxxxxxxxxxx
usqadd. */
- return 2312;
+ return 2313;
}
}
}
@@ -4780,7 +4780,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx000011100xxxxxxxxxxxxx
lsl. */
- return 1734;
+ return 1735;
}
else
{
@@ -4788,7 +4788,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx000011100xxxxxxxxxxxxx
urshl. */
- return 2305;
+ return 2306;
}
}
else
@@ -4799,7 +4799,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx010011100xxxxxxxxxxxxx
lsl. */
- return 1732;
+ return 1733;
}
else
{
@@ -4807,7 +4807,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx010011100xxxxxxxxxxxxx
uhsub. */
- return 2266;
+ return 2267;
}
}
}
@@ -4819,7 +4819,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0x0001x0xx001011100xxxxxxxxxxxxx
uqrshl. */
- return 2290;
+ return 2291;
}
else
{
@@ -4829,7 +4829,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx011011100xxxxxxxxxxxxx
lsl. */
- return 1733;
+ return 1734;
}
else
{
@@ -4837,7 +4837,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx011011100xxxxxxxxxxxxx
uqsub. */
- return 2299;
+ return 2300;
}
}
}
@@ -4854,7 +4854,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx000111100xxxxxxxxxxxxx
uqshl. */
- return 2294;
+ return 2295;
}
else
{
@@ -4862,7 +4862,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0xx000111100xxxxxxxxxxxxx
urshlr. */
- return 2306;
+ return 2307;
}
}
else
@@ -4873,7 +4873,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx010111100xxxxxxxxxxxxx
[...]
[diff truncated at 100000 bytes]