[binutils-gdb] aarch64: Define CSRE system registers
Przemyslaw Wirkus
wirkus@sourceware.org
Thu Oct 22 14:18:12 GMT 2020
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=5feaa09beca04312e51adc69766b0e4bfc181f99
commit 5feaa09beca04312e51adc69766b0e4bfc181f99
Author: Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
Date: Thu Oct 22 15:17:10 2020 +0100
aarch64: Define CSRE system registers
This patch introduces CSRE (Call Stack Recorder Extension) system
registers.
Note: as this is register only extension we do not want to hide these
registers behind -march flag going forward (they should be enabled by
default).
CSRE feature adds CSR PDEC (Decrements Call stack pointer by the size
of a Call stack record) instruction. This instruction will be added in
a following, separate patch. This change only adds CSRE system
registers.
gas/ChangeLog:
2020-10-08 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* NEWS: Docs update.
* testsuite/gas/aarch64/csre-invalid.d: New test.
* testsuite/gas/aarch64/csre-invalid.l: New test.
* testsuite/gas/aarch64/csre-invalid.s: New test.
* testsuite/gas/aarch64/csre.d: New test.
* testsuite/gas/aarch64/csre.s: New test.
opcodes/ChangeLog:
2020-10-08 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* aarch64-opc.c: New CSRE system registers defined.
Diff:
---
gas/NEWS | 3 ++-
gas/testsuite/gas/aarch64/csre-invalid.d | 3 +++
gas/testsuite/gas/aarch64/csre-invalid.l | 5 +++++
gas/testsuite/gas/aarch64/csre-invalid.s | 6 ++++++
gas/testsuite/gas/aarch64/csre.d | 29 +++++++++++++++++++++++++++++
gas/testsuite/gas/aarch64/csre.s | 25 +++++++++++++++++++++++++
opcodes/aarch64-opc.c | 13 +++++++++++++
7 files changed, 83 insertions(+), 1 deletion(-)
diff --git a/gas/NEWS b/gas/NEWS
index 6da318b4d2a..61a69efa66e 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -15,7 +15,8 @@
Add support for Cortex-R82, Neoverse V1, and Neoverse N2 for ARM.
* Add support for ETMv4 (Embedded Trace Macrocell), ETE (Embedded Trace
- Extension) and TRBE (Trace Buffer Extension) system registers for AArch64.
+ Extension), TRBE (Trace Buffer Extension) and CSRE (Call Stack Recorder
+ Extension) system registers for AArch64.
* Add support for Armv8-R AArch64.
diff --git a/gas/testsuite/gas/aarch64/csre-invalid.d b/gas/testsuite/gas/aarch64/csre-invalid.d
new file mode 100644
index 00000000000..f273b65010a
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/csre-invalid.d
@@ -0,0 +1,3 @@
+#name: Invalid CSRE System registers usage
+#source: csre-invalid.s
+#warning_output: csre-invalid.l
diff --git a/gas/testsuite/gas/aarch64/csre-invalid.l b/gas/testsuite/gas/aarch64/csre-invalid.l
new file mode 100644
index 00000000000..be3d4c4b75e
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/csre-invalid.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Warning: specified register cannot be written to at operand 1 -- `msr csridr_el0,x0'
+.*: Warning: specified register cannot be written to at operand 1 -- `msr csrptridx_el0,x0'
+.*: Warning: specified register cannot be written to at operand 1 -- `msr csrptridx_el1,x0'
+.*: Warning: specified register cannot be written to at operand 1 -- `msr csrptridx_el2,x0'
diff --git a/gas/testsuite/gas/aarch64/csre-invalid.s b/gas/testsuite/gas/aarch64/csre-invalid.s
new file mode 100644
index 00000000000..424f50a3fea
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/csre-invalid.s
@@ -0,0 +1,6 @@
+/* Write to read-only CSRE system registers. */
+
+msr csridr_el0 ,x0
+msr csrptridx_el0 ,x0
+msr csrptridx_el1 ,x0
+msr csrptridx_el2 ,x0
diff --git a/gas/testsuite/gas/aarch64/csre.d b/gas/testsuite/gas/aarch64/csre.d
new file mode 100644
index 00000000000..ac77d4ac1a2
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/csre.d
@@ -0,0 +1,29 @@
+#name: CSRE System registers
+#objdump: -dr
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+
+0+ <.*>:
+[^:]+: d5338000 mrs x0, csrcr_el0
+[^:]+: d5338020 mrs x0, csrptr_el0
+[^:]+: d5338040 mrs x0, csridr_el0
+[^:]+: d5338060 mrs x0, csrptridx_el0
+[^:]+: d5308000 mrs x0, csrcr_el1
+[^:]+: d5358000 mrs x0, csrcr_el12
+[^:]+: d5308020 mrs x0, csrptr_el1
+[^:]+: d5358020 mrs x0, csrptr_el12
+[^:]+: d5308060 mrs x0, csrptridx_el1
+[^:]+: d5348000 mrs x0, csrcr_el2
+[^:]+: d5348020 mrs x0, csrptr_el2
+[^:]+: d5348060 mrs x0, csrptridx_el2
+[^:]+: d5138000 msr csrcr_el0, x0
+[^:]+: d5138020 msr csrptr_el0, x0
+[^:]+: d5108000 msr csrcr_el1, x0
+[^:]+: d5158000 msr csrcr_el12, x0
+[^:]+: d5108020 msr csrptr_el1, x0
+[^:]+: d5158020 msr csrptr_el12, x0
+[^:]+: d5148000 msr csrcr_el2, x0
+[^:]+: d5148020 msr csrptr_el2, x0
diff --git a/gas/testsuite/gas/aarch64/csre.s b/gas/testsuite/gas/aarch64/csre.s
new file mode 100644
index 00000000000..bede41cf37d
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/csre.s
@@ -0,0 +1,25 @@
+/* Call Stack Recorder Extension system registers. */
+
+/* Read from system registers. */
+mrs x0, csrcr_el0
+mrs x0, csrptr_el0
+mrs x0, csridr_el0
+mrs x0, csrptridx_el0
+mrs x0, csrcr_el1
+mrs x0, csrcr_el12
+mrs x0, csrptr_el1
+mrs x0, csrptr_el12
+mrs x0, csrptridx_el1
+mrs x0, csrcr_el2
+mrs x0, csrptr_el2
+mrs x0, csrptridx_el2
+
+/* Write to system registers. */
+msr csrcr_el0, x0
+msr csrptr_el0, x0
+msr csrcr_el1, x0
+msr csrcr_el12, x0
+msr csrptr_el1, x0
+msr csrptr_el12, x0
+msr csrcr_el2, x0
+msr csrptr_el2, x0
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 5c8d8ec6443..b97d05563f5 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -4541,6 +4541,19 @@ const aarch64_sys_reg aarch64_sys_regs [] =
SR_CORE ("trclar", CPENC (2,1,C7,C12,6), F_REG_WRITE),
SR_CORE ("trcoslar", CPENC (2,1,C1,C0,4), F_REG_WRITE),
+ SR_CORE ("csrcr_el0", CPENC (2,3,C8,C0,0), 0),
+ SR_CORE ("csrptr_el0", CPENC (2,3,C8,C0,1), 0),
+ SR_CORE ("csridr_el0", CPENC (2,3,C8,C0,2), F_REG_READ),
+ SR_CORE ("csrptridx_el0", CPENC (2,3,C8,C0,3), F_REG_READ),
+ SR_CORE ("csrcr_el1", CPENC (2,0,C8,C0,0), 0),
+ SR_CORE ("csrcr_el12", CPENC (2,5,C8,C0,0), 0),
+ SR_CORE ("csrptr_el1", CPENC (2,0,C8,C0,1), 0),
+ SR_CORE ("csrptr_el12", CPENC (2,5,C8,C0,1), 0),
+ SR_CORE ("csrptridx_el1", CPENC (2,0,C8,C0,3), F_REG_READ),
+ SR_CORE ("csrcr_el2", CPENC (2,4,C8,C0,0), 0),
+ SR_CORE ("csrptr_el2", CPENC (2,4,C8,C0,1), 0),
+ SR_CORE ("csrptridx_el2", CPENC (2,4,C8,C0,3), F_REG_READ),
+
{ 0, CPENC (0,0,0,0,0), 0, 0 }
};
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