[binutils-gdb/binutils-2_34-branch] gas, arm: PR25660L Fix vadd/vsub with lt and le condition codes for MVE
Andre Simoes Dias Vieira
avieira@sourceware.org
Fri Mar 13 13:39:05 GMT 2020
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=b3174859c4b609242effbff5901c01935003537a
commit b3174859c4b609242effbff5901c01935003537a
Author: Andre Vieira <andre.simoesdiasvieira@arm.com>
Date: Fri Mar 13 13:31:56 2020 +0000
gas, arm: PR25660L Fix vadd/vsub with lt and le condition codes for MVE
As explained in the PR, the addition of MVE makes the parser strip 't' and 'e'
as suffixes when MVE is enabled. This leads to vadd and vsub in it blocks with
lt and le conditions to be initially parsed as vaddl and vsubl. This means the
operand parsing for these must allow for the same operands as the scalar vadd
and vsub. I had forgotten to do this and this patch remedies that oversight.
gas/ChangeLog:
2020-03-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
Backport from mainline.
2020-03-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR 25660
* config/tc-arm.c (operand_parse_code): Add OP_RNSDMQR and OP_oRNSDMQ.
(parse_operands): Handle new operand codes.
(do_neon_dyadic_long): Make shape check accept the scalar variants.
(asm_opcode_insns): Fix operand codes for vaddl and vsubl.
* testsuite/gas/arm/mve-vaddsub-it.s: New test.
* testsuite/gas/arm/mve-vaddsub-it.d: New test.
* testsuite/gas/arm/mve-vaddsub-it-bad.s: New test.
* testsuite/gas/arm/mve-vaddsub-it-bad.l: New test.
* testsuite/gas/arm/mve-vaddsub-it-bad.d: New test.
* testsuite/gas/arm/nomve-vaddsub-it.d: New test.
Diff:
---
gas/ChangeLog | 17 +++++++++++++++++
gas/config/tc-arm.c | 21 ++++++++++++++++++---
gas/testsuite/gas/arm/mve-vaddsub-it-bad.d | 6 ++++++
gas/testsuite/gas/arm/mve-vaddsub-it-bad.l | 7 +++++++
gas/testsuite/gas/arm/mve-vaddsub-it-bad.s | 11 +++++++++++
gas/testsuite/gas/arm/mve-vaddsub-it.d | 23 +++++++++++++++++++++++
gas/testsuite/gas/arm/mve-vaddsub-it.s | 17 +++++++++++++++++
gas/testsuite/gas/arm/nomve-vaddsub-it.d | 24 ++++++++++++++++++++++++
8 files changed, 123 insertions(+), 3 deletions(-)
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 8f1cc8cde89..4ad599ae794 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,20 @@
+2020-03-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ Backport from mainline.
+ 2020-03-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ PR 25660
+ * config/tc-arm.c (operand_parse_code): Add OP_RNSDMQR and OP_oRNSDMQ.
+ (parse_operands): Handle new operand codes.
+ (do_neon_dyadic_long): Make shape check accept the scalar variants.
+ (asm_opcode_insns): Fix operand codes for vaddl and vsubl.
+ * testsuite/gas/arm/mve-vaddsub-it.s: New test.
+ * testsuite/gas/arm/mve-vaddsub-it.d: New test.
+ * testsuite/gas/arm/mve-vaddsub-it-bad.s: New test.
+ * testsuite/gas/arm/mve-vaddsub-it-bad.l: New test.
+ * testsuite/gas/arm/mve-vaddsub-it-bad.d: New test.
+ * testsuite/gas/arm/nomve-vaddsub-it.d: New test.
+
2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
PR gas/25516
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index bb0b03e35ea..2ee2718744e 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -7046,6 +7046,8 @@ enum operand_parse_code
OP_RNDMQ, /* Neon double precision (0..31) or MVE vector register. */
OP_RNDMQR, /* Neon double precision (0..31), MVE vector or ARM register.
*/
+ OP_RNSDMQR, /* Neon single or double precision, MVE vector or ARM register.
+ */
OP_RNQ, /* Neon quad precision register */
OP_RNQMQ, /* Neon quad or MVE vector register. */
OP_RVSD, /* VFP single or double precision register */
@@ -7195,6 +7197,8 @@ enum operand_parse_code
OP_oRNSDQ, /* Optional single, double or quad precision vector register */
OP_oRNSDQMQ, /* Optional single, double or quad register or MVE vector
register. */
+ OP_oRNSDMQ, /* Optional single, double register or MVE vector
+ register. */
OP_oSHll, /* LSL immediate */
OP_oSHar, /* ASR immediate */
OP_oSHllar, /* LSL or ASR immediate */
@@ -7391,6 +7395,10 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break;
case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break;
case OP_oRND:
+ case OP_RNSDMQR:
+ po_reg_or_goto (REG_TYPE_VFS, try_rndmqr);
+ break;
+ try_rndmqr:
case OP_RNDMQR:
po_reg_or_goto (REG_TYPE_RN, try_rndmq);
break;
@@ -7456,6 +7464,13 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
case OP_RVSD_COND:
po_reg_or_goto (REG_TYPE_VFSD, try_cond);
break;
+ case OP_oRNSDMQ:
+ case OP_RNSDMQ:
+ po_reg_or_goto (REG_TYPE_NSD, try_mq2);
+ break;
+ try_mq2:
+ po_reg_or_fail (REG_TYPE_MQ);
+ break;
case OP_oRNSDQ:
case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break;
case OP_RNSDQMQR:
@@ -19542,7 +19557,7 @@ neon_mixed_length (struct neon_type_el et, unsigned size)
static void
do_neon_dyadic_long (void)
{
- enum neon_shape rs = neon_select_shape (NS_QDD, NS_QQQ, NS_QQR, NS_NULL);
+ enum neon_shape rs = neon_select_shape (NS_QDD, NS_HHH, NS_FFF, NS_DDD, NS_NULL);
if (rs == NS_QDD)
{
if (vfp_or_neon_is_neon (NEON_CHECK_ARCH | NEON_CHECK_CC) == FAIL)
@@ -26039,8 +26054,8 @@ static const struct asm_opcode insns[] =
#define ARM_VARIANT & fpu_neon_ext_v1
mnUF(vabd, _vabd, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_if_su),
mnUF(vabdl, _vabdl, 3, (RNQMQ, RNDMQ, RNDMQ), neon_dyadic_long),
- mnUF(vaddl, _vaddl, 3, (RNQMQ, RNDMQ, RNDMQR), neon_dyadic_long),
- mnUF(vsubl, _vsubl, 3, (RNQMQ, RNDMQ, RNDMQR), neon_dyadic_long),
+ mnUF(vaddl, _vaddl, 3, (RNSDQMQ, oRNSDMQ, RNSDMQR), neon_dyadic_long),
+ mnUF(vsubl, _vsubl, 3, (RNSDQMQ, oRNSDMQ, RNSDMQR), neon_dyadic_long),
mnUF(vand, _vand, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic),
mnUF(vbic, _vbic, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic),
mnUF(vorr, _vorr, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic),
diff --git a/gas/testsuite/gas/arm/mve-vaddsub-it-bad.d b/gas/testsuite/gas/arm/mve-vaddsub-it-bad.d
new file mode 100644
index 00000000000..1889c216f1c
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vaddsub-it-bad.d
@@ -0,0 +1,6 @@
+#name: Bad MVE vadd/vsub instructions in IT blocks
+#as: -march=armv8.1-m.main+mve.fp
+#error_output: mve-vaddsub-it-bad.l
+
+.*: +file format .*arm.*
+
diff --git a/gas/testsuite/gas/arm/mve-vaddsub-it-bad.l b/gas/testsuite/gas/arm/mve-vaddsub-it-bad.l
new file mode 100644
index 00000000000..5f41bceaf40
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vaddsub-it-bad.l
@@ -0,0 +1,7 @@
+[^:]*: Assembler messages:
+[^:]*:4: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+[^:]*:5: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+[^:]*:7: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+[^:]*:8: Warning: ARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLE
+[^:]*:10: Error: selected FPU does not support instruction -- `vaddl.s8 q0,d1,d2'
+[^:]*:11: Error: selected FPU does not support instruction -- `vsubl.s8 q0,d1,d2'
diff --git a/gas/testsuite/gas/arm/mve-vaddsub-it-bad.s b/gas/testsuite/gas/arm/mve-vaddsub-it-bad.s
new file mode 100644
index 00000000000..180f9392dbf
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vaddsub-it-bad.s
@@ -0,0 +1,11 @@
+.syntax unified
+.text
+itt le
+vaddle.f16 s3, s5, s7
+vsuble.f16 s7, s4, s6
+itt lt
+vaddlt.f16 s0, s5, s7
+vsublt.f16 s7, s4, s6
+
+vaddl.s8 q0, d1, d2
+vsubl.s8 q0, d1, d2
diff --git a/gas/testsuite/gas/arm/mve-vaddsub-it.d b/gas/testsuite/gas/arm/mve-vaddsub-it.d
new file mode 100644
index 00000000000..e0842b733fc
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vaddsub-it.d
@@ -0,0 +1,23 @@
+# name: Armv8.1-M Mainline vadd/vsub instructions in it blocks (with MVE)
+# as: -march=armv8.1-m.main+mve.fp+fp.dp
+# objdump: -dr --prefix-addresses --show-raw-insn -marmv8.1-m.main
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+[^>]*> bfdc itt le
+[^>]*> ee72 1aa3 vaddle.f32 s3, s5, s7
+[^>]*> ee34 7b06 vaddle.f64 d7, d4, d6
+[^>]*> bfbc itt lt
+[^>]*> ee72 1aa3 vaddlt.f32 s3, s5, s7
+[^>]*> ee34 7b06 vaddlt.f64 d7, d4, d6
+[^>]*> bfdc itt le
+[^>]*> ee72 1ae3 vsuble.f32 s3, s5, s7
+[^>]*> ee34 7b46 vsuble.f64 d7, d4, d6
+[^>]*> bfbc itt lt
+[^>]*> ee72 1ae3 vsublt.f32 s3, s5, s7
+[^>]*> ee34 7b46 vsublt.f64 d7, d4, d6
+[^>]*> bfdc itt le
+[^>]*> ee30 0a06 vaddle.f32 s0, s0, s12
+[^>]*> ee30 0b41 vsuble.f64 d0, d0, d1
+#...
diff --git a/gas/testsuite/gas/arm/mve-vaddsub-it.s b/gas/testsuite/gas/arm/mve-vaddsub-it.s
new file mode 100644
index 00000000000..f086a73094c
--- /dev/null
+++ b/gas/testsuite/gas/arm/mve-vaddsub-it.s
@@ -0,0 +1,17 @@
+.syntax unified
+.text
+itt le
+vaddle.f32 s3, s5, s7
+vaddle.f64 d7, d4, d6
+itt lt
+vaddlt.f32 s3, s5, s7
+vaddlt.f64 d7, d4, d6
+itt le
+vsuble.f32 s3, s5, s7
+vsuble.f64 d7, d4, d6
+itt lt
+vsublt.f32 s3, s5, s7
+vsublt.f64 d7, d4, d6
+itt le
+vaddle.f32 s0, s12
+vsuble.f64 d0, d1
diff --git a/gas/testsuite/gas/arm/nomve-vaddsub-it.d b/gas/testsuite/gas/arm/nomve-vaddsub-it.d
new file mode 100644
index 00000000000..50b12a0d5de
--- /dev/null
+++ b/gas/testsuite/gas/arm/nomve-vaddsub-it.d
@@ -0,0 +1,24 @@
+# name: Armv8.1-M Mainline vadd/vsub instructions in it blocks (without MVE)
+# as: -march=armv8.1-m.main+fp.dp
+# source: mve-vaddsub-it.s
+# objdump: -dr --prefix-addresses --show-raw-insn -marmv8.1-m.main
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+[^>]*> bfdc itt le
+[^>]*> ee72 1aa3 vaddle.f32 s3, s5, s7
+[^>]*> ee34 7b06 vaddle.f64 d7, d4, d6
+[^>]*> bfbc itt lt
+[^>]*> ee72 1aa3 vaddlt.f32 s3, s5, s7
+[^>]*> ee34 7b06 vaddlt.f64 d7, d4, d6
+[^>]*> bfdc itt le
+[^>]*> ee72 1ae3 vsuble.f32 s3, s5, s7
+[^>]*> ee34 7b46 vsuble.f64 d7, d4, d6
+[^>]*> bfbc itt lt
+[^>]*> ee72 1ae3 vsublt.f32 s3, s5, s7
+[^>]*> ee34 7b46 vsublt.f64 d7, d4, d6
+[^>]*> bfdc itt le
+[^>]*> ee30 0a06 vaddle.f32 s0, s0, s12
+[^>]*> ee30 0b41 vsuble.f64 d0, d0, d1
+#...
More information about the Binutils-cvs
mailing list