[binutils-gdb] x86: use template for AVX/AVX512 floating point comparison insns
Jan Beulich
jbeulich@sourceware.org
Mon Mar 9 09:15:24 GMT 2020
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=3fabc17903800a7a943b811a5a20166f9a220ad6
commit 3fabc17903800a7a943b811a5a20166f9a220ad6
Author: Jan Beulich <jbeulich@suse.com>
Date: Mon Mar 9 10:13:43 2020 +0100
x86: use template for AVX/AVX512 floating point comparison insns
These all follow an almost common pattern, again with the exception of
being commutative, which can be easily taken care of.
Note that, as an intended side effect (and in fact one of the reason to
introduce templates), AVX long-form pseudo-ops get introduced alongside
the already existing AVX512 ones.
Diff:
---
gas/ChangeLog | 6 +
gas/testsuite/gas/i386/avx-16bit.d | 112 +
gas/testsuite/gas/i386/avx-intel.d | 112 +
gas/testsuite/gas/i386/avx.d | 112 +
gas/testsuite/gas/i386/avx.s | 112 +
opcodes/ChangeLog | 6 +
opcodes/i386-opc.tbl | 518 +-
opcodes/i386-tbl.h | 26060 ++++++++++++++++++-----------------
8 files changed, 13960 insertions(+), 13078 deletions(-)
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 5839ce82eb4..1ede132a0bd 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,9 @@
+2020-03-09 Jan Beulich <jbeulich@suse.com>
+
+ * testsuite/gas/i386/avx.s: Add long-form VCMP[PS][SD] pseudos.
+ * testsuite/gas/i386/avx.d, testsuite/gas/i386/avx-16bit.d,
+ testsuite/gas/i386/avx-intel.d: Adjust expectations.
+
2020-03-07 Alan Modra <amodra@gmail.com>
* testsuite/gas/elf/dwarf-5-file0.s: Don't start directives in
diff --git a/gas/testsuite/gas/i386/avx-16bit.d b/gas/testsuite/gas/i386/avx-16bit.d
index 1af604227c2..9f4207c1f92 100644
--- a/gas/testsuite/gas/i386/avx-16bit.d
+++ b/gas/testsuite/gas/i386/avx-16bit.d
@@ -89,34 +89,62 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 67 c5 cc 57 11 vxorps \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cd c2 d4 00 vcmpeqpd %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: 67 c5 cd c2 11 00 vcmpeqpd \(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cd c2 d4 00 vcmpeqpd %ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: 67 c5 cd c2 11 00 vcmpeqpd \(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cd c2 d4 01 vcmpltpd %ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: 67 c5 cd c2 11 01 vcmpltpd \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cd c2 d4 01 vcmpltpd %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: 67 c5 cd c2 11 01 vcmpltpd \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cd c2 d4 02 vcmplepd %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: 67 c5 cd c2 11 02 vcmplepd \(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cd c2 d4 02 vcmplepd %ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: 67 c5 cd c2 11 02 vcmplepd \(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cd c2 d4 03 vcmpunordpd %ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: 67 c5 cd c2 11 03 vcmpunordpd \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cd c2 d4 03 vcmpunordpd %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: 67 c5 cd c2 11 03 vcmpunordpd \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cd c2 d4 04 vcmpneqpd %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: 67 c5 cd c2 11 04 vcmpneqpd \(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cd c2 d4 04 vcmpneqpd %ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: 67 c5 cd c2 11 04 vcmpneqpd \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cd c2 d4 05 vcmpnltpd %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: 67 c5 cd c2 11 05 vcmpnltpd \(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cd c2 d4 05 vcmpnltpd %ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: 67 c5 cd c2 11 05 vcmpnltpd \(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cd c2 d4 06 vcmpnlepd %ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: 67 c5 cd c2 11 06 vcmpnlepd \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cd c2 d4 06 vcmpnlepd %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: 67 c5 cd c2 11 06 vcmpnlepd \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cd c2 d4 07 vcmpordpd %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: 67 c5 cd c2 11 07 vcmpordpd \(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cd c2 d4 07 vcmpordpd %ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: 67 c5 cd c2 11 07 vcmpordpd \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cd c2 d4 08 vcmpeq_uqpd %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: 67 c5 cd c2 11 08 vcmpeq_uqpd \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cd c2 d4 09 vcmpngepd %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: 67 c5 cd c2 11 09 vcmpngepd \(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cd c2 d4 09 vcmpngepd %ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: 67 c5 cd c2 11 09 vcmpngepd \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cd c2 d4 0a vcmpngtpd %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: 67 c5 cd c2 11 0a vcmpngtpd \(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cd c2 d4 0a vcmpngtpd %ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: 67 c5 cd c2 11 0a vcmpngtpd \(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cd c2 d4 0b vcmpfalsepd %ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: 67 c5 cd c2 11 0b vcmpfalsepd \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cd c2 d4 0b vcmpfalsepd %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: 67 c5 cd c2 11 0b vcmpfalsepd \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cd c2 d4 0c vcmpneq_oqpd %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: 67 c5 cd c2 11 0c vcmpneq_oqpd \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cd c2 d4 0d vcmpgepd %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: 67 c5 cd c2 11 0d vcmpgepd \(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cd c2 d4 0d vcmpgepd %ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: 67 c5 cd c2 11 0d vcmpgepd \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cd c2 d4 0e vcmpgtpd %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: 67 c5 cd c2 11 0e vcmpgtpd \(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cd c2 d4 0e vcmpgtpd %ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: 67 c5 cd c2 11 0e vcmpgtpd \(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cd c2 d4 0f vcmptruepd %ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: 67 c5 cd c2 11 0f vcmptruepd \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cd c2 d4 0f vcmptruepd %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: 67 c5 cd c2 11 0f vcmptruepd \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cd c2 d4 10 vcmpeq_ospd %ymm4,%ymm6,%ymm2
@@ -153,34 +181,62 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 67 c5 cd c2 11 1f vcmptrue_uspd \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c2 d4 00 vcmpeqps %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: 67 c5 cc c2 11 00 vcmpeqps \(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cc c2 d4 00 vcmpeqps %ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: 67 c5 cc c2 11 00 vcmpeqps \(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cc c2 d4 01 vcmpltps %ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: 67 c5 cc c2 11 01 vcmpltps \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c2 d4 01 vcmpltps %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: 67 c5 cc c2 11 01 vcmpltps \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c2 d4 02 vcmpleps %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: 67 c5 cc c2 11 02 vcmpleps \(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cc c2 d4 02 vcmpleps %ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: 67 c5 cc c2 11 02 vcmpleps \(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cc c2 d4 03 vcmpunordps %ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: 67 c5 cc c2 11 03 vcmpunordps \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c2 d4 03 vcmpunordps %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: 67 c5 cc c2 11 03 vcmpunordps \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c2 d4 04 vcmpneqps %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: 67 c5 cc c2 11 04 vcmpneqps \(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cc c2 d4 04 vcmpneqps %ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: 67 c5 cc c2 11 04 vcmpneqps \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c2 d4 05 vcmpnltps %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: 67 c5 cc c2 11 05 vcmpnltps \(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cc c2 d4 05 vcmpnltps %ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: 67 c5 cc c2 11 05 vcmpnltps \(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cc c2 d4 06 vcmpnleps %ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: 67 c5 cc c2 11 06 vcmpnleps \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c2 d4 06 vcmpnleps %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: 67 c5 cc c2 11 06 vcmpnleps \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c2 d4 07 vcmpordps %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: 67 c5 cc c2 11 07 vcmpordps \(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cc c2 d4 07 vcmpordps %ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: 67 c5 cc c2 11 07 vcmpordps \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c2 d4 08 vcmpeq_uqps %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: 67 c5 cc c2 11 08 vcmpeq_uqps \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c2 d4 09 vcmpngeps %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: 67 c5 cc c2 11 09 vcmpngeps \(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cc c2 d4 09 vcmpngeps %ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: 67 c5 cc c2 11 09 vcmpngeps \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c2 d4 0a vcmpngtps %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: 67 c5 cc c2 11 0a vcmpngtps \(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cc c2 d4 0a vcmpngtps %ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: 67 c5 cc c2 11 0a vcmpngtps \(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cc c2 d4 0b vcmpfalseps %ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: 67 c5 cc c2 11 0b vcmpfalseps \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c2 d4 0b vcmpfalseps %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: 67 c5 cc c2 11 0b vcmpfalseps \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c2 d4 0c vcmpneq_oqps %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: 67 c5 cc c2 11 0c vcmpneq_oqps \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c2 d4 0d vcmpgeps %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: 67 c5 cc c2 11 0d vcmpgeps \(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cc c2 d4 0d vcmpgeps %ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: 67 c5 cc c2 11 0d vcmpgeps \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c2 d4 0e vcmpgtps %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: 67 c5 cc c2 11 0e vcmpgtps \(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cc c2 d4 0e vcmpgtps %ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: 67 c5 cc c2 11 0e vcmpgtps \(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cc c2 d4 0f vcmptrueps %ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: 67 c5 cc c2 11 0f vcmptrueps \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c2 d4 0f vcmptrueps %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: 67 c5 cc c2 11 0f vcmptrueps \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c2 d4 10 vcmpeq_osps %ymm4,%ymm6,%ymm2
@@ -910,34 +966,62 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 67 c5 cb 5c 11 vsubsd \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb c2 d4 00 vcmpeqsd %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: 67 c5 cb c2 11 00 vcmpeqsd \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 cb c2 d4 00 vcmpeqsd %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: 67 c5 cb c2 11 00 vcmpeqsd \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 cb c2 d4 01 vcmpltsd %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: 67 c5 cb c2 11 01 vcmpltsd \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb c2 d4 01 vcmpltsd %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: 67 c5 cb c2 11 01 vcmpltsd \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb c2 d4 02 vcmplesd %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: 67 c5 cb c2 11 02 vcmplesd \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 cb c2 d4 02 vcmplesd %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: 67 c5 cb c2 11 02 vcmplesd \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 cb c2 d4 03 vcmpunordsd %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: 67 c5 cb c2 11 03 vcmpunordsd \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb c2 d4 03 vcmpunordsd %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: 67 c5 cb c2 11 03 vcmpunordsd \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb c2 d4 04 vcmpneqsd %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: 67 c5 cb c2 11 04 vcmpneqsd \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 cb c2 d4 04 vcmpneqsd %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: 67 c5 cb c2 11 04 vcmpneqsd \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb c2 d4 05 vcmpnltsd %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: 67 c5 cb c2 11 05 vcmpnltsd \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 cb c2 d4 05 vcmpnltsd %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: 67 c5 cb c2 11 05 vcmpnltsd \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 cb c2 d4 06 vcmpnlesd %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: 67 c5 cb c2 11 06 vcmpnlesd \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb c2 d4 06 vcmpnlesd %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: 67 c5 cb c2 11 06 vcmpnlesd \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb c2 d4 07 vcmpordsd %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: 67 c5 cb c2 11 07 vcmpordsd \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 cb c2 d4 07 vcmpordsd %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: 67 c5 cb c2 11 07 vcmpordsd \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb c2 d4 08 vcmpeq_uqsd %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: 67 c5 cb c2 11 08 vcmpeq_uqsd \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb c2 d4 09 vcmpngesd %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: 67 c5 cb c2 11 09 vcmpngesd \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 cb c2 d4 09 vcmpngesd %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: 67 c5 cb c2 11 09 vcmpngesd \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb c2 d4 0a vcmpngtsd %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: 67 c5 cb c2 11 0a vcmpngtsd \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 cb c2 d4 0a vcmpngtsd %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: 67 c5 cb c2 11 0a vcmpngtsd \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 cb c2 d4 0b vcmpfalsesd %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: 67 c5 cb c2 11 0b vcmpfalsesd \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb c2 d4 0b vcmpfalsesd %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: 67 c5 cb c2 11 0b vcmpfalsesd \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb c2 d4 0c vcmpneq_oqsd %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: 67 c5 cb c2 11 0c vcmpneq_oqsd \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb c2 d4 0d vcmpgesd %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: 67 c5 cb c2 11 0d vcmpgesd \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 cb c2 d4 0d vcmpgesd %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: 67 c5 cb c2 11 0d vcmpgesd \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb c2 d4 0e vcmpgtsd %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: 67 c5 cb c2 11 0e vcmpgtsd \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 cb c2 d4 0e vcmpgtsd %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: 67 c5 cb c2 11 0e vcmpgtsd \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 cb c2 d4 0f vcmptruesd %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: 67 c5 cb c2 11 0f vcmptruesd \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb c2 d4 0f vcmptruesd %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: 67 c5 cb c2 11 0f vcmptruesd \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb c2 d4 10 vcmpeq_ossd %xmm4,%xmm6,%xmm2
@@ -996,34 +1080,62 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 67 c5 ca 5c 11 vsubss \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 ca c2 d4 00 vcmpeqss %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: 67 c5 ca c2 11 00 vcmpeqss \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 ca c2 d4 00 vcmpeqss %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: 67 c5 ca c2 11 00 vcmpeqss \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 ca c2 d4 01 vcmpltss %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: 67 c5 ca c2 11 01 vcmpltss \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 ca c2 d4 01 vcmpltss %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: 67 c5 ca c2 11 01 vcmpltss \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 ca c2 d4 02 vcmpless %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: 67 c5 ca c2 11 02 vcmpless \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 ca c2 d4 02 vcmpless %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: 67 c5 ca c2 11 02 vcmpless \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 ca c2 d4 03 vcmpunordss %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: 67 c5 ca c2 11 03 vcmpunordss \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 ca c2 d4 03 vcmpunordss %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: 67 c5 ca c2 11 03 vcmpunordss \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 ca c2 d4 04 vcmpneqss %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: 67 c5 ca c2 11 04 vcmpneqss \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 ca c2 d4 04 vcmpneqss %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: 67 c5 ca c2 11 04 vcmpneqss \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 ca c2 d4 05 vcmpnltss %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: 67 c5 ca c2 11 05 vcmpnltss \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 ca c2 d4 05 vcmpnltss %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: 67 c5 ca c2 11 05 vcmpnltss \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 ca c2 d4 06 vcmpnless %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: 67 c5 ca c2 11 06 vcmpnless \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 ca c2 d4 06 vcmpnless %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: 67 c5 ca c2 11 06 vcmpnless \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 ca c2 d4 07 vcmpordss %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: 67 c5 ca c2 11 07 vcmpordss \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 ca c2 d4 07 vcmpordss %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: 67 c5 ca c2 11 07 vcmpordss \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 ca c2 d4 08 vcmpeq_uqss %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: 67 c5 ca c2 11 08 vcmpeq_uqss \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 ca c2 d4 09 vcmpngess %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: 67 c5 ca c2 11 09 vcmpngess \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 ca c2 d4 09 vcmpngess %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: 67 c5 ca c2 11 09 vcmpngess \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 ca c2 d4 0a vcmpngtss %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: 67 c5 ca c2 11 0a vcmpngtss \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 ca c2 d4 0a vcmpngtss %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: 67 c5 ca c2 11 0a vcmpngtss \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 ca c2 d4 0b vcmpfalsess %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: 67 c5 ca c2 11 0b vcmpfalsess \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 ca c2 d4 0b vcmpfalsess %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: 67 c5 ca c2 11 0b vcmpfalsess \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 ca c2 d4 0c vcmpneq_oqss %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: 67 c5 ca c2 11 0c vcmpneq_oqss \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 ca c2 d4 0d vcmpgess %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: 67 c5 ca c2 11 0d vcmpgess \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 ca c2 d4 0d vcmpgess %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: 67 c5 ca c2 11 0d vcmpgess \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 ca c2 d4 0e vcmpgtss %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: 67 c5 ca c2 11 0e vcmpgtss \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 ca c2 d4 0e vcmpgtss %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: 67 c5 ca c2 11 0e vcmpgtss \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 ca c2 d4 0f vcmptruess %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: 67 c5 ca c2 11 0f vcmptruess \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 ca c2 d4 0f vcmptruess %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: 67 c5 ca c2 11 0f vcmptruess \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 ca c2 d4 10 vcmpeq_osss %xmm4,%xmm6,%xmm2
diff --git a/gas/testsuite/gas/i386/avx-intel.d b/gas/testsuite/gas/i386/avx-intel.d
index bc5485e6759..85a329b0daf 100644
--- a/gas/testsuite/gas/i386/avx-intel.d
+++ b/gas/testsuite/gas/i386/avx-intel.d
@@ -89,34 +89,62 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c5 cc 57 11 vxorps ymm2,ymm6,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 cd c2 d4 00 vcmpeqpd ymm2,ymm6,ymm4
[ ]*[a-f0-9]+: c5 cd c2 11 00 vcmpeqpd ymm2,ymm6,YMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 cd c2 d4 00 vcmpeqpd ymm2,ymm6,ymm4
+[ ]*[a-f0-9]+: c5 cd c2 11 00 vcmpeqpd ymm2,ymm6,YMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 cd c2 d4 01 vcmpltpd ymm2,ymm6,ymm4
+[ ]*[a-f0-9]+: c5 cd c2 11 01 vcmpltpd ymm2,ymm6,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 cd c2 d4 01 vcmpltpd ymm2,ymm6,ymm4
[ ]*[a-f0-9]+: c5 cd c2 11 01 vcmpltpd ymm2,ymm6,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 cd c2 d4 02 vcmplepd ymm2,ymm6,ymm4
[ ]*[a-f0-9]+: c5 cd c2 11 02 vcmplepd ymm2,ymm6,YMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 cd c2 d4 02 vcmplepd ymm2,ymm6,ymm4
+[ ]*[a-f0-9]+: c5 cd c2 11 02 vcmplepd ymm2,ymm6,YMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 cd c2 d4 03 vcmpunordpd ymm2,ymm6,ymm4
+[ ]*[a-f0-9]+: c5 cd c2 11 03 vcmpunordpd ymm2,ymm6,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 cd c2 d4 03 vcmpunordpd ymm2,ymm6,ymm4
[ ]*[a-f0-9]+: c5 cd c2 11 03 vcmpunordpd ymm2,ymm6,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 cd c2 d4 04 vcmpneqpd ymm2,ymm6,ymm4
[ ]*[a-f0-9]+: c5 cd c2 11 04 vcmpneqpd ymm2,ymm6,YMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 cd c2 d4 04 vcmpneqpd ymm2,ymm6,ymm4
+[ ]*[a-f0-9]+: c5 cd c2 11 04 vcmpneqpd ymm2,ymm6,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 cd c2 d4 05 vcmpnltpd ymm2,ymm6,ymm4
[ ]*[a-f0-9]+: c5 cd c2 11 05 vcmpnltpd ymm2,ymm6,YMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 cd c2 d4 05 vcmpnltpd ymm2,ymm6,ymm4
+[ ]*[a-f0-9]+: c5 cd c2 11 05 vcmpnltpd ymm2,ymm6,YMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 cd c2 d4 06 vcmpnlepd ymm2,ymm6,ymm4
+[ ]*[a-f0-9]+: c5 cd c2 11 06 vcmpnlepd ymm2,ymm6,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 cd c2 d4 06 vcmpnlepd ymm2,ymm6,ymm4
[ ]*[a-f0-9]+: c5 cd c2 11 06 vcmpnlepd ymm2,ymm6,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 cd c2 d4 07 vcmpordpd ymm2,ymm6,ymm4
[ ]*[a-f0-9]+: c5 cd c2 11 07 vcmpordpd ymm2,ymm6,YMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 cd c2 d4 07 vcmpordpd ymm2,ymm6,ymm4
+[ ]*[a-f0-9]+: c5 cd c2 11 07 vcmpordpd ymm2,ymm6,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 cd c2 d4 08 vcmpeq_uqpd ymm2,ymm6,ymm4
[ ]*[a-f0-9]+: c5 cd c2 11 08 vcmpeq_uqpd ymm2,ymm6,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 cd c2 d4 09 vcmpngepd ymm2,ymm6,ymm4
[ ]*[a-f0-9]+: c5 cd c2 11 09 vcmpngepd ymm2,ymm6,YMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 cd c2 d4 09 vcmpngepd ymm2,ymm6,ymm4
+[ ]*[a-f0-9]+: c5 cd c2 11 09 vcmpngepd ymm2,ymm6,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 cd c2 d4 0a vcmpngtpd ymm2,ymm6,ymm4
[ ]*[a-f0-9]+: c5 cd c2 11 0a vcmpngtpd ymm2,ymm6,YMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 cd c2 d4 0a vcmpngtpd ymm2,ymm6,ymm4
+[ ]*[a-f0-9]+: c5 cd c2 11 0a vcmpngtpd ymm2,ymm6,YMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 cd c2 d4 0b vcmpfalsepd ymm2,ymm6,ymm4
+[ ]*[a-f0-9]+: c5 cd c2 11 0b vcmpfalsepd ymm2,ymm6,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 cd c2 d4 0b vcmpfalsepd ymm2,ymm6,ymm4
[ ]*[a-f0-9]+: c5 cd c2 11 0b vcmpfalsepd ymm2,ymm6,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 cd c2 d4 0c vcmpneq_oqpd ymm2,ymm6,ymm4
[ ]*[a-f0-9]+: c5 cd c2 11 0c vcmpneq_oqpd ymm2,ymm6,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 cd c2 d4 0d vcmpgepd ymm2,ymm6,ymm4
[ ]*[a-f0-9]+: c5 cd c2 11 0d vcmpgepd ymm2,ymm6,YMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 cd c2 d4 0d vcmpgepd ymm2,ymm6,ymm4
+[ ]*[a-f0-9]+: c5 cd c2 11 0d vcmpgepd ymm2,ymm6,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 cd c2 d4 0e vcmpgtpd ymm2,ymm6,ymm4
[ ]*[a-f0-9]+: c5 cd c2 11 0e vcmpgtpd ymm2,ymm6,YMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 cd c2 d4 0e vcmpgtpd ymm2,ymm6,ymm4
+[ ]*[a-f0-9]+: c5 cd c2 11 0e vcmpgtpd ymm2,ymm6,YMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 cd c2 d4 0f vcmptruepd ymm2,ymm6,ymm4
+[ ]*[a-f0-9]+: c5 cd c2 11 0f vcmptruepd ymm2,ymm6,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 cd c2 d4 0f vcmptruepd ymm2,ymm6,ymm4
[ ]*[a-f0-9]+: c5 cd c2 11 0f vcmptruepd ymm2,ymm6,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 cd c2 d4 10 vcmpeq_ospd ymm2,ymm6,ymm4
@@ -153,34 +181,62 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c5 cd c2 11 1f vcmptrue_uspd ymm2,ymm6,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 cc c2 d4 00 vcmpeqps ymm2,ymm6,ymm4
[ ]*[a-f0-9]+: c5 cc c2 11 00 vcmpeqps ymm2,ymm6,YMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 cc c2 d4 00 vcmpeqps ymm2,ymm6,ymm4
+[ ]*[a-f0-9]+: c5 cc c2 11 00 vcmpeqps ymm2,ymm6,YMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 cc c2 d4 01 vcmpltps ymm2,ymm6,ymm4
+[ ]*[a-f0-9]+: c5 cc c2 11 01 vcmpltps ymm2,ymm6,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 cc c2 d4 01 vcmpltps ymm2,ymm6,ymm4
[ ]*[a-f0-9]+: c5 cc c2 11 01 vcmpltps ymm2,ymm6,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 cc c2 d4 02 vcmpleps ymm2,ymm6,ymm4
[ ]*[a-f0-9]+: c5 cc c2 11 02 vcmpleps ymm2,ymm6,YMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 cc c2 d4 02 vcmpleps ymm2,ymm6,ymm4
+[ ]*[a-f0-9]+: c5 cc c2 11 02 vcmpleps ymm2,ymm6,YMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 cc c2 d4 03 vcmpunordps ymm2,ymm6,ymm4
+[ ]*[a-f0-9]+: c5 cc c2 11 03 vcmpunordps ymm2,ymm6,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 cc c2 d4 03 vcmpunordps ymm2,ymm6,ymm4
[ ]*[a-f0-9]+: c5 cc c2 11 03 vcmpunordps ymm2,ymm6,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 cc c2 d4 04 vcmpneqps ymm2,ymm6,ymm4
[ ]*[a-f0-9]+: c5 cc c2 11 04 vcmpneqps ymm2,ymm6,YMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 cc c2 d4 04 vcmpneqps ymm2,ymm6,ymm4
+[ ]*[a-f0-9]+: c5 cc c2 11 04 vcmpneqps ymm2,ymm6,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 cc c2 d4 05 vcmpnltps ymm2,ymm6,ymm4
[ ]*[a-f0-9]+: c5 cc c2 11 05 vcmpnltps ymm2,ymm6,YMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 cc c2 d4 05 vcmpnltps ymm2,ymm6,ymm4
+[ ]*[a-f0-9]+: c5 cc c2 11 05 vcmpnltps ymm2,ymm6,YMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 cc c2 d4 06 vcmpnleps ymm2,ymm6,ymm4
+[ ]*[a-f0-9]+: c5 cc c2 11 06 vcmpnleps ymm2,ymm6,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 cc c2 d4 06 vcmpnleps ymm2,ymm6,ymm4
[ ]*[a-f0-9]+: c5 cc c2 11 06 vcmpnleps ymm2,ymm6,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 cc c2 d4 07 vcmpordps ymm2,ymm6,ymm4
[ ]*[a-f0-9]+: c5 cc c2 11 07 vcmpordps ymm2,ymm6,YMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 cc c2 d4 07 vcmpordps ymm2,ymm6,ymm4
+[ ]*[a-f0-9]+: c5 cc c2 11 07 vcmpordps ymm2,ymm6,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 cc c2 d4 08 vcmpeq_uqps ymm2,ymm6,ymm4
[ ]*[a-f0-9]+: c5 cc c2 11 08 vcmpeq_uqps ymm2,ymm6,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 cc c2 d4 09 vcmpngeps ymm2,ymm6,ymm4
[ ]*[a-f0-9]+: c5 cc c2 11 09 vcmpngeps ymm2,ymm6,YMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 cc c2 d4 09 vcmpngeps ymm2,ymm6,ymm4
+[ ]*[a-f0-9]+: c5 cc c2 11 09 vcmpngeps ymm2,ymm6,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 cc c2 d4 0a vcmpngtps ymm2,ymm6,ymm4
[ ]*[a-f0-9]+: c5 cc c2 11 0a vcmpngtps ymm2,ymm6,YMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 cc c2 d4 0a vcmpngtps ymm2,ymm6,ymm4
+[ ]*[a-f0-9]+: c5 cc c2 11 0a vcmpngtps ymm2,ymm6,YMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 cc c2 d4 0b vcmpfalseps ymm2,ymm6,ymm4
+[ ]*[a-f0-9]+: c5 cc c2 11 0b vcmpfalseps ymm2,ymm6,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 cc c2 d4 0b vcmpfalseps ymm2,ymm6,ymm4
[ ]*[a-f0-9]+: c5 cc c2 11 0b vcmpfalseps ymm2,ymm6,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 cc c2 d4 0c vcmpneq_oqps ymm2,ymm6,ymm4
[ ]*[a-f0-9]+: c5 cc c2 11 0c vcmpneq_oqps ymm2,ymm6,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 cc c2 d4 0d vcmpgeps ymm2,ymm6,ymm4
[ ]*[a-f0-9]+: c5 cc c2 11 0d vcmpgeps ymm2,ymm6,YMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 cc c2 d4 0d vcmpgeps ymm2,ymm6,ymm4
+[ ]*[a-f0-9]+: c5 cc c2 11 0d vcmpgeps ymm2,ymm6,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 cc c2 d4 0e vcmpgtps ymm2,ymm6,ymm4
[ ]*[a-f0-9]+: c5 cc c2 11 0e vcmpgtps ymm2,ymm6,YMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 cc c2 d4 0e vcmpgtps ymm2,ymm6,ymm4
+[ ]*[a-f0-9]+: c5 cc c2 11 0e vcmpgtps ymm2,ymm6,YMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 cc c2 d4 0f vcmptrueps ymm2,ymm6,ymm4
+[ ]*[a-f0-9]+: c5 cc c2 11 0f vcmptrueps ymm2,ymm6,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 cc c2 d4 0f vcmptrueps ymm2,ymm6,ymm4
[ ]*[a-f0-9]+: c5 cc c2 11 0f vcmptrueps ymm2,ymm6,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 cc c2 d4 10 vcmpeq_osps ymm2,ymm6,ymm4
@@ -910,34 +966,62 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c5 cb 5c 11 vsubsd xmm2,xmm6,QWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 cb c2 d4 00 vcmpeqsd xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c5 cb c2 11 00 vcmpeqsd xmm2,xmm6,QWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 cb c2 d4 00 vcmpeqsd xmm2,xmm6,xmm4
+[ ]*[a-f0-9]+: c5 cb c2 11 00 vcmpeqsd xmm2,xmm6,QWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 cb c2 d4 01 vcmpltsd xmm2,xmm6,xmm4
+[ ]*[a-f0-9]+: c5 cb c2 11 01 vcmpltsd xmm2,xmm6,QWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 cb c2 d4 01 vcmpltsd xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c5 cb c2 11 01 vcmpltsd xmm2,xmm6,QWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 cb c2 d4 02 vcmplesd xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c5 cb c2 11 02 vcmplesd xmm2,xmm6,QWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 cb c2 d4 02 vcmplesd xmm2,xmm6,xmm4
+[ ]*[a-f0-9]+: c5 cb c2 11 02 vcmplesd xmm2,xmm6,QWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 cb c2 d4 03 vcmpunordsd xmm2,xmm6,xmm4
+[ ]*[a-f0-9]+: c5 cb c2 11 03 vcmpunordsd xmm2,xmm6,QWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 cb c2 d4 03 vcmpunordsd xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c5 cb c2 11 03 vcmpunordsd xmm2,xmm6,QWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 cb c2 d4 04 vcmpneqsd xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c5 cb c2 11 04 vcmpneqsd xmm2,xmm6,QWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 cb c2 d4 04 vcmpneqsd xmm2,xmm6,xmm4
+[ ]*[a-f0-9]+: c5 cb c2 11 04 vcmpneqsd xmm2,xmm6,QWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 cb c2 d4 05 vcmpnltsd xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c5 cb c2 11 05 vcmpnltsd xmm2,xmm6,QWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 cb c2 d4 05 vcmpnltsd xmm2,xmm6,xmm4
+[ ]*[a-f0-9]+: c5 cb c2 11 05 vcmpnltsd xmm2,xmm6,QWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 cb c2 d4 06 vcmpnlesd xmm2,xmm6,xmm4
+[ ]*[a-f0-9]+: c5 cb c2 11 06 vcmpnlesd xmm2,xmm6,QWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 cb c2 d4 06 vcmpnlesd xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c5 cb c2 11 06 vcmpnlesd xmm2,xmm6,QWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 cb c2 d4 07 vcmpordsd xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c5 cb c2 11 07 vcmpordsd xmm2,xmm6,QWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 cb c2 d4 07 vcmpordsd xmm2,xmm6,xmm4
+[ ]*[a-f0-9]+: c5 cb c2 11 07 vcmpordsd xmm2,xmm6,QWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 cb c2 d4 08 vcmpeq_uqsd xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c5 cb c2 11 08 vcmpeq_uqsd xmm2,xmm6,QWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 cb c2 d4 09 vcmpngesd xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c5 cb c2 11 09 vcmpngesd xmm2,xmm6,QWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 cb c2 d4 09 vcmpngesd xmm2,xmm6,xmm4
+[ ]*[a-f0-9]+: c5 cb c2 11 09 vcmpngesd xmm2,xmm6,QWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 cb c2 d4 0a vcmpngtsd xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c5 cb c2 11 0a vcmpngtsd xmm2,xmm6,QWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 cb c2 d4 0a vcmpngtsd xmm2,xmm6,xmm4
+[ ]*[a-f0-9]+: c5 cb c2 11 0a vcmpngtsd xmm2,xmm6,QWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 cb c2 d4 0b vcmpfalsesd xmm2,xmm6,xmm4
+[ ]*[a-f0-9]+: c5 cb c2 11 0b vcmpfalsesd xmm2,xmm6,QWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 cb c2 d4 0b vcmpfalsesd xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c5 cb c2 11 0b vcmpfalsesd xmm2,xmm6,QWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 cb c2 d4 0c vcmpneq_oqsd xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c5 cb c2 11 0c vcmpneq_oqsd xmm2,xmm6,QWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 cb c2 d4 0d vcmpgesd xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c5 cb c2 11 0d vcmpgesd xmm2,xmm6,QWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 cb c2 d4 0d vcmpgesd xmm2,xmm6,xmm4
+[ ]*[a-f0-9]+: c5 cb c2 11 0d vcmpgesd xmm2,xmm6,QWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 cb c2 d4 0e vcmpgtsd xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c5 cb c2 11 0e vcmpgtsd xmm2,xmm6,QWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 cb c2 d4 0e vcmpgtsd xmm2,xmm6,xmm4
+[ ]*[a-f0-9]+: c5 cb c2 11 0e vcmpgtsd xmm2,xmm6,QWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 cb c2 d4 0f vcmptruesd xmm2,xmm6,xmm4
+[ ]*[a-f0-9]+: c5 cb c2 11 0f vcmptruesd xmm2,xmm6,QWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 cb c2 d4 0f vcmptruesd xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c5 cb c2 11 0f vcmptruesd xmm2,xmm6,QWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 cb c2 d4 10 vcmpeq_ossd xmm2,xmm6,xmm4
@@ -996,34 +1080,62 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c5 ca 5c 11 vsubss xmm2,xmm6,DWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 ca c2 d4 00 vcmpeqss xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c5 ca c2 11 00 vcmpeqss xmm2,xmm6,DWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 ca c2 d4 00 vcmpeqss xmm2,xmm6,xmm4
+[ ]*[a-f0-9]+: c5 ca c2 11 00 vcmpeqss xmm2,xmm6,DWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 ca c2 d4 01 vcmpltss xmm2,xmm6,xmm4
+[ ]*[a-f0-9]+: c5 ca c2 11 01 vcmpltss xmm2,xmm6,DWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 ca c2 d4 01 vcmpltss xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c5 ca c2 11 01 vcmpltss xmm2,xmm6,DWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 ca c2 d4 02 vcmpless xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c5 ca c2 11 02 vcmpless xmm2,xmm6,DWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 ca c2 d4 02 vcmpless xmm2,xmm6,xmm4
+[ ]*[a-f0-9]+: c5 ca c2 11 02 vcmpless xmm2,xmm6,DWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 ca c2 d4 03 vcmpunordss xmm2,xmm6,xmm4
+[ ]*[a-f0-9]+: c5 ca c2 11 03 vcmpunordss xmm2,xmm6,DWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 ca c2 d4 03 vcmpunordss xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c5 ca c2 11 03 vcmpunordss xmm2,xmm6,DWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 ca c2 d4 04 vcmpneqss xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c5 ca c2 11 04 vcmpneqss xmm2,xmm6,DWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 ca c2 d4 04 vcmpneqss xmm2,xmm6,xmm4
+[ ]*[a-f0-9]+: c5 ca c2 11 04 vcmpneqss xmm2,xmm6,DWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 ca c2 d4 05 vcmpnltss xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c5 ca c2 11 05 vcmpnltss xmm2,xmm6,DWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 ca c2 d4 05 vcmpnltss xmm2,xmm6,xmm4
+[ ]*[a-f0-9]+: c5 ca c2 11 05 vcmpnltss xmm2,xmm6,DWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 ca c2 d4 06 vcmpnless xmm2,xmm6,xmm4
+[ ]*[a-f0-9]+: c5 ca c2 11 06 vcmpnless xmm2,xmm6,DWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 ca c2 d4 06 vcmpnless xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c5 ca c2 11 06 vcmpnless xmm2,xmm6,DWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 ca c2 d4 07 vcmpordss xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c5 ca c2 11 07 vcmpordss xmm2,xmm6,DWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 ca c2 d4 07 vcmpordss xmm2,xmm6,xmm4
+[ ]*[a-f0-9]+: c5 ca c2 11 07 vcmpordss xmm2,xmm6,DWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 ca c2 d4 08 vcmpeq_uqss xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c5 ca c2 11 08 vcmpeq_uqss xmm2,xmm6,DWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 ca c2 d4 09 vcmpngess xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c5 ca c2 11 09 vcmpngess xmm2,xmm6,DWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 ca c2 d4 09 vcmpngess xmm2,xmm6,xmm4
+[ ]*[a-f0-9]+: c5 ca c2 11 09 vcmpngess xmm2,xmm6,DWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 ca c2 d4 0a vcmpngtss xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c5 ca c2 11 0a vcmpngtss xmm2,xmm6,DWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 ca c2 d4 0a vcmpngtss xmm2,xmm6,xmm4
+[ ]*[a-f0-9]+: c5 ca c2 11 0a vcmpngtss xmm2,xmm6,DWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 ca c2 d4 0b vcmpfalsess xmm2,xmm6,xmm4
+[ ]*[a-f0-9]+: c5 ca c2 11 0b vcmpfalsess xmm2,xmm6,DWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 ca c2 d4 0b vcmpfalsess xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c5 ca c2 11 0b vcmpfalsess xmm2,xmm6,DWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 ca c2 d4 0c vcmpneq_oqss xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c5 ca c2 11 0c vcmpneq_oqss xmm2,xmm6,DWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 ca c2 d4 0d vcmpgess xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c5 ca c2 11 0d vcmpgess xmm2,xmm6,DWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 ca c2 d4 0d vcmpgess xmm2,xmm6,xmm4
+[ ]*[a-f0-9]+: c5 ca c2 11 0d vcmpgess xmm2,xmm6,DWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 ca c2 d4 0e vcmpgtss xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c5 ca c2 11 0e vcmpgtss xmm2,xmm6,DWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 ca c2 d4 0e vcmpgtss xmm2,xmm6,xmm4
+[ ]*[a-f0-9]+: c5 ca c2 11 0e vcmpgtss xmm2,xmm6,DWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c5 ca c2 d4 0f vcmptruess xmm2,xmm6,xmm4
+[ ]*[a-f0-9]+: c5 ca c2 11 0f vcmptruess xmm2,xmm6,DWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 ca c2 d4 0f vcmptruess xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c5 ca c2 11 0f vcmptruess xmm2,xmm6,DWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 ca c2 d4 10 vcmpeq_osss xmm2,xmm6,xmm4
diff --git a/gas/testsuite/gas/i386/avx.d b/gas/testsuite/gas/i386/avx.d
index 643560867c1..d25e0e33eba 100644
--- a/gas/testsuite/gas/i386/avx.d
+++ b/gas/testsuite/gas/i386/avx.d
@@ -88,34 +88,62 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c5 cc 57 11 vxorps \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cd c2 d4 00 vcmpeqpd %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cd c2 11 00 vcmpeqpd \(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cd c2 d4 00 vcmpeqpd %ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cd c2 11 00 vcmpeqpd \(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cd c2 d4 01 vcmpltpd %ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cd c2 11 01 vcmpltpd \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cd c2 d4 01 vcmpltpd %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cd c2 11 01 vcmpltpd \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cd c2 d4 02 vcmplepd %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cd c2 11 02 vcmplepd \(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cd c2 d4 02 vcmplepd %ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cd c2 11 02 vcmplepd \(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cd c2 d4 03 vcmpunordpd %ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cd c2 11 03 vcmpunordpd \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cd c2 d4 03 vcmpunordpd %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cd c2 11 03 vcmpunordpd \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cd c2 d4 04 vcmpneqpd %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cd c2 11 04 vcmpneqpd \(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cd c2 d4 04 vcmpneqpd %ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cd c2 11 04 vcmpneqpd \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cd c2 d4 05 vcmpnltpd %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cd c2 11 05 vcmpnltpd \(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cd c2 d4 05 vcmpnltpd %ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cd c2 11 05 vcmpnltpd \(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cd c2 d4 06 vcmpnlepd %ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cd c2 11 06 vcmpnlepd \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cd c2 d4 06 vcmpnlepd %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cd c2 11 06 vcmpnlepd \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cd c2 d4 07 vcmpordpd %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cd c2 11 07 vcmpordpd \(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cd c2 d4 07 vcmpordpd %ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cd c2 11 07 vcmpordpd \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cd c2 d4 08 vcmpeq_uqpd %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cd c2 11 08 vcmpeq_uqpd \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cd c2 d4 09 vcmpngepd %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cd c2 11 09 vcmpngepd \(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cd c2 d4 09 vcmpngepd %ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cd c2 11 09 vcmpngepd \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cd c2 d4 0a vcmpngtpd %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cd c2 11 0a vcmpngtpd \(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cd c2 d4 0a vcmpngtpd %ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cd c2 11 0a vcmpngtpd \(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cd c2 d4 0b vcmpfalsepd %ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cd c2 11 0b vcmpfalsepd \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cd c2 d4 0b vcmpfalsepd %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cd c2 11 0b vcmpfalsepd \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cd c2 d4 0c vcmpneq_oqpd %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cd c2 11 0c vcmpneq_oqpd \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cd c2 d4 0d vcmpgepd %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cd c2 11 0d vcmpgepd \(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cd c2 d4 0d vcmpgepd %ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cd c2 11 0d vcmpgepd \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cd c2 d4 0e vcmpgtpd %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cd c2 11 0e vcmpgtpd \(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cd c2 d4 0e vcmpgtpd %ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cd c2 11 0e vcmpgtpd \(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cd c2 d4 0f vcmptruepd %ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cd c2 11 0f vcmptruepd \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cd c2 d4 0f vcmptruepd %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cd c2 11 0f vcmptruepd \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cd c2 d4 10 vcmpeq_ospd %ymm4,%ymm6,%ymm2
@@ -152,34 +180,62 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c5 cd c2 11 1f vcmptrue_uspd \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c2 d4 00 vcmpeqps %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c2 11 00 vcmpeqps \(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cc c2 d4 00 vcmpeqps %ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cc c2 11 00 vcmpeqps \(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cc c2 d4 01 vcmpltps %ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cc c2 11 01 vcmpltps \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c2 d4 01 vcmpltps %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c2 11 01 vcmpltps \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c2 d4 02 vcmpleps %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c2 11 02 vcmpleps \(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cc c2 d4 02 vcmpleps %ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cc c2 11 02 vcmpleps \(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cc c2 d4 03 vcmpunordps %ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cc c2 11 03 vcmpunordps \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c2 d4 03 vcmpunordps %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c2 11 03 vcmpunordps \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c2 d4 04 vcmpneqps %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c2 11 04 vcmpneqps \(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cc c2 d4 04 vcmpneqps %ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cc c2 11 04 vcmpneqps \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c2 d4 05 vcmpnltps %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c2 11 05 vcmpnltps \(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cc c2 d4 05 vcmpnltps %ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cc c2 11 05 vcmpnltps \(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cc c2 d4 06 vcmpnleps %ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cc c2 11 06 vcmpnleps \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c2 d4 06 vcmpnleps %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c2 11 06 vcmpnleps \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c2 d4 07 vcmpordps %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c2 11 07 vcmpordps \(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cc c2 d4 07 vcmpordps %ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cc c2 11 07 vcmpordps \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c2 d4 08 vcmpeq_uqps %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c2 11 08 vcmpeq_uqps \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c2 d4 09 vcmpngeps %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c2 11 09 vcmpngeps \(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cc c2 d4 09 vcmpngeps %ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cc c2 11 09 vcmpngeps \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c2 d4 0a vcmpngtps %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c2 11 0a vcmpngtps \(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cc c2 d4 0a vcmpngtps %ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cc c2 11 0a vcmpngtps \(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cc c2 d4 0b vcmpfalseps %ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cc c2 11 0b vcmpfalseps \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c2 d4 0b vcmpfalseps %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c2 11 0b vcmpfalseps \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c2 d4 0c vcmpneq_oqps %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c2 11 0c vcmpneq_oqps \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c2 d4 0d vcmpgeps %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c2 11 0d vcmpgeps \(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cc c2 d4 0d vcmpgeps %ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cc c2 11 0d vcmpgeps \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c2 d4 0e vcmpgtps %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c2 11 0e vcmpgtps \(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cc c2 d4 0e vcmpgtps %ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cc c2 11 0e vcmpgtps \(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cc c2 d4 0f vcmptrueps %ymm4,%ymm6,%ymm2
+[ ]*[a-f0-9]+: c5 cc c2 11 0f vcmptrueps \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c2 d4 0f vcmptrueps %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c2 11 0f vcmptrueps \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c2 d4 10 vcmpeq_osps %ymm4,%ymm6,%ymm2
@@ -909,34 +965,62 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c5 cb 5c 11 vsubsd \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb c2 d4 00 vcmpeqsd %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb c2 11 00 vcmpeqsd \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 cb c2 d4 00 vcmpeqsd %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 cb c2 11 00 vcmpeqsd \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 cb c2 d4 01 vcmpltsd %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 cb c2 11 01 vcmpltsd \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb c2 d4 01 vcmpltsd %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb c2 11 01 vcmpltsd \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb c2 d4 02 vcmplesd %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb c2 11 02 vcmplesd \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 cb c2 d4 02 vcmplesd %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 cb c2 11 02 vcmplesd \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 cb c2 d4 03 vcmpunordsd %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 cb c2 11 03 vcmpunordsd \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb c2 d4 03 vcmpunordsd %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb c2 11 03 vcmpunordsd \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb c2 d4 04 vcmpneqsd %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb c2 11 04 vcmpneqsd \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 cb c2 d4 04 vcmpneqsd %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 cb c2 11 04 vcmpneqsd \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb c2 d4 05 vcmpnltsd %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb c2 11 05 vcmpnltsd \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 cb c2 d4 05 vcmpnltsd %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 cb c2 11 05 vcmpnltsd \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 cb c2 d4 06 vcmpnlesd %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 cb c2 11 06 vcmpnlesd \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb c2 d4 06 vcmpnlesd %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb c2 11 06 vcmpnlesd \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb c2 d4 07 vcmpordsd %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb c2 11 07 vcmpordsd \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 cb c2 d4 07 vcmpordsd %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 cb c2 11 07 vcmpordsd \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb c2 d4 08 vcmpeq_uqsd %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb c2 11 08 vcmpeq_uqsd \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb c2 d4 09 vcmpngesd %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb c2 11 09 vcmpngesd \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 cb c2 d4 09 vcmpngesd %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 cb c2 11 09 vcmpngesd \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb c2 d4 0a vcmpngtsd %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb c2 11 0a vcmpngtsd \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 cb c2 d4 0a vcmpngtsd %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 cb c2 11 0a vcmpngtsd \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 cb c2 d4 0b vcmpfalsesd %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 cb c2 11 0b vcmpfalsesd \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb c2 d4 0b vcmpfalsesd %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb c2 11 0b vcmpfalsesd \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb c2 d4 0c vcmpneq_oqsd %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb c2 11 0c vcmpneq_oqsd \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb c2 d4 0d vcmpgesd %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb c2 11 0d vcmpgesd \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 cb c2 d4 0d vcmpgesd %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 cb c2 11 0d vcmpgesd \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb c2 d4 0e vcmpgtsd %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb c2 11 0e vcmpgtsd \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 cb c2 d4 0e vcmpgtsd %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 cb c2 11 0e vcmpgtsd \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 cb c2 d4 0f vcmptruesd %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 cb c2 11 0f vcmptruesd \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb c2 d4 0f vcmptruesd %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb c2 11 0f vcmptruesd \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 cb c2 d4 10 vcmpeq_ossd %xmm4,%xmm6,%xmm2
@@ -995,34 +1079,62 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c5 ca 5c 11 vsubss \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 ca c2 d4 00 vcmpeqss %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 ca c2 11 00 vcmpeqss \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 ca c2 d4 00 vcmpeqss %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 ca c2 11 00 vcmpeqss \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 ca c2 d4 01 vcmpltss %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 ca c2 11 01 vcmpltss \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 ca c2 d4 01 vcmpltss %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 ca c2 11 01 vcmpltss \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 ca c2 d4 02 vcmpless %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 ca c2 11 02 vcmpless \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 ca c2 d4 02 vcmpless %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 ca c2 11 02 vcmpless \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 ca c2 d4 03 vcmpunordss %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 ca c2 11 03 vcmpunordss \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 ca c2 d4 03 vcmpunordss %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 ca c2 11 03 vcmpunordss \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 ca c2 d4 04 vcmpneqss %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 ca c2 11 04 vcmpneqss \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 ca c2 d4 04 vcmpneqss %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 ca c2 11 04 vcmpneqss \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 ca c2 d4 05 vcmpnltss %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 ca c2 11 05 vcmpnltss \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 ca c2 d4 05 vcmpnltss %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 ca c2 11 05 vcmpnltss \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 ca c2 d4 06 vcmpnless %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 ca c2 11 06 vcmpnless \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 ca c2 d4 06 vcmpnless %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 ca c2 11 06 vcmpnless \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 ca c2 d4 07 vcmpordss %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 ca c2 11 07 vcmpordss \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 ca c2 d4 07 vcmpordss %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 ca c2 11 07 vcmpordss \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 ca c2 d4 08 vcmpeq_uqss %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 ca c2 11 08 vcmpeq_uqss \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 ca c2 d4 09 vcmpngess %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 ca c2 11 09 vcmpngess \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 ca c2 d4 09 vcmpngess %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 ca c2 11 09 vcmpngess \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 ca c2 d4 0a vcmpngtss %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 ca c2 11 0a vcmpngtss \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 ca c2 d4 0a vcmpngtss %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 ca c2 11 0a vcmpngtss \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 ca c2 d4 0b vcmpfalsess %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 ca c2 11 0b vcmpfalsess \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 ca c2 d4 0b vcmpfalsess %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 ca c2 11 0b vcmpfalsess \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 ca c2 d4 0c vcmpneq_oqss %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 ca c2 11 0c vcmpneq_oqss \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 ca c2 d4 0d vcmpgess %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 ca c2 11 0d vcmpgess \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 ca c2 d4 0d vcmpgess %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 ca c2 11 0d vcmpgess \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 ca c2 d4 0e vcmpgtss %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 ca c2 11 0e vcmpgtss \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 ca c2 d4 0e vcmpgtss %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 ca c2 11 0e vcmpgtss \(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 ca c2 d4 0f vcmptruess %xmm4,%xmm6,%xmm2
+[ ]*[a-f0-9]+: c5 ca c2 11 0f vcmptruess \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 ca c2 d4 0f vcmptruess %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 ca c2 11 0f vcmptruess \(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 ca c2 d4 10 vcmpeq_osss %xmm4,%xmm6,%xmm2
diff --git a/gas/testsuite/gas/i386/avx.s b/gas/testsuite/gas/i386/avx.s
index 0867dd22109..aaa87a61624 100644
--- a/gas/testsuite/gas/i386/avx.s
+++ b/gas/testsuite/gas/i386/avx.s
@@ -95,36 +95,64 @@ _start:
vxorps (%ecx),%ymm6,%ymm2
vcmpeqpd %ymm4,%ymm6,%ymm2
vcmpeqpd (%ecx),%ymm6,%ymm2
+ vcmpeq_oqpd %ymm4,%ymm6,%ymm2
+ vcmpeq_oqpd (%ecx),%ymm6,%ymm2
vcmpltpd %ymm4,%ymm6,%ymm2
vcmpltpd (%ecx),%ymm6,%ymm2
+ vcmplt_ospd %ymm4,%ymm6,%ymm2
+ vcmplt_ospd (%ecx),%ymm6,%ymm2
vcmplepd %ymm4,%ymm6,%ymm2
vcmplepd (%ecx),%ymm6,%ymm2
+ vcmple_ospd %ymm4,%ymm6,%ymm2
+ vcmple_ospd (%ecx),%ymm6,%ymm2
vcmpunordpd %ymm4,%ymm6,%ymm2
vcmpunordpd (%ecx),%ymm6,%ymm2
+ vcmpunord_qpd %ymm4,%ymm6,%ymm2
+ vcmpunord_qpd (%ecx),%ymm6,%ymm2
vcmpneqpd %ymm4,%ymm6,%ymm2
vcmpneqpd (%ecx),%ymm6,%ymm2
+ vcmpneq_uqpd %ymm4,%ymm6,%ymm2
+ vcmpneq_uqpd (%ecx),%ymm6,%ymm2
vcmpnltpd %ymm4,%ymm6,%ymm2
vcmpnltpd (%ecx),%ymm6,%ymm2
+ vcmpnlt_uspd %ymm4,%ymm6,%ymm2
+ vcmpnlt_uspd (%ecx),%ymm6,%ymm2
vcmpnlepd %ymm4,%ymm6,%ymm2
vcmpnlepd (%ecx),%ymm6,%ymm2
+ vcmpnle_uspd %ymm4,%ymm6,%ymm2
+ vcmpnle_uspd (%ecx),%ymm6,%ymm2
vcmpordpd %ymm4,%ymm6,%ymm2
vcmpordpd (%ecx),%ymm6,%ymm2
+ vcmpord_qpd %ymm4,%ymm6,%ymm2
+ vcmpord_qpd (%ecx),%ymm6,%ymm2
vcmpeq_uqpd %ymm4,%ymm6,%ymm2
vcmpeq_uqpd (%ecx),%ymm6,%ymm2
vcmpngepd %ymm4,%ymm6,%ymm2
vcmpngepd (%ecx),%ymm6,%ymm2
+ vcmpnge_uspd %ymm4,%ymm6,%ymm2
+ vcmpnge_uspd (%ecx),%ymm6,%ymm2
vcmpngtpd %ymm4,%ymm6,%ymm2
vcmpngtpd (%ecx),%ymm6,%ymm2
+ vcmpngt_uspd %ymm4,%ymm6,%ymm2
+ vcmpngt_uspd (%ecx),%ymm6,%ymm2
vcmpfalsepd %ymm4,%ymm6,%ymm2
vcmpfalsepd (%ecx),%ymm6,%ymm2
+ vcmpfalse_oqpd %ymm4,%ymm6,%ymm2
+ vcmpfalse_oqpd (%ecx),%ymm6,%ymm2
vcmpneq_oqpd %ymm4,%ymm6,%ymm2
vcmpneq_oqpd (%ecx),%ymm6,%ymm2
vcmpgepd %ymm4,%ymm6,%ymm2
vcmpgepd (%ecx),%ymm6,%ymm2
+ vcmpge_ospd %ymm4,%ymm6,%ymm2
+ vcmpge_ospd (%ecx),%ymm6,%ymm2
vcmpgtpd %ymm4,%ymm6,%ymm2
vcmpgtpd (%ecx),%ymm6,%ymm2
+ vcmpgt_ospd %ymm4,%ymm6,%ymm2
+ vcmpgt_ospd (%ecx),%ymm6,%ymm2
vcmptruepd %ymm4,%ymm6,%ymm2
vcmptruepd (%ecx),%ymm6,%ymm2
+ vcmptrue_uqpd %ymm4,%ymm6,%ymm2
+ vcmptrue_uqpd (%ecx),%ymm6,%ymm2
vcmpeq_ospd %ymm4,%ymm6,%ymm2
vcmpeq_ospd (%ecx),%ymm6,%ymm2
vcmplt_oqpd %ymm4,%ymm6,%ymm2
@@ -159,36 +187,64 @@ _start:
vcmptrue_uspd (%ecx),%ymm6,%ymm2
vcmpeqps %ymm4,%ymm6,%ymm2
vcmpeqps (%ecx),%ymm6,%ymm2
+ vcmpeq_oqps %ymm4,%ymm6,%ymm2
+ vcmpeq_oqps (%ecx),%ymm6,%ymm2
vcmpltps %ymm4,%ymm6,%ymm2
vcmpltps (%ecx),%ymm6,%ymm2
+ vcmplt_osps %ymm4,%ymm6,%ymm2
+ vcmplt_osps (%ecx),%ymm6,%ymm2
vcmpleps %ymm4,%ymm6,%ymm2
vcmpleps (%ecx),%ymm6,%ymm2
+ vcmple_osps %ymm4,%ymm6,%ymm2
+ vcmple_osps (%ecx),%ymm6,%ymm2
vcmpunordps %ymm4,%ymm6,%ymm2
vcmpunordps (%ecx),%ymm6,%ymm2
+ vcmpunord_qps %ymm4,%ymm6,%ymm2
+ vcmpunord_qps (%ecx),%ymm6,%ymm2
vcmpneqps %ymm4,%ymm6,%ymm2
vcmpneqps (%ecx),%ymm6,%ymm2
+ vcmpneq_uqps %ymm4,%ymm6,%ymm2
+ vcmpneq_uqps (%ecx),%ymm6,%ymm2
vcmpnltps %ymm4,%ymm6,%ymm2
vcmpnltps (%ecx),%ymm6,%ymm2
+ vcmpnlt_usps %ymm4,%ymm6,%ymm2
+ vcmpnlt_usps (%ecx),%ymm6,%ymm2
vcmpnleps %ymm4,%ymm6,%ymm2
vcmpnleps (%ecx),%ymm6,%ymm2
+ vcmpnle_usps %ymm4,%ymm6,%ymm2
+ vcmpnle_usps (%ecx),%ymm6,%ymm2
vcmpordps %ymm4,%ymm6,%ymm2
vcmpordps (%ecx),%ymm6,%ymm2
+ vcmpord_qps %ymm4,%ymm6,%ymm2
+ vcmpord_qps (%ecx),%ymm6,%ymm2
vcmpeq_uqps %ymm4,%ymm6,%ymm2
vcmpeq_uqps (%ecx),%ymm6,%ymm2
vcmpngeps %ymm4,%ymm6,%ymm2
vcmpngeps (%ecx),%ymm6,%ymm2
+ vcmpnge_usps %ymm4,%ymm6,%ymm2
+ vcmpnge_usps (%ecx),%ymm6,%ymm2
vcmpngtps %ymm4,%ymm6,%ymm2
vcmpngtps (%ecx),%ymm6,%ymm2
+ vcmpngt_usps %ymm4,%ymm6,%ymm2
+ vcmpngt_usps (%ecx),%ymm6,%ymm2
vcmpfalseps %ymm4,%ymm6,%ymm2
vcmpfalseps (%ecx),%ymm6,%ymm2
+ vcmpfalse_oqps %ymm4,%ymm6,%ymm2
+ vcmpfalse_oqps (%ecx),%ymm6,%ymm2
vcmpneq_oqps %ymm4,%ymm6,%ymm2
vcmpneq_oqps (%ecx),%ymm6,%ymm2
vcmpgeps %ymm4,%ymm6,%ymm2
vcmpgeps (%ecx),%ymm6,%ymm2
+ vcmpge_osps %ymm4,%ymm6,%ymm2
+ vcmpge_osps (%ecx),%ymm6,%ymm2
vcmpgtps %ymm4,%ymm6,%ymm2
vcmpgtps (%ecx),%ymm6,%ymm2
+ vcmpgt_osps %ymm4,%ymm6,%ymm2
+ vcmpgt_osps (%ecx),%ymm6,%ymm2
vcmptrueps %ymm4,%ymm6,%ymm2
vcmptrueps (%ecx),%ymm6,%ymm2
+ vcmptrue_uqps %ymm4,%ymm6,%ymm2
+ vcmptrue_uqps (%ecx),%ymm6,%ymm2
vcmpeq_osps %ymm4,%ymm6,%ymm2
vcmpeq_osps (%ecx),%ymm6,%ymm2
vcmplt_oqps %ymm4,%ymm6,%ymm2
@@ -977,36 +1033,64 @@ _start:
vsubsd (%ecx),%xmm6,%xmm2
vcmpeqsd %xmm4,%xmm6,%xmm2
vcmpeqsd (%ecx),%xmm6,%xmm2
+ vcmpeq_oqsd %xmm4,%xmm6,%xmm2
+ vcmpeq_oqsd (%ecx),%xmm6,%xmm2
vcmpltsd %xmm4,%xmm6,%xmm2
vcmpltsd (%ecx),%xmm6,%xmm2
+ vcmplt_ossd %xmm4,%xmm6,%xmm2
+ vcmplt_ossd (%ecx),%xmm6,%xmm2
vcmplesd %xmm4,%xmm6,%xmm2
vcmplesd (%ecx),%xmm6,%xmm2
+ vcmple_ossd %xmm4,%xmm6,%xmm2
+ vcmple_ossd (%ecx),%xmm6,%xmm2
vcmpunordsd %xmm4,%xmm6,%xmm2
vcmpunordsd (%ecx),%xmm6,%xmm2
+ vcmpunord_qsd %xmm4,%xmm6,%xmm2
+ vcmpunord_qsd (%ecx),%xmm6,%xmm2
vcmpneqsd %xmm4,%xmm6,%xmm2
vcmpneqsd (%ecx),%xmm6,%xmm2
+ vcmpneq_uqsd %xmm4,%xmm6,%xmm2
+ vcmpneq_uqsd (%ecx),%xmm6,%xmm2
vcmpnltsd %xmm4,%xmm6,%xmm2
vcmpnltsd (%ecx),%xmm6,%xmm2
+ vcmpnlt_ussd %xmm4,%xmm6,%xmm2
+ vcmpnlt_ussd (%ecx),%xmm6,%xmm2
vcmpnlesd %xmm4,%xmm6,%xmm2
vcmpnlesd (%ecx),%xmm6,%xmm2
+ vcmpnle_ussd %xmm4,%xmm6,%xmm2
+ vcmpnle_ussd (%ecx),%xmm6,%xmm2
vcmpordsd %xmm4,%xmm6,%xmm2
vcmpordsd (%ecx),%xmm6,%xmm2
+ vcmpord_qsd %xmm4,%xmm6,%xmm2
+ vcmpord_qsd (%ecx),%xmm6,%xmm2
vcmpeq_uqsd %xmm4,%xmm6,%xmm2
vcmpeq_uqsd (%ecx),%xmm6,%xmm2
vcmpngesd %xmm4,%xmm6,%xmm2
vcmpngesd (%ecx),%xmm6,%xmm2
+ vcmpnge_ussd %xmm4,%xmm6,%xmm2
+ vcmpnge_ussd (%ecx),%xmm6,%xmm2
vcmpngtsd %xmm4,%xmm6,%xmm2
vcmpngtsd (%ecx),%xmm6,%xmm2
+ vcmpngt_ussd %xmm4,%xmm6,%xmm2
+ vcmpngt_ussd (%ecx),%xmm6,%xmm2
vcmpfalsesd %xmm4,%xmm6,%xmm2
vcmpfalsesd (%ecx),%xmm6,%xmm2
+ vcmpfalse_oqsd %xmm4,%xmm6,%xmm2
+ vcmpfalse_oqsd (%ecx),%xmm6,%xmm2
vcmpneq_oqsd %xmm4,%xmm6,%xmm2
vcmpneq_oqsd (%ecx),%xmm6,%xmm2
vcmpgesd %xmm4,%xmm6,%xmm2
vcmpgesd (%ecx),%xmm6,%xmm2
+ vcmpge_ossd %xmm4,%xmm6,%xmm2
+ vcmpge_ossd (%ecx),%xmm6,%xmm2
vcmpgtsd %xmm4,%xmm6,%xmm2
vcmpgtsd (%ecx),%xmm6,%xmm2
+ vcmpgt_ossd %xmm4,%xmm6,%xmm2
+ vcmpgt_ossd (%ecx),%xmm6,%xmm2
vcmptruesd %xmm4,%xmm6,%xmm2
vcmptruesd (%ecx),%xmm6,%xmm2
+ vcmptrue_uqsd %xmm4,%xmm6,%xmm2
+ vcmptrue_uqsd (%ecx),%xmm6,%xmm2
vcmpeq_ossd %xmm4,%xmm6,%xmm2
vcmpeq_ossd (%ecx),%xmm6,%xmm2
vcmplt_oqsd %xmm4,%xmm6,%xmm2
@@ -1067,36 +1151,64 @@ _start:
vsubss (%ecx),%xmm6,%xmm2
vcmpeqss %xmm4,%xmm6,%xmm2
vcmpeqss (%ecx),%xmm6,%xmm2
+ vcmpeq_oqss %xmm4,%xmm6,%xmm2
+ vcmpeq_oqss (%ecx),%xmm6,%xmm2
vcmpltss %xmm4,%xmm6,%xmm2
vcmpltss (%ecx),%xmm6,%xmm2
+ vcmplt_osss %xmm4,%xmm6,%xmm2
+ vcmplt_osss (%ecx),%xmm6,%xmm2
vcmpless %xmm4,%xmm6,%xmm2
vcmpless (%ecx),%xmm6,%xmm2
+ vcmple_osss %xmm4,%xmm6,%xmm2
+ vcmple_osss (%ecx),%xmm6,%xmm2
vcmpunordss %xmm4,%xmm6,%xmm2
vcmpunordss (%ecx),%xmm6,%xmm2
+ vcmpunord_qss %xmm4,%xmm6,%xmm2
+ vcmpunord_qss (%ecx),%xmm6,%xmm2
vcmpneqss %xmm4,%xmm6,%xmm2
vcmpneqss (%ecx),%xmm6,%xmm2
+ vcmpneq_uqss %xmm4,%xmm6,%xmm2
+ vcmpneq_uqss (%ecx),%xmm6,%xmm2
vcmpnltss %xmm4,%xmm6,%xmm2
vcmpnltss (%ecx),%xmm6,%xmm2
+ vcmpnlt_usss %xmm4,%xmm6,%xmm2
+ vcmpnlt_usss (%ecx),%xmm6,%xmm2
vcmpnless %xmm4,%xmm6,%xmm2
vcmpnless (%ecx),%xmm6,%xmm2
+ vcmpnle_usss %xmm4,%xmm6,%xmm2
+ vcmpnle_usss (%ecx),%xmm6,%xmm2
vcmpordss %xmm4,%xmm6,%xmm2
vcmpordss (%ecx),%xmm6,%xmm2
+ vcmpord_qss %xmm4,%xmm6,%xmm2
+ vcmpord_qss (%ecx),%xmm6,%xmm2
vcmpeq_uqss %xmm4,%xmm6,%xmm2
vcmpeq_uqss (%ecx),%xmm6,%xmm2
vcmpngess %xmm4,%xmm6,%xmm2
vcmpngess (%ecx),%xmm6,%xmm2
+ vcmpnge_usss %xmm4,%xmm6,%xmm2
+ vcmpnge_usss (%ecx),%xmm6,%xmm2
vcmpngtss %xmm4,%xmm6,%xmm2
vcmpngtss (%ecx),%xmm6,%xmm2
+ vcmpngt_usss %xmm4,%xmm6,%xmm2
+ vcmpngt_usss (%ecx),%xmm6,%xmm2
vcmpfalsess %xmm4,%xmm6,%xmm2
vcmpfalsess (%ecx),%xmm6,%xmm2
+ vcmpfalse_oqss %xmm4,%xmm6,%xmm2
+ vcmpfalse_oqss (%ecx),%xmm6,%xmm2
vcmpneq_oqss %xmm4,%xmm6,%xmm2
vcmpneq_oqss (%ecx),%xmm6,%xmm2
vcmpgess %xmm4,%xmm6,%xmm2
vcmpgess (%ecx),%xmm6,%xmm2
+ vcmpge_osss %xmm4,%xmm6,%xmm2
+ vcmpge_osss (%ecx),%xmm6,%xmm2
vcmpgtss %xmm4,%xmm6,%xmm2
vcmpgtss (%ecx),%xmm6,%xmm2
+ vcmpgt_osss %xmm4,%xmm6,%xmm2
+ vcmpgt_osss (%ecx),%xmm6,%xmm2
vcmptruess %xmm4,%xmm6,%xmm2
vcmptruess (%ecx),%xmm6,%xmm2
+ vcmptrue_uqss %xmm4,%xmm6,%xmm2
+ vcmptrue_uqss (%ecx),%xmm6,%xmm2
vcmpeq_osss %xmm4,%xmm6,%xmm2
vcmpeq_osss (%ecx),%xmm6,%xmm2
vcmplt_oqss %xmm4,%xmm6,%xmm2
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index ad310587975..e7e7d866e9e 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@
+2020-03-09 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
+ vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
+ * i386-tbl.h: Re-generate.
+
2020-03-09 Jan Beulich <jbeulich@suse.com>
* i386-gen.c (set_bitfield): Ignore zero-length field names.
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 5213c80ad10..d8e997fe79a 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -1727,6 +1727,16 @@ gf2p8mulb, 2, 0x660f38cf, None, 3, CpuGFNI, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSu
// AVX instructions.
+<avx_frel:imm:comm, eq:00:C, eq_oq:00:C, lt:01:, lt_os:01:, le:02:, le_os:02:, \
+ unord:03:C, unord_q:03:C, neq:04:C, neq_uq:04:C, nlt:05:, nlt_us:05:, \
+ nle:06:, nle_us:06:, ord:07:C, ord_q:07:C, eq_uq:08:C, \
+ nge:09:, nge_us:09:, ngt:0a:, ngt_us:0a:, false:0b:C, false_oq:0b:C, \
+ neq_oq:0c:C, ge:0d:, ge_os:0d:, gt:0e:, gt_os:0e:, true:0f:C, \
+ true_uq:0f:C, eq_os:10:C, lt_oq:11:, le_oq:12:, \
+ unord_s:13:C, neq_us:14:C, nlt_uq:15:, nle_uq:16:, ord_s:17:C, eq_us:18:C, \
+ nge_uq:19:, ngt_uq:1a:, false_os:1b:C, neq_os:1c:C, ge_oq:1d:, gt_oq:1e:, \
+ true_us:1f:C>
+
vaddpd, 3, 0x6658, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vaddps, 3, 0x58, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vaddsd, 3, 0xf258, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
@@ -1744,138 +1754,14 @@ vblendvps, 4, 0x664a, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexVVVV=1|VexW=1|Ve
vbroadcastf128, 2, 0x661a, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex, RegYMM }
vbroadcastsd, 2, 0x6619, None, 1, CpuAVX, Modrm|Vex=2|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegYMM }
vbroadcastss, 2, 0x6618, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegXMM|RegYMM }
-vcmpeq_ospd, 3, 0x66c2, 0x10, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vcmpeq_osps, 3, 0xc2, 0x10, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vcmpeq_ossd, 3, 0xf2c2, 0x10, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vcmpeq_osss, 3, 0xf3c2, 0x10, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vcmpeqpd, 3, 0x66c2, 0x0, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vcmpeqps, 3, 0xc2, 0x0, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vcmpeqsd, 3, 0xf2c2, 0x0, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vcmpeqss, 3, 0xf3c2, 0x0, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vcmpeq_uqpd, 3, 0x66c2, 0x8, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vcmpeq_uqps, 3, 0xc2, 0x8, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vcmpeq_uqsd, 3, 0xf2c2, 0x8, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vcmpeq_uqss, 3, 0xf3c2, 0x8, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vcmpeq_uspd, 3, 0x66c2, 0x18, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vcmpeq_usps, 3, 0xc2, 0x18, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vcmpeq_ussd, 3, 0xf2c2, 0x18, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vcmpeq_usss, 3, 0xf3c2, 0x18, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vcmpfalse_ospd, 3, 0x66c2, 0x1b, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vcmpfalse_osps, 3, 0xc2, 0x1b, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vcmpfalse_ossd, 3, 0xf2c2, 0x1b, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vcmpfalse_osss, 3, 0xf3c2, 0x1b, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vcmpfalsepd, 3, 0x66c2, 0xb, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vcmpfalseps, 3, 0xc2, 0xb, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vcmpfalsesd, 3, 0xf2c2, 0xb, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vcmpfalsess, 3, 0xf3c2, 0xb, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vcmpge_oqpd, 3, 0x66c2, 0x1d, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vcmpge_oqps, 3, 0xc2, 0x1d, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vcmpge_oqsd, 3, 0xf2c2, 0x1d, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vcmpge_oqss, 3, 0xf3c2, 0x1d, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vcmpgepd, 3, 0x66c2, 0xd, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vcmpgeps, 3, 0xc2, 0xd, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vcmpgesd, 3, 0xf2c2, 0xd, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vcmpgess, 3, 0xf3c2, 0xd, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vcmpgt_oqpd, 3, 0x66c2, 0x1e, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vcmpgt_oqps, 3, 0xc2, 0x1e, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vcmpgt_oqsd, 3, 0xf2c2, 0x1e, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vcmpgt_oqss, 3, 0xf3c2, 0x1e, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vcmpgtpd, 3, 0x66c2, 0xe, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vcmpgtps, 3, 0xc2, 0xe, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vcmpgtsd, 3, 0xf2c2, 0xe, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vcmpgtss, 3, 0xf3c2, 0xe, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vcmple_oqpd, 3, 0x66c2, 0x12, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vcmple_oqps, 3, 0xc2, 0x12, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vcmple_oqsd, 3, 0xf2c2, 0x12, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vcmple_oqss, 3, 0xf3c2, 0x12, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vcmplepd, 3, 0x66c2, 0x2, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vcmpleps, 3, 0xc2, 0x2, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vcmplesd, 3, 0xf2c2, 0x2, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vcmpless, 3, 0xf3c2, 0x2, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vcmplt_oqpd, 3, 0x66c2, 0x11, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vcmplt_oqps, 3, 0xc2, 0x11, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vcmplt_oqsd, 3, 0xf2c2, 0x11, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vcmplt_oqss, 3, 0xf3c2, 0x11, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vcmpltpd, 3, 0x66c2, 0x1, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vcmpltps, 3, 0xc2, 0x1, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vcmpltsd, 3, 0xf2c2, 0x1, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vcmpltss, 3, 0xf3c2, 0x1, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vcmpneq_oqpd, 3, 0x66c2, 0xc, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vcmpneq_oqps, 3, 0xc2, 0xc, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vcmpneq_oqsd, 3, 0xf2c2, 0xc, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vcmpneq_oqss, 3, 0xf3c2, 0xc, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vcmpneq_ospd, 3, 0x66c2, 0x1c, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vcmpneq_osps, 3, 0xc2, 0x1c, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vcmpneq_ossd, 3, 0xf2c2, 0x1c, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vcmpneq_osss, 3, 0xf3c2, 0x1c, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vcmpneqpd, 3, 0x66c2, 0x4, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vcmpneqps, 3, 0xc2, 0x4, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vcmpneqsd, 3, 0xf2c2, 0x4, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vcmpneqss, 3, 0xf3c2, 0x4, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vcmpneq_uspd, 3, 0x66c2, 0x14, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vcmpneq_usps, 3, 0xc2, 0x14, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vcmpneq_ussd, 3, 0xf2c2, 0x14, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vcmpneq_usss, 3, 0xf3c2, 0x14, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vcmpngepd, 3, 0x66c2, 0x9, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vcmpngeps, 3, 0xc2, 0x9, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vcmpngesd, 3, 0xf2c2, 0x9, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vcmpngess, 3, 0xf3c2, 0x9, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vcmpnge_uqpd, 3, 0x66c2, 0x19, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vcmpnge_uqps, 3, 0xc2, 0x19, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vcmpnge_uqsd, 3, 0xf2c2, 0x19, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vcmpnge_uqss, 3, 0xf3c2, 0x19, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vcmpngtpd, 3, 0x66c2, 0xa, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vcmpngtps, 3, 0xc2, 0xa, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vcmpngtsd, 3, 0xf2c2, 0xa, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vcmpngtss, 3, 0xf3c2, 0xa, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vcmpngt_uqpd, 3, 0x66c2, 0x1a, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vcmpngt_uqps, 3, 0xc2, 0x1a, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vcmpngt_uqsd, 3, 0xf2c2, 0x1a, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vcmpngt_uqss, 3, 0xf3c2, 0x1a, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vcmpnlepd, 3, 0x66c2, 0x6, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vcmpnleps, 3, 0xc2, 0x6, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vcmpnlesd, 3, 0xf2c2, 0x6, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vcmpnless, 3, 0xf3c2, 0x6, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vcmpnle_uqpd, 3, 0x66c2, 0x16, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vcmpnle_uqps, 3, 0xc2, 0x16, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vcmpnle_uqsd, 3, 0xf2c2, 0x16, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vcmpnle_uqss, 3, 0xf3c2, 0x16, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vcmpnltpd, 3, 0x66c2, 0x5, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vcmpnltps, 3, 0xc2, 0x5, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vcmpnltsd, 3, 0xf2c2, 0x5, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vcmpnltss, 3, 0xf3c2, 0x5, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vcmpnlt_uqpd, 3, 0x66c2, 0x15, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vcmpnlt_uqps, 3, 0xc2, 0x15, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vcmpnlt_uqsd, 3, 0xf2c2, 0x15, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vcmpnlt_uqss, 3, 0xf3c2, 0x15, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vcmpordpd, 3, 0x66c2, 0x7, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vcmpordps, 3, 0xc2, 0x7, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vcmpordsd, 3, 0xf2c2, 0x7, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vcmpordss, 3, 0xf3c2, 0x7, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vcmpord_spd, 3, 0x66c2, 0x17, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vcmpord_sps, 3, 0xc2, 0x17, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vcmpord_ssd, 3, 0xf2c2, 0x17, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vcmpord_sss, 3, 0xf3c2, 0x17, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
+vcmp<avx_frel>pd, 3, 0x66c2, 0x<avx_frel:imm>, 1, CpuAVX, Modrm|<avx_frel:comm>|Vex|VexOpcode=0|VexVVVV|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
+vcmp<avx_frel>ps, 3, 0xc2, 0x<avx_frel:imm>, 1, CpuAVX, Modrm|<avx_frel:comm>|Vex|VexOpcode=0|VexVVVV|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
+vcmp<avx_frel>sd, 3, 0xf2c2, 0x<avx_frel:imm>, 1, CpuAVX, Modrm|<avx_frel:comm>|VexLIG|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
+vcmp<avx_frel>ss, 3, 0xf3c2, 0x<avx_frel:imm>, 1, CpuAVX, Modrm|<avx_frel:comm>|VexLIG|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
vcmppd, 4, 0x66c2, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpps, 4, 0xc2, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
vcmpsd, 4, 0xf2c2, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcmpss, 4, 0xf3c2, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vcmptruepd, 3, 0x66c2, 0xf, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vcmptrueps, 3, 0xc2, 0xf, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vcmptruesd, 3, 0xf2c2, 0xf, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vcmptruess, 3, 0xf3c2, 0xf, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vcmptrue_uspd, 3, 0x66c2, 0x1f, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vcmptrue_usps, 3, 0xc2, 0x1f, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vcmptrue_ussd, 3, 0xf2c2, 0x1f, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vcmptrue_usss, 3, 0xf3c2, 0x1f, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vcmpunordpd, 3, 0x66c2, 0x3, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vcmpunordps, 3, 0xc2, 0x3, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vcmpunordsd, 3, 0xf2c2, 0x3, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vcmpunordss, 3, 0xf3c2, 0x3, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vcmpunord_spd, 3, 0x66c2, 0x13, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vcmpunord_sps, 3, 0xc2, 0x13, 1, CpuAVX, Modrm|C|Vex|VexOpcode=0|VexVVVV=1|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
-vcmpunord_ssd, 3, 0xf2c2, 0x13, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
-vcmpunord_sss, 3, 0xf3c2, 0x13, 1, CpuAVX, Modrm|C|Vex=3|VexOpcode=0|VexVVVV|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
vcomisd, 2, 0x662f, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM }
vcomiss, 2, 0x2f, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM }
vcvtdq2pd, 2, 0xf3e6, None, 1, CpuAVX, Modrm|Vex128|VexOpcode=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM }
@@ -2898,385 +2784,25 @@ vbroadcastsd, 2, 0x6619, None, 1, CpuAVX512F, Modrm|Masking=3|VexOpcode=1|VexW1|
vpbroadcastd, 2, 0x6658, None, 1, CpuAVX512F, Modrm|Masking=3|VexOpcode=1|VexW0|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
vpbroadcastd, 2, 0x667C, None, 1, CpuAVX512F, Modrm|Masking=3|VexOpcode=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, RegXMM|RegYMM|RegZMM }
+vcmp<avx_frel>pd, 3, 0x66C2, 0x<avx_frel:imm>, 1, CpuAVX512F, Modrm|Masking=2|VexOpcode=0|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
+vcmp<avx_frel>pd, 4, 0x66C2, 0x<avx_frel:imm>, 1, CpuAVX512F, Modrm|EVex512|Masking=2|VexOpcode=0|VexVVVV|VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, { Imm8, RegZMM, RegZMM, RegMask }
vcmppd, 4, 0x66C2, None, 1, CpuAVX512F, Modrm|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
vcmppd, 5, 0x66C2, None, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, Imm8, RegZMM, RegZMM, RegMask }
-vcmpeqpd, 3, 0x66C2, 0, 1, CpuAVX512F, Modrm|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
-vcmpeqpd, 4, 0x66C2, 0, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, { Imm8, RegZMM, RegZMM, RegMask }
-vcmpeq_oqpd, 3, 0x66C2, 0, 1, CpuAVX512F, Modrm|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
-vcmpeq_oqpd, 4, 0x66C2, 0, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, { Imm8, RegZMM, RegZMM, RegMask }
-vcmpeq_ospd, 3, 0x66C2, 16, 1, CpuAVX512F, Modrm|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
-vcmpeq_ospd, 4, 0x66C2, 16, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, { Imm8, RegZMM, RegZMM, RegMask }
-vcmpeq_uqpd, 3, 0x66C2, 8, 1, CpuAVX512F, Modrm|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
-vcmpeq_uqpd, 4, 0x66C2, 8, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, { Imm8, RegZMM, RegZMM, RegMask }
-vcmpeq_uspd, 3, 0x66C2, 24, 1, CpuAVX512F, Modrm|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
-vcmpeq_uspd, 4, 0x66C2, 24, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, { Imm8, RegZMM, RegZMM, RegMask }
-vcmpfalsepd, 3, 0x66C2, 11, 1, CpuAVX512F, Modrm|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
-vcmpfalsepd, 4, 0x66C2, 11, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, { Imm8, RegZMM, RegZMM, RegMask }
-vcmpfalse_oqpd, 3, 0x66C2, 11, 1, CpuAVX512F, Modrm|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
-vcmpfalse_oqpd, 4, 0x66C2, 11, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, { Imm8, RegZMM, RegZMM, RegMask }
-vcmpfalse_ospd, 3, 0x66C2, 27, 1, CpuAVX512F, Modrm|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
-vcmpfalse_ospd, 4, 0x66C2, 27, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, { Imm8, RegZMM, RegZMM, RegMask }
-vcmpgepd, 3, 0x66C2, 13, 1, CpuAVX512F, Modrm|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
-vcmpgepd, 4, 0x66C2, 13, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, { Imm8, RegZMM, RegZMM, RegMask }
-vcmpge_oqpd, 3, 0x66C2, 29, 1, CpuAVX512F, Modrm|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
-vcmpge_oqpd, 4, 0x66C2, 29, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, { Imm8, RegZMM, RegZMM, RegMask }
-vcmpge_ospd, 3, 0x66C2, 13, 1, CpuAVX512F, Modrm|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask }
-vcmpge_ospd, 4, 0x66C2, 13, 1, CpuAVX512F, Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_q[...]
[diff truncated at 100000 bytes]
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