[binutils-gdb] RISC-V: Don't generate the ELF privilege attributes when no CSR are used.
Nelson Chu
nelsonc1225@sourceware.org
Fri Jun 5 04:22:31 GMT 2020
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=3fc6c3dc2af2283bd89f1b1278b39922416e8d1b
commit 3fc6c3dc2af2283bd89f1b1278b39922416e8d1b
Author: Nelson Chu <nelson.chu@sifive.com>
Date: Fri May 29 15:31:46 2020 +0800
RISC-V: Don't generate the ELF privilege attributes when no CSR are used.
gas/
* config/tc-riscv.c (explicit_csr): New static boolean.
Used to indicate CSR are explictly used.
(riscv_ip): Set explicit_csr to TRUE if any CSR is used.
(riscv_write_out_attrs): If we already have set elf priv
attributes, then generate them. Otherwise, don't generate
them when no CSR are used.
* testsuite/gas/riscv/attribute-01.d: Remove the priv attributes.
* testsuite/gas/riscv/attribute-02.d: Likewise.
* testsuite/gas/riscv/attribute-03.d: Likewise.
* testsuite/gas/riscv/attribute-04.d: Likewise.
* testsuite/gas/riscv/attribute-05.d: Likewise.
* testsuite/gas/riscv/attribute-06.d: Likewise.
* testsuite/gas/riscv/attribute-07.d: Likewise.
* testsuite/gas/riscv/attribute-08.d: Likewise.
* testsuite/gas/riscv/attribute-09.d: Likewise.
* testsuite/gas/riscv/attribute-10.d: Likewise.
* testsuite/gas/riscv/attribute-unknown.d: Likewise.
* testsuite/gas/riscv/attribute-11.s: New testcase.
* testsuite/gas/riscv/attribute-11.d: New testcase. The CSR is
used, so we should output the ELF priv attributes.
* testsuite/gas/riscv/attribute-12.d: New testcase. The CSR is
used, so output the priv attributes according to the -mpriv-spec.
* testsuite/gas/riscv/attribute-13.d: New testcase. The CSR isn't
used, so ignore the -mpriv-spec setting.
ld/
* testsuite/ld-riscv-elf/attr-merge-arch-01.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-stack-align.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-01.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-02.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-03.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-04.d: Likewise.
* testsuite/ld-riscv-elf/attr-merge-strict-align-05.d: Likewise.
* testsuite/ld-riscv-elf/call-relax.d: Add -mno-arch-attr.
Diff:
---
gas/ChangeLog | 27 ++++++++++++++++++++++
gas/config/tc-riscv.c | 9 ++++++++
gas/testsuite/gas/riscv/attribute-01.d | 3 ---
gas/testsuite/gas/riscv/attribute-02.d | 3 ---
gas/testsuite/gas/riscv/attribute-03.d | 3 ---
gas/testsuite/gas/riscv/attribute-04.d | 3 ---
gas/testsuite/gas/riscv/attribute-06.d | 3 ---
gas/testsuite/gas/riscv/attribute-07.d | 3 ---
gas/testsuite/gas/riscv/attribute-08.d | 3 ---
gas/testsuite/gas/riscv/attribute-09.d | 3 ---
gas/testsuite/gas/riscv/attribute-10.d | 3 ---
gas/testsuite/gas/riscv/attribute-11.d | 8 +++++++
gas/testsuite/gas/riscv/attribute-11.s | 1 +
gas/testsuite/gas/riscv/attribute-12.d | 9 ++++++++
gas/testsuite/gas/riscv/attribute-13.d | 6 +++++
gas/testsuite/gas/riscv/attribute-unknown.d | 3 ---
ld/ChangeLog | 14 +++++++++++
ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d | 3 ---
ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d | 3 ---
ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d | 3 ---
ld/testsuite/ld-riscv-elf/attr-merge-stack-align.d | 2 --
.../ld-riscv-elf/attr-merge-strict-align-01.d | 3 ---
.../ld-riscv-elf/attr-merge-strict-align-02.d | 3 ---
.../ld-riscv-elf/attr-merge-strict-align-03.d | 3 ---
.../ld-riscv-elf/attr-merge-strict-align-04.d | 3 ---
.../ld-riscv-elf/attr-merge-strict-align-05.d | 3 ---
ld/testsuite/ld-riscv-elf/call-relax.d | 2 +-
27 files changed, 75 insertions(+), 57 deletions(-)
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 19cefba5e62..14d10799f0b 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,30 @@
+2020-06-05 Nelson Chu <nelson.chu@sifive.com>
+
+ * config/tc-riscv.c (explicit_csr): New static boolean.
+ Used to indicate CSR are explictly used.
+ (riscv_ip): Set explicit_csr to TRUE if any CSR is used.
+ (riscv_write_out_attrs): If we already have set elf priv
+ attributes, then generate them. Otherwise, don't generate
+ them when no CSR are used.
+ * testsuite/gas/riscv/attribute-01.d: Remove the priv attributes.
+ * testsuite/gas/riscv/attribute-02.d: Likewise.
+ * testsuite/gas/riscv/attribute-03.d: Likewise.
+ * testsuite/gas/riscv/attribute-04.d: Likewise.
+ * testsuite/gas/riscv/attribute-05.d: Likewise.
+ * testsuite/gas/riscv/attribute-06.d: Likewise.
+ * testsuite/gas/riscv/attribute-07.d: Likewise.
+ * testsuite/gas/riscv/attribute-08.d: Likewise.
+ * testsuite/gas/riscv/attribute-09.d: Likewise.
+ * testsuite/gas/riscv/attribute-10.d: Likewise.
+ * testsuite/gas/riscv/attribute-unknown.d: Likewise.
+ * testsuite/gas/riscv/attribute-11.s: New testcase.
+ * testsuite/gas/riscv/attribute-11.d: New testcase. The CSR is
+ used, so we should output the ELF priv attributes.
+ * testsuite/gas/riscv/attribute-12.d: New testcase. The CSR is
+ used, so output the priv attributes according to the -mpriv-spec.
+ * testsuite/gas/riscv/attribute-13.d: New testcase. The CSR isn't
+ used, so ignore the -mpriv-spec setting.
+
2020-06-04 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-ip2k. (ip2k_apply_fix): Pass endianness to
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index da94b5b1cfb..cc77dbf6c00 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -374,6 +374,9 @@ static bfd_boolean start_assemble = FALSE;
/* Indicate ELF attributes are explictly set. */
static bfd_boolean explicit_attr = FALSE;
+/* Indicate CSR are explictly used. */
+static bfd_boolean explicit_csr = FALSE;
+
/* Macros for encoding relaxation state for RVC branches and far jumps. */
#define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
((relax_substateT) \
@@ -2212,6 +2215,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
case 'E': /* Control register. */
insn_with_csr = TRUE;
+ explicit_csr = TRUE;
if (reg_lookup (&s, RCLASS_CSR, ®no))
INSERT_OPERAND (CSR, *ip, regno);
else
@@ -3605,6 +3609,11 @@ riscv_write_out_attrs (void)
&& !riscv_set_default_priv_spec (NULL))
return;
+ /* If we already have set elf priv attributes, then generate them.
+ Otherwise, don't generate them when no CSR are used. */
+ if (!explicit_csr)
+ return;
+
/* Re-write priv attributes by default_priv_spec. */
priv_str = riscv_get_priv_spec_name (default_priv_spec);
p = priv_str;
diff --git a/gas/testsuite/gas/riscv/attribute-01.d b/gas/testsuite/gas/riscv/attribute-01.d
index f02734744e1..2e19e09abf2 100644
--- a/gas/testsuite/gas/riscv/attribute-01.d
+++ b/gas/testsuite/gas/riscv/attribute-01.d
@@ -4,6 +4,3 @@
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0"
- Tag_RISCV_priv_spec: [0-9_\"].*
- Tag_RISCV_priv_spec_minor: [0-9_\"].*
-#...
diff --git a/gas/testsuite/gas/riscv/attribute-02.d b/gas/testsuite/gas/riscv/attribute-02.d
index 02b532d0a88..ae0195e9a2c 100644
--- a/gas/testsuite/gas/riscv/attribute-02.d
+++ b/gas/testsuite/gas/riscv/attribute-02.d
@@ -4,6 +4,3 @@
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_xargle0p0"
- Tag_RISCV_priv_spec: [0-9_\"].*
- Tag_RISCV_priv_spec_minor: [0-9_\"].*
-#...
diff --git a/gas/testsuite/gas/riscv/attribute-03.d b/gas/testsuite/gas/riscv/attribute-03.d
index ded529aa617..9916ff6e927 100644
--- a/gas/testsuite/gas/riscv/attribute-03.d
+++ b/gas/testsuite/gas/riscv/attribute-03.d
@@ -4,6 +4,3 @@
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0_xargle0p0_xfoo0p0"
- Tag_RISCV_priv_spec: [0-9_\"].*
- Tag_RISCV_priv_spec_minor: [0-9_\"].*
-#...
diff --git a/gas/testsuite/gas/riscv/attribute-04.d b/gas/testsuite/gas/riscv/attribute-04.d
index df6c8182d5b..408464d01ce 100644
--- a/gas/testsuite/gas/riscv/attribute-04.d
+++ b/gas/testsuite/gas/riscv/attribute-04.d
@@ -4,6 +4,3 @@
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0_f2p0_d2p0"
- Tag_RISCV_priv_spec: [0-9_\"].*
- Tag_RISCV_priv_spec_minor: [0-9_\"].*
-#...
diff --git a/gas/testsuite/gas/riscv/attribute-06.d b/gas/testsuite/gas/riscv/attribute-06.d
index e1d62c45db7..a2dd9fbb97e 100644
--- a/gas/testsuite/gas/riscv/attribute-06.d
+++ b/gas/testsuite/gas/riscv/attribute-06.d
@@ -4,6 +4,3 @@
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv32i2p0"
- Tag_RISCV_priv_spec: [0-9_\"].*
- Tag_RISCV_priv_spec_minor: [0-9_\"].*
-#...
diff --git a/gas/testsuite/gas/riscv/attribute-07.d b/gas/testsuite/gas/riscv/attribute-07.d
index 59f02b4c4e3..342a53752ce 100644
--- a/gas/testsuite/gas/riscv/attribute-07.d
+++ b/gas/testsuite/gas/riscv/attribute-07.d
@@ -4,6 +4,3 @@
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv64i2p0"
- Tag_RISCV_priv_spec: [0-9_\"].*
- Tag_RISCV_priv_spec_minor: [0-9_\"].*
-#...
diff --git a/gas/testsuite/gas/riscv/attribute-08.d b/gas/testsuite/gas/riscv/attribute-08.d
index 13b82a97a63..c10ac0ca353 100644
--- a/gas/testsuite/gas/riscv/attribute-08.d
+++ b/gas/testsuite/gas/riscv/attribute-08.d
@@ -4,6 +4,3 @@
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv32e1p9"
- Tag_RISCV_priv_spec: [0-9_\"].*
- Tag_RISCV_priv_spec_minor: [0-9_\"].*
-#...
diff --git a/gas/testsuite/gas/riscv/attribute-09.d b/gas/testsuite/gas/riscv/attribute-09.d
index 53945a27ebc..cad1713b0a0 100644
--- a/gas/testsuite/gas/riscv/attribute-09.d
+++ b/gas/testsuite/gas/riscv/attribute-09.d
@@ -4,6 +4,3 @@
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv32i2p1_m2p0_zicsr0p0"
- Tag_RISCV_priv_spec: [0-9_\"].*
- Tag_RISCV_priv_spec_minor: [0-9_\"].*
-#...
diff --git a/gas/testsuite/gas/riscv/attribute-10.d b/gas/testsuite/gas/riscv/attribute-10.d
index 91691fda77a..ba903d17275 100644
--- a/gas/testsuite/gas/riscv/attribute-10.d
+++ b/gas/testsuite/gas/riscv/attribute-10.d
@@ -4,6 +4,3 @@
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0"
- Tag_RISCV_priv_spec: [0-9_\"].*
- Tag_RISCV_priv_spec_minor: [0-9_\"].*
-#...
diff --git a/gas/testsuite/gas/riscv/attribute-11.d b/gas/testsuite/gas/riscv/attribute-11.d
new file mode 100644
index 00000000000..4bd66f0bb29
--- /dev/null
+++ b/gas/testsuite/gas/riscv/attribute-11.d
@@ -0,0 +1,8 @@
+#as: -march-attr
+#readelf: -A
+#source: attribute-11.s
+Attribute Section: riscv
+File Attributes
+ Tag_RISCV_arch: [a-zA-Z0-9_\"].*
+ Tag_RISCV_priv_spec: [0-9_\"].*
+#...
diff --git a/gas/testsuite/gas/riscv/attribute-11.s b/gas/testsuite/gas/riscv/attribute-11.s
new file mode 100644
index 00000000000..81099b27ca1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/attribute-11.s
@@ -0,0 +1 @@
+ csrr a0, 0x0
diff --git a/gas/testsuite/gas/riscv/attribute-12.d b/gas/testsuite/gas/riscv/attribute-12.d
new file mode 100644
index 00000000000..980b36cada6
--- /dev/null
+++ b/gas/testsuite/gas/riscv/attribute-12.d
@@ -0,0 +1,9 @@
+#as: -march-attr -mpriv-spec=1.9.1
+#readelf: -A
+#source: attribute-11.s
+Attribute Section: riscv
+File Attributes
+ Tag_RISCV_arch: [a-zA-Z0-9_\"].*
+ Tag_RISCV_priv_spec: 1
+ Tag_RISCV_priv_spec_minor: 9
+ Tag_RISCV_priv_spec_revision: 1
diff --git a/gas/testsuite/gas/riscv/attribute-13.d b/gas/testsuite/gas/riscv/attribute-13.d
new file mode 100644
index 00000000000..b8dfe3a7dee
--- /dev/null
+++ b/gas/testsuite/gas/riscv/attribute-13.d
@@ -0,0 +1,6 @@
+#as: -march-attr -mpriv-spec=1.9.1
+#readelf: -A
+#source: empty.s
+Attribute Section: riscv
+File Attributes
+ Tag_RISCV_arch: [a-zA-Z0-9_\"].*
diff --git a/gas/testsuite/gas/riscv/attribute-unknown.d b/gas/testsuite/gas/riscv/attribute-unknown.d
index 120e3dee6ca..667f21acfc1 100644
--- a/gas/testsuite/gas/riscv/attribute-unknown.d
+++ b/gas/testsuite/gas/riscv/attribute-unknown.d
@@ -4,8 +4,5 @@
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: [a-zA-Z0-9_\"].*
- Tag_RISCV_priv_spec: [0-9_\"].*
- Tag_RISCV_priv_spec_minor: [0-9_\"].*
-#...
Tag_unknown_255: "test"
Tag_unknown_256: 123 \(0x7b\)
diff --git a/ld/ChangeLog b/ld/ChangeLog
index 00066c59c07..5b6805a31bc 100644
--- a/ld/ChangeLog
+++ b/ld/ChangeLog
@@ -1,3 +1,17 @@
+2020-06-05 Nelson Chu <nelson.chu@sifive.com>
+
+ * testsuite/ld-riscv-elf/attr-merge-arch-01.d: The CSR isn't used,
+ so ignore the -mpriv-spec setting.
+ * testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise.
+ * testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise.
+ * testsuite/ld-riscv-elf/attr-merge-stack-align.d: Likewise.
+ * testsuite/ld-riscv-elf/attr-merge-strict-align-01.d: Likewise.
+ * testsuite/ld-riscv-elf/attr-merge-strict-align-02.d: Likewise.
+ * testsuite/ld-riscv-elf/attr-merge-strict-align-03.d: Likewise.
+ * testsuite/ld-riscv-elf/attr-merge-strict-align-04.d: Likewise.
+ * testsuite/ld-riscv-elf/attr-merge-strict-align-05.d: Likewise.
+ * testsuite/ld-riscv-elf/call-relax.d: Add -mno-arch-attr.
+
2020-06-04 H.J. Lu <hongjiu.lu@intel.com>
PR ld/26080
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d
index 032f9641ad2..5baaba4c16f 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d
@@ -7,6 +7,3 @@
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv32i2p0_m2p0"
- Tag_RISCV_priv_spec: [0-9_\"].*
- Tag_RISCV_priv_spec_minor: [0-9_\"].*
-#...
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d
index 54a7621f2c3..a7d79a1ea2b 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d
@@ -7,6 +7,3 @@
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv32i2p0_m2p0"
- Tag_RISCV_priv_spec: [0-9_\"].*
- Tag_RISCV_priv_spec_minor: [0-9_\"].*
-#...
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d
index 67f0437e328..d46dee808de 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d
@@ -7,6 +7,3 @@
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: "rv32i2p0_m2p0_xbar2p0_xfoo2p0"
- Tag_RISCV_priv_spec: [0-9_\"].*
- Tag_RISCV_priv_spec_minor: [0-9_\"].*
-#...
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-stack-align.d b/ld/testsuite/ld-riscv-elf/attr-merge-stack-align.d
index 5585fac3b7b..e4d965a3e99 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-stack-align.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-stack-align.d
@@ -8,6 +8,4 @@ Attribute Section: riscv
File Attributes
Tag_RISCV_stack_align: 16-bytes
Tag_RISCV_arch: [a-zA-Z0-9_\"].*
- Tag_RISCV_priv_spec: [0-9_\"].*
- Tag_RISCV_priv_spec_minor: [0-9_\"].*
#...
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-01.d b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-01.d
index 91011a2ba4d..10399307bbb 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-01.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-01.d
@@ -8,6 +8,3 @@ Attribute Section: riscv
File Attributes
Tag_RISCV_arch: [a-zA-Z0-9_\"].*
Tag_RISCV_unaligned_access: Unaligned access
- Tag_RISCV_priv_spec: [0-9_\"].*
- Tag_RISCV_priv_spec_minor: [0-9_\"].*
-#...
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-02.d b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-02.d
index 5bdea27948b..12ca1c4dd31 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-02.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-02.d
@@ -8,6 +8,3 @@ Attribute Section: riscv
File Attributes
Tag_RISCV_arch: [a-zA-Z0-9_\"].*
Tag_RISCV_unaligned_access: Unaligned access
- Tag_RISCV_priv_spec: [0-9_\"].*
- Tag_RISCV_priv_spec_minor: [0-9_\"].*
-#...
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-03.d b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-03.d
index ac886fb7681..e41351da011 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-03.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-03.d
@@ -8,6 +8,3 @@ Attribute Section: riscv
File Attributes
Tag_RISCV_arch: [a-zA-Z0-9_\"].*
Tag_RISCV_unaligned_access: Unaligned access
- Tag_RISCV_priv_spec: [0-9_\"].*
- Tag_RISCV_priv_spec_minor: [0-9_\"].*
-#...
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-04.d b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-04.d
index dd45f76317a..ac2a766cfca 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-04.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-04.d
@@ -7,6 +7,3 @@
Attribute Section: riscv
File Attributes
Tag_RISCV_arch: [a-zA-Z0-9_\"].*
- Tag_RISCV_priv_spec: [0-9_\"].*
- Tag_RISCV_priv_spec_minor: [0-9_\"].*
-#...
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-05.d b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-05.d
index ef0c154a121..608c05e8c38 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-05.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-strict-align-05.d
@@ -8,6 +8,3 @@ Attribute Section: riscv
File Attributes
Tag_RISCV_arch: [a-zA-Z0-9_\"].*
Tag_RISCV_unaligned_access: Unaligned access
- Tag_RISCV_priv_spec: [0-9_\"].*
- Tag_RISCV_priv_spec_minor: [0-9_\"].*
-#...
diff --git a/ld/testsuite/ld-riscv-elf/call-relax.d b/ld/testsuite/ld-riscv-elf/call-relax.d
index 46d9c84f35f..597ff675353 100644
--- a/ld/testsuite/ld-riscv-elf/call-relax.d
+++ b/ld/testsuite/ld-riscv-elf/call-relax.d
@@ -3,7 +3,7 @@
#source: call-relax-1.s
#source: call-relax-2.s
#source: call-relax-3.s
-#as: -march=rv32ic
+#as: -march=rv32ic -mno-arch-attr
#ld: -melf32lriscv
#objdump: -d
#pass
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