[binutils-gdb] x86: Add {vex} pseudo prefix
H.J.Lu
hjl@sourceware.org
Fri Jan 17 15:08:00 GMT 2020
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=42e04b360158941f4d490a38cad14b11593854fa
commit 42e04b360158941f4d490a38cad14b11593854fa
Author: H.J. Lu <hjl.tools@gmail.com>
Date: Fri Jan 17 07:07:55 2020 -0800
x86: Add {vex} pseudo prefix
There are 2-byte VEX prefix and 3-byte VEX prefix. 2-byte VEX prefix
can't encode all operands. By default, assembler tries 2-byte VEX prefix
first. {vex3} can be used to force 3-byte VEX prefix. This patch adds
{vex} pseudo prefix and keeps {vex2} for backward compatibility.
gas/
* config/tc-i386.c (_i386_insn): Replace vex_encoding_vex2
with vex_encoding_vex.
(parse_insn): Likewise.
* doc/c-i386.texi: Replace {vex2} with {vex}. Update {vex}
and {vex3} documentation.
* testsuite/gas/i386/pseudos.s: Replace 3 {vex2} tests with
{vex}.
* testsuite/gas/i386/x86-64-pseudos.s: Likewise.
opcodes/
* i386-opc.tbl: Add {vex} pseudo prefix.
* i386-tbl.h: Regenerated.
Diff:
---
gas/ChangeLog | 11 +++++++++++
gas/config/tc-i386.c | 6 +++---
gas/doc/c-i386.texi | 4 ++--
gas/testsuite/gas/i386/pseudos.s | 6 +++---
gas/testsuite/gas/i386/x86-64-pseudos.s | 6 +++---
opcodes/ChangeLog | 5 +++++
opcodes/i386-opc.tbl | 1 +
opcodes/i386-tbl.h | 12 ++++++++++++
8 files changed, 40 insertions(+), 11 deletions(-)
diff --git a/gas/ChangeLog b/gas/ChangeLog
index f2b49b7..e3adaa7 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,14 @@
+2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (_i386_insn): Replace vex_encoding_vex2
+ with vex_encoding_vex.
+ (parse_insn): Likewise.
+ * doc/c-i386.texi: Replace {vex2} with {vex}. Update {vex}
+ and {vex3} documentation.
+ * testsuite/gas/i386/pseudos.s: Replace 3 {vex2} tests with
+ {vex}.
+ * testsuite/gas/i386/x86-64-pseudos.s: Likewise.
+
2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR 25376
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 3f7f422..8728725 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -419,7 +419,7 @@ struct _i386_insn
enum
{
vex_encoding_default = 0,
- vex_encoding_vex2,
+ vex_encoding_vex,
vex_encoding_vex3,
vex_encoding_evex
} vec_encoding;
@@ -4722,8 +4722,8 @@ parse_insn (char *line, char *mnemonic)
i.dir_encoding = dir_encoding_store;
break;
case 0x4:
- /* {vex2} */
- i.vec_encoding = vex_encoding_vex2;
+ /* {vex} */
+ i.vec_encoding = vex_encoding_vex;
break;
case 0x5:
/* {vex3} */
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index 4b25803..e8685dd 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -758,10 +758,10 @@ Different encoding options can be specified via pseudo prefixes:
@samp{@{store@}} -- prefer store-form instruction.
@item
-@samp{@{vex2@}} -- prefer 2-byte VEX prefix for VEX instruction.
+@samp{@{vex@}} -- encode with VEX prefix.
@item
-@samp{@{vex3@}} -- prefer 3-byte VEX prefix for VEX instruction.
+@samp{@{vex3@}} -- encode with 3-byte VEX prefix.
@item
@samp{@{evex@}} -- encode with EVEX prefix.
diff --git a/gas/testsuite/gas/i386/pseudos.s b/gas/testsuite/gas/i386/pseudos.s
index 419a4c5..19900dd 100644
--- a/gas/testsuite/gas/i386/pseudos.s
+++ b/gas/testsuite/gas/i386/pseudos.s
@@ -6,9 +6,9 @@ _start:
{vex3} {load} vmovaps %xmm7,%xmm2
{vex3} {store} vmovaps %xmm7,%xmm2
vmovaps %xmm7,%xmm2
- {vex2} vmovaps %xmm7,%xmm2
- {vex2} {load} vmovaps %xmm7,%xmm2
- {vex2} {store} vmovaps %xmm7,%xmm2
+ {vex} vmovaps %xmm7,%xmm2
+ {vex} {load} vmovaps %xmm7,%xmm2
+ {vex} {store} vmovaps %xmm7,%xmm2
{vex3} vmovaps (%eax),%xmm2
vmovaps (%eax),%xmm2
{vex2} vmovaps (%eax),%xmm2
diff --git a/gas/testsuite/gas/i386/x86-64-pseudos.s b/gas/testsuite/gas/i386/x86-64-pseudos.s
index 33712d3..14b6c92 100644
--- a/gas/testsuite/gas/i386/x86-64-pseudos.s
+++ b/gas/testsuite/gas/i386/x86-64-pseudos.s
@@ -6,9 +6,9 @@ _start:
{vex3} {load} vmovaps %xmm7,%xmm2
{vex3} {store} vmovaps %xmm7,%xmm2
vmovaps %xmm7,%xmm2
- {vex2} vmovaps %xmm7,%xmm2
- {vex2} {load} vmovaps %xmm7,%xmm2
- {vex2} {store} vmovaps %xmm7,%xmm2
+ {vex} vmovaps %xmm7,%xmm2
+ {vex} {load} vmovaps %xmm7,%xmm2
+ {vex} {store} vmovaps %xmm7,%xmm2
{vex3} vmovaps (%rax),%xmm2
vmovaps (%rax),%xmm2
{vex2} vmovaps (%rax),%xmm2
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 2d3b6d1..e48e566 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-opc.tbl: Add {vex} pseudo prefix.
+ * i386-tbl.h: Regenerated.
+
2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR 25376
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 73cd6c6..d8af259 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -879,6 +879,7 @@ rex.wrxb, 0, 0x4f, None, 1, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ld
{disp32}, 0, 0x1, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 }
{load}, 0, 0x2, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 }
{store}, 0, 0x3, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 }
+{vex}, 0, 0x4, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 }
{vex2}, 0, 0x4, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 }
{vex3}, 0, 0x5, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 }
{evex}, 0, 0x6, None, 0, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 }
diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index e9381bf..758d92b 100644
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -7600,6 +7600,18 @@ const insn_template i386_optab[] =
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0 } } } },
+ { "{vex}", 0x4, None, 0, 0,
+ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0 } } } },
{ "{vex2}", 0x4, None, 0, 0,
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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