[binutils-gdb] Add support for the GBZ80 and Z80N variants of the Z80 architecture, and add DWARF debug info suppor
Nick Clifton
nickc@sourceware.org
Fri Feb 7 14:56:00 GMT 2020
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=9fc0b501af78bc4a92f53ec712e1aaa123e0224c
commit 9fc0b501af78bc4a92f53ec712e1aaa123e0224c
Author: Sergey Belyashov <sergey.belyashov@gmail.com>
Date: Fri Feb 7 14:53:46 2020 +0000
Add support for the GBZ80 and Z80N variants of the Z80 architecture, and add DWARF debug info support to the Z80 assembler.
PR 25469
bfd * archures.c: Add GBZ80 and Z80N machine values.
* reloc.c: Add BFD_RELOC_Z80_16_BE.
* coff-z80.c: Add support for new reloc.
* coffcode.h: Add support for new machine values.
* cpu-z80.c: Add support for new machine names.
* elf32-z80.c: Add support for new reloc.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
binutils* readelf.c (get_machine_flags): Add support for Z80N machine
number.
gas * config/tc-z80.c: Add -gbz80 command line option to generate code
for the GameBoy Z80. Add support for generating DWARF.
* config/tc-z80.h: Add support for DWARF debug information
generation.
* doc/c-z80.texi: Document new command line option.
* testsuite/gas/z80/gbz80_all.d: New file.
* testsuite/gas/z80/gbz80_all.s: New file.
* testsuite/gas/z80/z80.exp: Run the new tests.
* testsuite/gas/z80/z80n_all.d: New file.
* testsuite/gas/z80/z80n_all.s: New file.
* testsuite/gas/z80/z80n_reloc.d: New file.
include * coff/internal.h (R_IMM16BE): Define.
* elf/z80.h (EF_Z80_MACH_Z80N): Define.
(R_Z80_16_BE): New reloc.
ld * emulparams/elf32z80.sh: Use z80 emulation.
* emultempl/z80.em: Make generic to both COFF and ELF Z80 emulations.
* emultempl/z80elf.em: Delete.
* testsuite/ld-elf/pr22450.d: Expect to fail for the Z80.
* testsuite/ld-elf/sec64k.exp: Fix Z80 assembly.
* testsuite/ld-unique/pr21529.s: Avoid register name conflict.
* testsuite/ld-unique/unique.s: Likewise.
* testsuite/ld-unique/unique_empty.s: Likewise.
* testsuite/ld-unique/unique_shared.s: Likewise.
* testsuite/ld-unique/unique.d: Updated expected output.
* testsuite/ld-z80/arch_z80n.d: New file.
* testsuite/ld-z80/comb_arch_z80_z80n.d: New file.
* testsuite/ld-z80/labels.s: Add more labels.
* testsuite/ld-z80/relocs.s: Add more reloc tests.
* testsuite/ld-z80/relocs_f_z80n.d: New file
opcodes * z80-dis.c: Add support for GBZ80 opcodes.
Diff:
---
bfd/ChangeLog | 12 +
bfd/archures.c | 17 +-
bfd/bfd-in2.h | 20 +-
bfd/coff-z80.c | 26 +
bfd/coffcode.h | 2 +
bfd/cpu-z80.c | 3 +-
bfd/elf32-z80.c | 350 +++++++--
bfd/libbfd.h | 1 +
bfd/reloc.c | 4 +
binutils/ChangeLog | 6 +
binutils/readelf.c | 1 +
gas/ChangeLog | 15 +
gas/config/tc-z80.c | 610 ++++++++++++---
gas/config/tc-z80.h | 21 +-
gas/doc/c-z80.texi | 22 +-
gas/testsuite/gas/z80/gbz80_all.d | 514 +++++++++++++
gas/testsuite/gas/z80/gbz80_all.s | 519 +++++++++++++
gas/testsuite/gas/z80/z80.exp | 6 +
gas/testsuite/gas/z80/z80n_all.d | 1208 +++++++++++++++++++++++++++++
gas/testsuite/gas/z80/z80n_all.s | 1242 ++++++++++++++++++++++++++++++
gas/testsuite/gas/z80/z80n_reloc.d | 10 +
include/ChangeLog | 7 +
include/coff/internal.h | 1 +
include/elf/z80.h | 2 +
ld/ChangeLog | 19 +
ld/emulparams/elf32z80.sh | 2 +-
ld/emultempl/z80.em | 215 +++---
ld/emultempl/z80elf.em | 133 ----
ld/testsuite/ld-elf/pr22450.d | 1 +
ld/testsuite/ld-elf/sec64k.exp | 8 +
ld/testsuite/ld-unique/pr21529.s | 8 +-
ld/testsuite/ld-unique/unique.d | 2 +-
ld/testsuite/ld-unique/unique.s | 6 +-
ld/testsuite/ld-unique/unique_empty.s | 2 +-
ld/testsuite/ld-unique/unique_shared.s | 6 +-
ld/testsuite/ld-z80/arch_z80n.d | 11 +
ld/testsuite/ld-z80/comb_arch_z80_z80n.d | 11 +
ld/testsuite/ld-z80/labels.s | 6 +
ld/testsuite/ld-z80/relocs.s | 11 +
ld/testsuite/ld-z80/relocs_f_z80n.d | 86 +++
opcodes/ChangeLog | 5 +
opcodes/z80-dis.c | 173 ++++-
42 files changed, 4860 insertions(+), 464 deletions(-)
diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index 584dd7f..96d8fe1 100644
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,15 @@
+2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
+
+ PR 25469
+ * archures.c: Add GBZ80 and Z80N machine values.
+ * reloc.c: Add BFD_RELOC_Z80_16_BE.
+ * coff-z80.c: Add support for new reloc.
+ * coffcode.h: Add support for new machine values.
+ * cpu-z80.c: Add support for new machine names.
+ * elf32-z80.c: Add support for new reloc.
+ * bfd-in2.h: Regenerate.
+ * libbfd.h: Regenerate.
+
2020-02-07 Nick Clifton <nickc@redhat.com>
PR 23932
diff --git a/bfd/archures.c b/bfd/archures.c
index 89c7990..5789ea2 100644
--- a/bfd/archures.c
+++ b/bfd/archures.c
@@ -504,14 +504,15 @@ DESCRIPTION
. bfd_arch_xtensa, {* Tensilica's Xtensa cores. *}
.#define bfd_mach_xtensa 1
. bfd_arch_z80,
-.#define bfd_mach_gbz80 0 {* GameBoy Z80 (reduced instruction set) *}
-.#define bfd_mach_z80strict 1 {* Z80 without undocumented opcodes. *}
-.#define bfd_mach_z180 2 {* Z180: successor with additional instructions, but without halves of ix and iy *}
-.#define bfd_mach_z80 3 {* Z80 with ixl, ixh, iyl, and iyh. *}
-.#define bfd_mach_ez80_z80 4 {* eZ80 (successor of Z80 & Z180) in Z80 (16-bit address) mode *}
-.#define bfd_mach_ez80_adl 5 {* eZ80 (successor of Z80 & Z180) in ADL (24-bit address) mode *}
-.#define bfd_mach_z80full 7 {* Z80 with all undocumented instructions. *}
-.#define bfd_mach_r800 11 {* R800: successor with multiplication. *}
+.#define bfd_mach_z80strict 1 {* Zilog Z80 without undocumented opcodes. *}
+.#define bfd_mach_z180 2 {* Zilog Z180: successor with additional instructions, but without halves of ix and iy *}
+.#define bfd_mach_z80 3 {* Zilog Z80 with ixl, ixh, iyl, and iyh. *}
+.#define bfd_mach_ez80_z80 4 {* Zilog eZ80 (successor of Z80 & Z180) in Z80 (16-bit address) mode *}
+.#define bfd_mach_ez80_adl 5 {* Zilog eZ80 (successor of Z80 & Z180) in ADL (24-bit address) mode *}
+.#define bfd_mach_z80n 6 {* Z80N *}
+.#define bfd_mach_z80full 7 {* Zilog Z80 with all undocumented instructions. *}
+.#define bfd_mach_gbz80 8 {* GameBoy Z80 (reduced instruction set) *}
+.#define bfd_mach_r800 11 {* Ascii R800: successor with multiplication. *}
. bfd_arch_lm32, {* Lattice Mico32. *}
.#define bfd_mach_lm32 1
. bfd_arch_microblaze,{* Xilinx MicroBlaze. *}
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index 2d26b81..180383b 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -1897,14 +1897,15 @@ enum bfd_architecture
bfd_arch_xtensa, /* Tensilica's Xtensa cores. */
#define bfd_mach_xtensa 1
bfd_arch_z80,
-#define bfd_mach_gbz80 0 /* GameBoy Z80 (reduced instruction set) */
-#define bfd_mach_z80strict 1 /* Z80 without undocumented opcodes. */
-#define bfd_mach_z180 2 /* Z180: successor with additional instructions, but without halves of ix and iy */
-#define bfd_mach_z80 3 /* Z80 with ixl, ixh, iyl, and iyh. */
-#define bfd_mach_ez80_z80 4 /* eZ80 (successor of Z80 & Z180) in Z80 (16-bit address) mode */
-#define bfd_mach_ez80_adl 5 /* eZ80 (successor of Z80 & Z180) in ADL (24-bit address) mode */
-#define bfd_mach_z80full 7 /* Z80 with all undocumented instructions. */
-#define bfd_mach_r800 11 /* R800: successor with multiplication. */
+#define bfd_mach_z80strict 1 /* Zilog Z80 without undocumented opcodes. */
+#define bfd_mach_z180 2 /* Zilog Z180: successor with additional instructions, but without halves of ix and iy */
+#define bfd_mach_z80 3 /* Zilog Z80 with ixl, ixh, iyl, and iyh. */
+#define bfd_mach_ez80_z80 4 /* Zilog eZ80 (successor of Z80 & Z180) in Z80 (16-bit address) mode */
+#define bfd_mach_ez80_adl 5 /* Zilog eZ80 (successor of Z80 & Z180) in ADL (24-bit address) mode */
+#define bfd_mach_z80n 6 /* Z80N */
+#define bfd_mach_z80full 7 /* Zilog Z80 with all undocumented instructions. */
+#define bfd_mach_gbz80 8 /* GameBoy Z80 (reduced instruction set) */
+#define bfd_mach_r800 11 /*Ascii R800: Z80 successor with multiplication. */
bfd_arch_lm32, /* Lattice Mico32. */
#define bfd_mach_lm32 1
bfd_arch_microblaze,/* Xilinx MicroBlaze. */
@@ -5301,6 +5302,9 @@ BFD_RELOC_XTENSA_ASM_EXPAND. */
/* Highest 16 bits of multibyte (32 or 24 bit) value. */
BFD_RELOC_Z80_WORD1,
+/* 16 bit word big endian */
+ BFD_RELOC_Z80_16_BE,
+
/* DJNZ offset. */
BFD_RELOC_Z8K_DISP7,
diff --git a/bfd/coff-z80.c b/bfd/coff-z80.c
index bb519fd..8913fb5 100644
--- a/bfd/coff-z80.c
+++ b/bfd/coff-z80.c
@@ -221,6 +221,21 @@ static bfd_howto_type howto_table[] =
0, /* src_mask */
0xffff, /* dst_mask */
FALSE), /* pcrel_offset */
+
+ BFD_HOWTO (BFD_RELOC_Z80_16_BE,
+ R_IMM16BE, /* type */
+ 0, /* rightshift */
+ 1, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_bitfield, /* complain_on_overflow */
+ 0, /* special_function */
+ "r_imm16be", /* name */
+ FALSE, /* partial_inplace */
+ 0x0000ffff, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
};
#define NUM_HOWTOS ARRAY_SIZE (howto_table)
@@ -421,6 +436,17 @@ extra_case (bfd *in_abfd,
break;
}
+ case R_IMM16BE:
+ if (reloc->howto->partial_inplace)
+ val += (bfd_get_8 ( in_abfd, data+*src_ptr+0) * 0x100 +
+ bfd_get_8 ( in_abfd, data+*src_ptr+1)) & reloc->howto->src_mask;
+
+ bfd_put_8 (in_abfd, val >> 8, data + *dst_ptr+0);
+ bfd_put_8 (in_abfd, val, data + *dst_ptr+1);
+ (*dst_ptr) += 2;
+ (*src_ptr) += 2;
+ break;
+
default:
abort ();
}
diff --git a/bfd/coffcode.h b/bfd/coffcode.h
index dec2e9c..96a7f20 100644
--- a/bfd/coffcode.h
+++ b/bfd/coffcode.h
@@ -2163,6 +2163,7 @@ coff_set_arch_mach_hook (bfd *abfd, void * filehdr)
{
case bfd_mach_z80strict << 12:
case bfd_mach_z80 << 12:
+ case bfd_mach_z80n << 12:
case bfd_mach_z80full << 12:
case bfd_mach_r800 << 12:
case bfd_mach_gbz80 << 12:
@@ -2655,6 +2656,7 @@ coff_set_flags (bfd * abfd,
{
case bfd_mach_z80strict:
case bfd_mach_z80:
+ case bfd_mach_z80n:
case bfd_mach_z80full:
case bfd_mach_r800:
case bfd_mach_gbz80:
diff --git a/bfd/cpu-z80.c b/bfd/cpu-z80.c
index 96fcfa3..76f2ff6 100644
--- a/bfd/cpu-z80.c
+++ b/bfd/cpu-z80.c
@@ -54,7 +54,8 @@ static const bfd_arch_info_type arch_info_struct[] =
N (bfd_mach_r800, "r800", 16, FALSE, M(4)),
N (bfd_mach_gbz80, "gbz80", 16, FALSE, M(5)),
N (bfd_mach_z180, "z180", 16, FALSE, M(6)),
- N (bfd_mach_ez80_z80, "ez80-z80", 16, FALSE, M(7)),
+ N (bfd_mach_z80n, "z80n", 16, FALSE, M(7)),
+ N (bfd_mach_ez80_z80, "ez80-z80", 16, FALSE, M(8)),
N (bfd_mach_ez80_adl, "ez80-adl", 24, FALSE, NULL)
};
diff --git a/bfd/elf32-z80.c b/bfd/elf32-z80.c
index 888606e..89089f5 100644
--- a/bfd/elf32-z80.c
+++ b/bfd/elf32-z80.c
@@ -30,12 +30,6 @@
/* All users of this file have bfd_octets_per_byte (abfd, sec) == 1. */
#define OCTETS_PER_BYTE(ABFD, SEC) 1
-/* Relocation functions. */
-static reloc_howto_type *bfd_elf32_bfd_reloc_type_lookup
- (bfd *, bfd_reloc_code_real_type);
-static bfd_boolean z80_info_to_howto_rel
- (bfd *, arelent *, Elf_Internal_Rela *);
-
typedef struct {
bfd_reloc_code_real_type r_type;
reloc_howto_type howto;
@@ -44,6 +38,11 @@ typedef struct {
#define BFD_EMPTY_HOWTO(rt,x) {rt, EMPTY_HOWTO(x)}
#define BFD_HOWTO(rt,a,b,c,d,e,f,g,h,i,j,k,l,m) {rt, HOWTO(a,b,c,d,e,f,g,h,i,j,k,l,m)}
+static bfd_reloc_status_type
+z80_elf_16_be_reloc (bfd *abfd, arelent *reloc_entry, asymbol *symbol,
+ void *data, asection *input_section, bfd *output_bfd,
+ char **error_message);
+
static const
bfd_howto_type elf_z80_howto_table[] =
{
@@ -253,11 +252,27 @@ bfd_howto_type elf_z80_howto_table[] =
0, /* src_mask */
0xffff, /* dst_mask */
FALSE), /* pcrel_offset */
+
+ /* An 16 bit big endian absolute relocation */
+ BFD_HOWTO (BFD_RELOC_Z80_16_BE,
+ R_Z80_16_BE, /* type */
+ 0, /* rightshift */
+ 1, /* size (0 = byte, 1 = short, 2 = long) */
+ 16, /* bitsize */
+ FALSE, /* pc_relative */
+ 0, /* bitpos */
+ complain_overflow_bitfield, /* complain_on_overflow */
+ z80_elf_16_be_reloc, /* special_function */
+ "r_imm16be", /* name */
+ FALSE, /* partial_inplace */
+ 0x00000000, /* src_mask */
+ 0x0000ffff, /* dst_mask */
+ FALSE), /* pcrel_offset */
};
static reloc_howto_type *
-bfd_elf32_bfd_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
- bfd_reloc_code_real_type code)
+z80_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
+ bfd_reloc_code_real_type code)
{
enum
{
@@ -268,16 +283,16 @@ bfd_elf32_bfd_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
for (i = 0; i < table_size; i++)
{
if (elf_z80_howto_table[i].r_type == code)
- return &elf_z80_howto_table[i].howto;
+ return &elf_z80_howto_table[i].howto;
}
- printf ("%s:%d Not found type %d\n", __FILE__, __LINE__, code);
+ printf ("%s:%d Not found BFD reloc type %d\n", __FILE__, __LINE__, code);
return NULL;
}
static reloc_howto_type *
-bfd_elf32_bfd_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED, const char *r_name)
+z80_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED, const char *r_name)
{
enum
{
@@ -288,82 +303,308 @@ bfd_elf32_bfd_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED, const char *r_name)
for (i = 0; i < table_size; i++)
{
if (elf_z80_howto_table[i].howto.name != NULL
- && strcasecmp (elf_z80_howto_table[i].howto.name, r_name) == 0)
- return &elf_z80_howto_table[i].howto;
+ && strcasecmp (elf_z80_howto_table[i].howto.name, r_name) == 0)
+ return &elf_z80_howto_table[i].howto;
}
+ printf ("%s:%d Not found ELF reloc name `%s'\n", __FILE__, __LINE__, r_name);
+
return NULL;
}
-/* Set the howto pointer for an z80 ELF reloc. */
-
-static bfd_boolean
-z80_info_to_howto_rel (bfd *abfd, arelent *cache_ptr, Elf_Internal_Rela *dst)
+static reloc_howto_type *
+z80_rtype_to_howto (bfd *abfd, unsigned r_type)
{
enum
{
table_size = sizeof (elf_z80_howto_table) / sizeof (elf_z80_howto_table[0])
};
- unsigned int i;
- unsigned int r_type = ELF32_R_TYPE (dst->r_info);
+ unsigned int i;
for (i = 0; i < table_size; i++)
{
if (elf_z80_howto_table[i].howto.type == r_type)
- {
- cache_ptr->howto = &elf_z80_howto_table[i].howto;
- return TRUE;
- }
+ return &elf_z80_howto_table[i].howto;
}
/* xgettext:c-format */
_bfd_error_handler (_("%pB: unsupported relocation type %#x"),
- abfd, r_type);
+ abfd, r_type);
+ return NULL;
+}
+
+/* Set the howto pointer for an z80 ELF reloc. */
+
+static bfd_boolean
+z80_info_to_howto_rela (bfd *abfd, arelent *cache_ptr, Elf_Internal_Rela *dst)
+{
+ unsigned int r_type = ELF32_R_TYPE (dst->r_info);
+ reloc_howto_type *howto = z80_rtype_to_howto (abfd, r_type);
+ if (howto != NULL)
+ {
+ cache_ptr->howto = howto;
+ return TRUE;
+ }
bfd_set_error (bfd_error_bad_value);
return FALSE;
}
+static bfd_reloc_status_type
+z80_elf_final_link_relocate (unsigned long r_type,
+ bfd *input_bfd,
+ bfd *output_bfd ATTRIBUTE_UNUSED,
+ asection *input_section ATTRIBUTE_UNUSED,
+ bfd_byte *contents,
+ bfd_vma offset,
+ bfd_vma value,
+ bfd_vma addend,
+ struct bfd_link_info *info ATTRIBUTE_UNUSED,
+ asection *sym_sec ATTRIBUTE_UNUSED,
+ int is_local ATTRIBUTE_UNUSED)
+{
+ bfd_boolean r;
+ reloc_howto_type *howto;
+
+ switch (r_type)
+ {
+ case R_Z80_16_BE:
+ value += addend;
+ bfd_put_8 (input_bfd, value >> 8, contents + offset + 0);
+ bfd_put_8 (input_bfd, value >> 0, contents + offset + 1);
+ return bfd_reloc_ok;
+ }
+
+ howto = z80_rtype_to_howto (input_bfd, r_type);
+ if (howto == NULL)
+ return bfd_reloc_notsupported;
+
+ r = _bfd_final_link_relocate (howto, input_bfd, input_section, contents,
+ offset, value, addend);
+ return r ? bfd_reloc_ok : bfd_reloc_notsupported;
+}
+
+static bfd_boolean
+z80_elf_relocate_section (bfd *output_bfd,
+ struct bfd_link_info *info,
+ bfd *input_bfd,
+ asection *input_section,
+ bfd_byte *contents,
+ Elf_Internal_Rela *relocs,
+ Elf_Internal_Sym *local_syms,
+ asection **local_sections)
+{
+ Elf_Internal_Shdr *symtab_hdr;
+ struct elf_link_hash_entry **sym_hashes;
+ Elf_Internal_Rela *rel, *relend;
+
+ symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
+ sym_hashes = elf_sym_hashes (input_bfd);
+
+ rel = relocs;
+ relend = relocs + input_section->reloc_count;
+ for (; rel < relend; rel++)
+ {
+ unsigned int r_type;
+ unsigned long r_symndx;
+ Elf_Internal_Sym *sym;
+ asection *sec;
+ struct elf_link_hash_entry *h;
+ bfd_vma relocation;
+
+ /* This is a final link. */
+ r_symndx = ELF32_R_SYM (rel->r_info);
+ r_type = ELF32_R_TYPE (rel->r_info);
+ h = NULL;
+ sym = NULL;
+ sec = NULL;
+ if (r_symndx < symtab_hdr->sh_info)
+ {
+ sym = local_syms + r_symndx;
+ sec = local_sections[r_symndx];
+ relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
+ }
+ else
+ {
+ bfd_boolean unresolved_reloc, warned, ignored;
+
+ RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
+ r_symndx, symtab_hdr, sym_hashes,
+ h, sec, relocation,
+ unresolved_reloc, warned, ignored);
+ }
+
+ if (sec != NULL && discarded_section (sec))
+ {
+ /* For relocs against symbols from removed linkonce sections,
+ or sections discarded by a linker script, we just want the
+ section contents cleared. Avoid any special processing. */
+ reloc_howto_type *howto;
+ howto = z80_rtype_to_howto (input_bfd, r_type);
+ RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
+ rel, 1, relend, howto, 0, contents);
+ }
+
+ if (bfd_link_relocatable (info))
+ continue;
+
+
+ z80_elf_final_link_relocate (r_type, input_bfd, output_bfd,
+ input_section,
+ contents, rel->r_offset,
+ relocation, rel->r_addend,
+ info, sec, h == NULL);
+ }
+
+ return TRUE;
+}
+
+/* The final processing done just before writing out a Z80 ELF object
+ file. This gets the Z80 architecture right based on the machine
+ number. */
+
static bfd_boolean
-z80_elf_set_mach_from_flags (bfd *abfd)
+z80_elf_final_write_processing (bfd *abfd)
{
- int mach;
- switch (elf_elfheader (abfd)->e_flags)
+ unsigned long val = bfd_get_mach (abfd);
+
+ switch (val)
{
- case EF_Z80_MACH_GBZ80:
- mach = bfd_mach_gbz80;
+ default:
+ _bfd_error_handler (_("%pB: unsupported bfd mach %#lx"),
+ abfd, val);
+ /* fall through */
+ case bfd_mach_z80:
+ case bfd_mach_z80full:
+ case bfd_mach_z80strict:
+ val = EF_Z80_MACH_Z80;
break;
- case EF_Z80_MACH_Z80:
- mach = bfd_mach_z80;
+ case bfd_mach_gbz80:
+ val = EF_Z80_MACH_GBZ80;
break;
- case EF_Z80_MACH_Z180:
- mach = bfd_mach_z180;
+ case bfd_mach_z80n:
+ val = EF_Z80_MACH_Z80N;
break;
- case EF_Z80_MACH_EZ80_Z80:
- mach = bfd_mach_ez80_z80;
+ case bfd_mach_z180:
+ val = EF_Z80_MACH_Z180;
break;
- case EF_Z80_MACH_EZ80_ADL:
- mach = bfd_mach_ez80_adl;
+ case bfd_mach_ez80_z80:
+ val = EF_Z80_MACH_EZ80_Z80;
break;
- case EF_Z80_MACH_R800:
- mach = bfd_mach_r800;
+ case bfd_mach_ez80_adl:
+ val = EF_Z80_MACH_EZ80_ADL;
break;
- default:
- mach = bfd_mach_z80;
+ case bfd_mach_r800:
+ val = EF_Z80_MACH_R800;
break;
}
+ elf_elfheader (abfd)->e_machine = EM_Z80;
+ elf_elfheader (abfd)->e_flags &= ~EF_Z80_MACH_MSK;
+ elf_elfheader (abfd)->e_flags |= val;
+ return _bfd_elf_final_write_processing (abfd);
+}
- bfd_default_set_arch_mach (abfd, bfd_arch_z80, mach);
- return TRUE;
+/* Set the right machine number. */
+static bfd_boolean
+z80_elf_object_p (bfd *abfd)
+{
+ unsigned int mach;
+
+ if (elf_elfheader (abfd)->e_machine == EM_Z80)
+ {
+ int e_mach = elf_elfheader (abfd)->e_flags & EF_Z80_MACH_MSK;
+ switch (e_mach)
+ {
+ default:
+ _bfd_error_handler (_("%pB: unsupported mach %#x"),
+ abfd, e_mach);
+ /* fall through */
+ case EF_Z80_MACH_Z80:
+ mach = bfd_mach_z80;
+ break;
+ case EF_Z80_MACH_GBZ80:
+ mach = bfd_mach_gbz80;
+ break;
+ case EF_Z80_MACH_Z180:
+ mach = bfd_mach_z180;
+ break;
+ case EF_Z80_MACH_EZ80_Z80:
+ mach = bfd_mach_ez80_z80;
+ break;
+ case EF_Z80_MACH_EZ80_ADL:
+ mach = bfd_mach_ez80_adl;
+ break;
+ case EF_Z80_MACH_R800:
+ mach = bfd_mach_r800;
+ break;
+ case EF_Z80_MACH_Z80N:
+ mach = bfd_mach_z80n;
+ break;
+ }
+ }
+ else
+ {
+ _bfd_error_handler (_("%pB: unsupported arch %#x"),
+ abfd, elf_elfheader (abfd)->e_machine);
+ mach = bfd_mach_z80;
+ }
+ return bfd_default_set_arch_mach (abfd, bfd_arch_z80, mach);
}
static int
-z80_is_local_label_name (bfd * abfd ATTRIBUTE_UNUSED,
- const char * name)
+z80_is_local_label_name (bfd * abfd ATTRIBUTE_UNUSED,
+ const char * name)
{
return (name[0] == '.' && name[1] == 'L') ||
- _bfd_elf_is_local_label_name (abfd, name);
+ _bfd_elf_is_local_label_name (abfd, name);
}
+static bfd_reloc_status_type
+z80_elf_16_be_reloc (bfd *abfd,
+ arelent *reloc_entry,
+ asymbol *symbol,
+ void *data,
+ asection *input_section,
+ bfd *output_bfd,
+ char **error_message)
+{
+ bfd_vma val;
+ long x;
+ bfd_size_type octets = (reloc_entry->address
+ * OCTETS_PER_BYTE (abfd, input_section));
+
+ /* If this is a relocatable link (output_bfd test tells us), just
+ call the generic function. Any adjustment will be done at final
+ link time. */
+ if (output_bfd != NULL)
+ return bfd_elf_generic_reloc (abfd, reloc_entry, symbol, data,
+ input_section, output_bfd, error_message);
+
+ /* Get symbol value. */
+ val = 0;
+ if (!bfd_is_com_section (symbol->section))
+ val = symbol->value;
+ val += symbol->section->output_offset + input_section->output_offset;
+ if (symbol->section->output_section)
+ val += symbol->section->output_section->vma;
+
+ val += reloc_entry->addend;
+ if (reloc_entry->howto->partial_inplace)
+ {
+ x = bfd_get_8 (abfd, (bfd_byte *) data + octets + 0) * 0x100;
+ x += bfd_get_8 (abfd, (bfd_byte *) data + octets + 1);
+ x &= ~reloc_entry->howto->src_mask;
+ }
+ else
+ x = 0;
+
+ x |= val & reloc_entry->howto->dst_mask;
+ if (x < -0x8000 || x >= 0x10000)
+ return bfd_reloc_outofrange;
+
+ bfd_put_8 (abfd, x >> 8, (bfd_byte *) data + octets + 0);
+ bfd_put_8 (abfd, x >> 0, (bfd_byte *) data + octets + 1);
+ return bfd_reloc_ok;
+}
#define ELF_ARCH bfd_arch_z80
#define ELF_MACHINE_CODE EM_Z80
@@ -372,9 +613,20 @@ z80_is_local_label_name (bfd * abfd ATTRIBUTE_UNUSED,
#define TARGET_LITTLE_SYM z80_elf32_vec
#define TARGET_LITTLE_NAME "elf32-z80"
-#define elf_info_to_howto NULL
-#define elf_info_to_howto_rel z80_info_to_howto_rel
-#define elf_backend_object_p z80_elf_set_mach_from_flags
+#define elf_backend_can_refcount 1
+#define elf_backend_can_gc_sections 1
+#define elf_backend_stack_align 1
+#define elf_backend_rela_normal 1
+
+#define elf_info_to_howto z80_info_to_howto_rela
+#define elf_info_to_howto_rel z80_info_to_howto_rela
+
+#define elf_backend_final_write_processing z80_elf_final_write_processing
+#define elf_backend_object_p z80_elf_object_p
+#define elf_backend_relocate_section z80_elf_relocate_section
+
+#define bfd_elf32_bfd_reloc_type_lookup z80_reloc_type_lookup
+#define bfd_elf32_bfd_reloc_name_lookup z80_reloc_name_lookup
#define bfd_elf32_bfd_is_local_label_name z80_is_local_label_name
#include "elf32-target.h"
diff --git a/bfd/libbfd.h b/bfd/libbfd.h
index d97d4e5..a3684a9 100644
--- a/bfd/libbfd.h
+++ b/bfd/libbfd.h
@@ -2875,6 +2875,7 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
"BFD_RELOC_Z80_BYTE3",
"BFD_RELOC_Z80_WORD0",
"BFD_RELOC_Z80_WORD1",
+ "BFD_RELOC_Z80_16_BE",
"BFD_RELOC_Z8K_DISP7",
"BFD_RELOC_Z8K_CALLR",
"BFD_RELOC_Z8K_IMM4L",
diff --git a/bfd/reloc.c b/bfd/reloc.c
index 33cd671..dab7d17 100644
--- a/bfd/reloc.c
+++ b/bfd/reloc.c
@@ -6697,6 +6697,10 @@ ENUM
BFD_RELOC_Z80_WORD1
ENUMDOC
Highest 16 bits of multibyte (32 or 24 bit) value.
+ENUM
+ BFD_RELOC_Z80_16_BE
+ENUMDOC
+ Like BFD_RELOC_16 but big-endian.
ENUM
BFD_RELOC_Z8K_DISP7
diff --git a/binutils/ChangeLog b/binutils/ChangeLog
index 3edf233..eea4756 100644
--- a/binutils/ChangeLog
+++ b/binutils/ChangeLog
@@ -1,3 +1,9 @@
+2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
+
+ PR 25469
+ * readelf.c (get_machine_flags): Add support for Z80N machine
+ number.
+
2020-02-07 Nick Clifton <nickc@redhat.com>
* dwarf.c (display_debug_lines_decoded): Force a NUL termination
diff --git a/binutils/readelf.c b/binutils/readelf.c
index d2ced1e..58667dd 100644
--- a/binutils/readelf.c
+++ b/binutils/readelf.c
@@ -3769,6 +3769,7 @@ get_machine_flags (Filedata * filedata, unsigned e_flags, unsigned e_machine)
case EF_Z80_MACH_EZ80_Z80: strcat (buf, ", EZ80"); break;
case EF_Z80_MACH_EZ80_ADL: strcat (buf, ", EZ80, ADL"); break;
case EF_Z80_MACH_GBZ80: strcat (buf, ", GBZ80"); break;
+ case EF_Z80_MACH_Z80N: strcat (buf, ", Z80N"); break;
default:
strcat (buf, _(", unknown")); break;
}
diff --git a/gas/ChangeLog b/gas/ChangeLog
index b600180..1cc473b 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,18 @@
+2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
+
+ PR 25469
+ * config/tc-z80.c: Add -gbz80 command line option to generate code
+ for the GameBoy Z80. Add support for generating DWARF.
+ * config/tc-z80.h: Add support for DWARF debug information
+ generation.
+ * doc/c-z80.texi: Document new command line option.
+ * testsuite/gas/z80/gbz80_all.d: New file.
+ * testsuite/gas/z80/gbz80_all.s: New file.
+ * testsuite/gas/z80/z80.exp: Run the new tests.
+ * testsuite/gas/z80/z80n_all.d: New file.
+ * testsuite/gas/z80/z80n_all.s: New file.
+ * testsuite/gas/z80/z80n_reloc.d: New file.
+
2020-02-06 H.J. Lu <hongjiu.lu@intel.com>
PR gas/25381
diff --git a/gas/config/tc-z80.c b/gas/config/tc-z80.c
index d823549..abe8c11 100644
--- a/gas/config/tc-z80.c
+++ b/gas/config/tc-z80.c
@@ -24,6 +24,7 @@
#include "subsegs.h"
#include "elf/z80.h"
#include "dwarf2dbg.h"
+#include "dw2gencfi.h"
/* Exported constants. */
const char comment_chars[] = ";\0";
@@ -43,6 +44,7 @@ enum options
OPTION_MACH_EZ80_Z80,
OPTION_MACH_EZ80_ADL,
OPTION_MACH_GBZ80,
+ OPTION_MACH_Z80N,
OPTION_MACH_INST,
OPTION_MACH_NO_INST,
OPTION_MACH_IUD,
@@ -63,6 +65,7 @@ enum options
#define INS_GBZ80 (1 << 2)
#define INS_Z180 (1 << 3)
#define INS_EZ80 (1 << 4)
+#define INS_Z80N (1 << 5)
#define INS_MARCH_MASK 0xffff
#define INS_IDX_HALF (1 << 16)
@@ -72,7 +75,7 @@ enum options
#define INS_ROT_II_LD (1 << 20) /* instructions like SLA (ii+d),r; which is: LD r,(ii+d); SLA r; LD (ii+d),r */
#define INS_TUNE_MASK 0xffff0000
-#define INS_NOT_GBZ80 (INS_Z80 | INS_Z180 | INS_R800 | INS_EZ80)
+#define INS_NOT_GBZ80 (INS_Z80 | INS_Z180 | INS_R800 | INS_EZ80 | INS_Z80N)
#define INS_ALL 0
#define INS_UNDOC (INS_IDX_HALF | INS_IN_F_C)
@@ -85,6 +88,8 @@ struct option md_longopts[] =
{ "z180", no_argument, NULL, OPTION_MACH_Z180},
{ "ez80", no_argument, NULL, OPTION_MACH_EZ80_Z80},
{ "ez80-adl", no_argument, NULL, OPTION_MACH_EZ80_ADL},
+ { "gbz80", no_argument, NULL, OPTION_MACH_GBZ80},
+ { "z80n", no_argument, NULL, OPTION_MACH_Z80N},
{ "fp-s", required_argument, NULL, OPTION_FP_SINGLE_FORMAT},
{ "fp-d", required_argument, NULL, OPTION_FP_DOUBLE_FORMAT},
{ "strict", no_argument, NULL, OPTION_MACH_FUD},
@@ -243,7 +248,7 @@ md_parse_option (int c, const char* arg)
ins_err = (ins_err & INS_MARCH_MASK) | (~INS_Z80 & INS_MARCH_MASK);
break;
case OPTION_MACH_R800:
- ins_ok = INS_R800 | INS_IDX_HALF;
+ ins_ok = INS_R800 | INS_IDX_HALF | INS_IN_F_C;
ins_err = INS_UNPORT;
break;
case OPTION_MACH_Z180:
@@ -251,12 +256,12 @@ md_parse_option (int c, const char* arg)
ins_err = INS_UNDOC | INS_UNPORT;
break;
case OPTION_MACH_EZ80_Z80:
- ins_ok = INS_EZ80;
+ ins_ok = INS_EZ80 | INS_IDX_HALF;
ins_err = (INS_UNDOC | INS_UNPORT) & ~INS_IDX_HALF;
cpu_mode = 0;
break;
case OPTION_MACH_EZ80_ADL:
- ins_ok = INS_EZ80;
+ ins_ok = INS_EZ80 | INS_IDX_HALF;
ins_err = (INS_UNDOC | INS_UNPORT) & ~INS_IDX_HALF;
cpu_mode = 1;
break;
@@ -264,6 +269,10 @@ md_parse_option (int c, const char* arg)
ins_ok = INS_GBZ80;
ins_err = INS_UNDOC | INS_UNPORT;
break;
+ case OPTION_MACH_Z80N:
+ ins_ok = INS_Z80N | INS_UNPORT | INS_UNDOC;
+ ins_err = 0;
+ break;
case OPTION_FP_SINGLE_FORMAT:
str_to_float = get_str_to_float (arg);
break;
@@ -325,11 +334,13 @@ md_show_usage (FILE * f)
{
fprintf (f, "\n\
CPU model options:\n\
- -z80\t\t\t assemble for Z80\n\
- -r800\t\t\t assemble for R800\n\
- -z180\t\t\t assemble for Z180\n\
- -ez80\t\t\t assemble for eZ80 in Z80 mode by default\n\
- -ez80-adl\t\t assemble for eZ80 in ADL mode by default\n\
+ -z80\t\t\t assemble for Zilog Z80\n\
+ -r800\t\t\t assemble for Ascii R800\n\
+ -z180\t\t\t assemble for Zilog Z180\n\
+ -ez80\t\t\t assemble for Zilog eZ80 in Z80 mode by default\n\
+ -ez80-adl\t\t assemble for Zilog eZ80 in ADL mode by default\n\
+ -gbz80\t\t assemble for GameBoy Z80\n\
+ -z80n\t\t\t assemble for Z80N\n\
\n\
Compatibility options:\n\
-local-prefix=TEXT\t treat labels prefixed by TEXT as local\n\
@@ -507,6 +518,9 @@ z80_md_end (void)
case INS_EZ80:
mach_type = cpu_mode ? bfd_mach_ez80_adl : bfd_mach_ez80_z80;
break;
+ case INS_Z80N:
+ mach_type = bfd_mach_z80n;
+ break;
default:
mach_type = 0;
}
@@ -536,6 +550,9 @@ z80_elf_final_processing (void)
case INS_EZ80:
elf_flags = cpu_mode ? EF_Z80_MACH_EZ80_ADL : EF_Z80_MACH_EZ80_Z80;
break;
+ case INS_Z80N:
+ elf_flags = EF_Z80_MACH_Z80N;
+ break;
default:
elf_flags = 0;
}
@@ -843,6 +860,22 @@ parse_exp_not_indexed (const char *s, expressionS *op)
}
op->X_md = indir = is_indir (p);
+ if (indir && (ins_ok & INS_GBZ80))
+ { /* check for instructions like ld a,(hl+), ld (hl-),a */
+ p = skip_space (p+1);
+ if (!strncasecmp (p, "hl", 2))
+ {
+ p = skip_space(p+2);
+ if (*skip_space(p+1) == ')' && (*p == '+' || *p == '-'))
+ {
+ op->X_op = O_md1;
+ op->X_add_symbol = NULL;
+ op->X_add_number = (*p == '+') ? REG_HL : -REG_HL;
+ input_line_pointer = (char*)skip_space(p + 1) + 1;
+ return input_line_pointer;
+ }
+ }
+ }
input_line_pointer = (char*) s ;
expression (op);
switch (op->X_op)
@@ -1122,7 +1155,6 @@ static void
emit_byte (expressionS * val, bfd_reloc_code_real_type r_type)
{
char *p;
- int lo, hi;
if (r_type == BFD_RELOC_8)
{
@@ -1141,15 +1173,12 @@ emit_byte (expressionS * val, bfd_reloc_code_real_type r_type)
}
else if (val->X_op == O_constant)
{
- lo = -128;
- hi = (BFD_RELOC_8 == r_type) ? 255 : 127;
-
- if ((val->X_add_number < lo) || (val->X_add_number > hi))
+ if ((val->X_add_number < -128) || (val->X_add_number >= 128))
{
if (r_type == BFD_RELOC_Z80_DISP8)
- as_bad (_("offset too large"));
+ as_bad (_("index overflow (%+ld)"), val->X_add_number);
else
- as_warn (_("overflow"));
+ as_bad (_("offset overflow (%+ld)"), val->X_add_number);
}
}
else
@@ -1340,6 +1369,51 @@ emit_s (char prefix, char opcode, const char *args)
}
static const char *
+emit_sub (char prefix, char opcode, const char *args)
+{
+ expressionS arg_s;
+ const char *p;
+
+ if (!(ins_ok & INS_GBZ80))
+ return emit_s (prefix, opcode, args);
+ p = parse_exp (args, & arg_s);
+ if (*p++ != ',')
+ {
+ error (_("bad instruction syntax"));
+ return p;
+ }
+
+ if (arg_s.X_md != 0 || arg_s.X_op != O_register || arg_s.X_add_number != REG_A)
+ ill_op ();
+
+ p = parse_exp (p, & arg_s);
+
+ emit_sx (prefix, opcode, & arg_s);
+ return p;
+}
+
+static const char *
+emit_swap (char prefix, char opcode, const char *args)
+{
+ expressionS reg;
+ const char *p;
+ char *q;
+
+ if (!(ins_ok & INS_Z80N))
+ return emit_mr (prefix, opcode, args);
+
+ /* check for alias swap a for swapnib of Z80N */
+ p = parse_exp (args, ®);
+ if (reg.X_md != 0 || reg.X_op != O_register || reg.X_add_number != REG_A)
+ ill_op ();
+
+ q = frag_more (2);
+ *q++ = 0xED;
+ *q = 0x23;
+ return p;
+}
+
+static const char *
emit_call (char prefix ATTRIBUTE_UNUSED, char opcode, const char * args)
{
expressionS addr;
@@ -1425,6 +1499,12 @@ emit_jp (char prefix, char opcode, const char * args)
*q++ = (rnum & R_IX) ? 0xDD : 0xFD;
*q = prefix;
}
+ else if (addr.X_op == O_register && rnum == REG_C && (ins_ok & INS_Z80N))
+ {
+ q = frag_more (2);
+ *q++ = 0xED;
+ *q = 0x98;
+ }
else
ill_op ();
}
@@ -1496,6 +1576,31 @@ emit_pop (char prefix ATTRIBUTE_UNUSED, char opcode, const char * args)
}
static const char *
+emit_push (char prefix, char opcode, const char * args)
+{
+ expressionS arg;
+ const char *p;
+ char *q;
+
+ p = parse_exp (args, & arg);
+ if (arg.X_op == O_register)
+ return emit_pop (prefix, opcode, args);
+
+ if (arg.X_md || arg.X_op == O_md1 || !(ins_ok & INS_Z80N))
+ ill_op ();
+
+ q = frag_more (2);
+ *q++ = 0xED;
+ *q = 0x8A;
+
+ q = frag_more (2);
+ fix_new_exp (frag_now, q - frag_now->fr_literal, 2, &arg, FALSE,
+ BFD_RELOC_Z80_16_BE);
+
+ return p;
+}
+
+static const char *
emit_retcc (char prefix ATTRIBUTE_UNUSED, char opcode, const char * args)
{
char cc, *q;
@@ -1571,19 +1676,38 @@ emit_add (char prefix, char opcode, const char * args)
if ((term.X_md) || (term.X_op != O_register))
ill_op ();
else
- switch (term.X_add_number & ~R_INDEX)
+ switch (term.X_add_number)
{
case REG_A:
p = emit_s (0, prefix, p);
break;
+ case REG_SP:
+ p = parse_exp (p, &term);
+ if (!(ins_ok & INS_GBZ80) || term.X_md || term.X_op == O_register)
+ ill_op ();
+ q = frag_more (1);
+ *q = 0xE8;
+ emit_byte (&term, BFD_RELOC_Z80_DISP8);
+ break;
+ case REG_BC:
+ case REG_DE:
+ if (!(ins_ok & INS_Z80N))
+ {
+ ill_op ();
+ break;
+ }
+ /* Fall through. */
case REG_HL:
+ case REG_IX:
+ case REG_IY:
lhs = term.X_add_number;
p = parse_exp (p, &term);
- if ((!term.X_md) && (term.X_op == O_register))
+ rhs = term.X_add_number;
+ if (term.X_md != 0 || term.X_op == O_md1)
+ ill_op ();
+ else if ((term.X_op == O_register) && (rhs & R_ARITH) && (rhs == lhs || (rhs & ~R_INDEX) != REG_HL))
{
- rhs = term.X_add_number;
- if ((rhs & R_ARITH)
- && ((rhs == lhs) || ((rhs & ~R_INDEX) != REG_HL)))
+ if (1)
{
q = frag_more ((lhs & R_INDEX) ? 2 : 1);
if (lhs & R_INDEX)
@@ -1592,6 +1716,24 @@ emit_add (char prefix, char opcode, const char * args)
break;
}
}
+ else if (!(lhs & R_INDEX) && (ins_ok & INS_Z80N))
+ {
+ if (term.X_op == O_register && rhs == REG_A)
+ { /* ADD BC/DE/HL,A */
+ q = frag_more (2);
+ *q++ = 0xED;
+ *q = 0x33 - (lhs & 3);
+ break;
+ }
+ else if (term.X_op != O_register && term.X_op != O_md1)
+ { /* ADD BC/DE/HL,nn */
+ q = frag_more (2);
+ *q++ = 0xED;
+ *q = 0x36 - (lhs & 3);
+ emit_word (&term);
+ break;
+ }
+ }
/* Fall through. */
default:
ill_op ();
@@ -1628,6 +1770,27 @@ emit_bit (char prefix, char opcode, const char * args)
return p;
}
+/* BSLA DE,B; BSRA DE,B; BSRL DE,B; BSRF DE,B; BRLC DE,B (Z80N only) */
+static const char *
+emit_bshft (char prefix, char opcode, const char * args)
+{
+ expressionS r1, r2;
+ const char *p;
+ char *q;
+
+ p = parse_exp (args, & r1);
+ if (*p++ != ',')
+ error (_("bad instruction syntax"));
+ p = parse_exp (p, & r2);
+ if (r1.X_md || r1.X_op != O_register || r1.X_add_number != REG_DE ||
+ r2.X_md || r2.X_op != O_register || r2.X_add_number != REG_B)
+ ill_op ();
+ q = frag_more (2);
+ *q++ = prefix;
+ *q = opcode;
+ return p;
+}
+
static const char *
emit_jpcc (char prefix, char opcode, const char * args)
{
@@ -1726,13 +1889,21 @@ emit_in (char prefix ATTRIBUTE_UNUSED, char opcode ATTRIBUTE_UNUSED,
char *q;
p = parse_exp (args, ®);
- if (*p++ != ',')
+ if (reg.X_md && reg.X_op == O_register && reg.X_add_number == REG_C)
+ { /* permit instruction in (c) as alias for in f,(c) */
+ port = reg;
+ reg.X_md = 0;
+ reg.X_add_number = REG_F;
+ }
+ else
{
- error (_("bad instruction syntax"));
- return p;
+ if (*p++ != ',')
+ {
+ error (_("bad instruction syntax"));
+ return p;
+ }
+ p = parse_exp (p, &port);
}
-
- p = parse_exp (p, &port);
if (reg.X_md == 0
&& reg.X_op == O_register
&& (reg.X_add_number <= 7 || reg.X_add_number == REG_F)
@@ -1958,7 +2129,15 @@ emit_ld_m_r (expressionS *dst, expressionS *src)
switch (dst->X_op)
{
case O_md1:
- prefix = (dst->X_add_number == REG_IX) ? 0xDD : 0xFD;
+ if (ins_ok & INS_GBZ80)
+ { /* LD (HL+),A or LD (HL-),A */
+ if (src->X_op != O_register || src->X_add_number != REG_A)
+ break;
+ *frag_more (1) = (dst->X_add_number == REG_HL) ? 0x22 : 0x32;
+ return;
+ }
+ else
+ prefix = (dst->X_add_number == REG_IX) ? 0xDD : 0xFD;
/* Fall through. */
case O_register:
switch (dst->X_add_number)
@@ -1998,7 +2177,7 @@ emit_ld_m_r (expressionS *dst, expressionS *src)
if (src->X_add_number == REG_A)
{
q = frag_more (1);
- *q = 0x32;
+ *q = (ins_ok & INS_GBZ80) ? 0xEA : 0x32;
emit_word (dst);
return;
}
@@ -2112,6 +2291,15 @@ emit_ld_r_m (expressionS *dst, expressionS *src)
switch (src->X_op)
{
case O_md1:
+ if (ins_ok & INS_GBZ80)
+ { /* LD A,(HL+) or LD A,(HL-) */
+ if (dst->X_op == O_register && dst->X_add_number == REG_A)
+ *frag_more (1) = (src->X_add_number == REG_HL) ? 0x2A : 0x3A;
+ else
+ ill_op ();
+ break;
+ }
+ /* Fall through. */
case O_register:
if (dst->X_add_number > 7)
ill_op ();
@@ -2140,7 +2328,7 @@ emit_ld_r_m (expressionS *dst, expressionS *src)
if (dst->X_add_number == REG_A)
{
q = frag_more (1);
- *q = 0x3A;
+ *q = (ins_ok & INS_GBZ80) ? 0xFA : 0x3A;
emit_word (src);
}
}
@@ -2208,8 +2396,6 @@ emit_ld_r_r (expressionS *dst, expressionS *src)
default:
ill_op ();
}
- if (ins_ok & INS_GBZ80)
- ill_op ();
opcode = 0xF9;
break;
case REG_HL:
@@ -2522,7 +2708,7 @@ emit_lddldi (char prefix, char opcode, const char * args)
p = parse_exp (args, & dst);
if (*p++ != ',')
error (_("bad instruction syntax"));
- p = parse_exp (args, & src);
+ p = parse_exp (p, & src);
if (dst.X_op != O_register || src.X_op != O_register)
ill_op ();
@@ -2568,12 +2754,18 @@ emit_ldh (char prefix ATTRIBUTE_UNUSED, char opcode ATTRIBUTE_UNUSED,
&& dst.X_op == O_register
&& dst.X_add_number == REG_A
&& src.X_md != 0
- && src.X_op != O_md1
- && src.X_op != O_register)
+ && src.X_op != O_md1)
{
- q = frag_more (1);
- *q = 0xF0;
- emit_byte (& src, BFD_RELOC_8);
+ if (src.X_op != O_register)
+ {
+ q = frag_more (1);
+ *q = 0xF0;
+ emit_byte (& src, BFD_RELOC_8);
+ }
+ else if (src.X_add_number == REG_C)
+ *frag_more (1) = 0xF2;
+ else
+ ill_op ();
}
else if (dst.X_md != 0
&& dst.X_op != O_md1
@@ -2605,6 +2797,29 @@ emit_ldh (char prefix ATTRIBUTE_UNUSED, char opcode ATTRIBUTE_UNUSED,
}
static const char *
+emit_ldhl (char prefix ATTRIBUTE_UNUSED, char opcode, const char * args)
+{
+ expressionS dst, src;
+ const char *p;
+ char *q;
+ p = parse_exp (args, & dst);
+ if (*p++ != ',')
+ {
+ error (_("bad instruction syntax"));
+ return p;
+ }
+
+ p = parse_exp (p, & src);
+ if (dst.X_md || dst.X_op != O_register || dst.X_add_number != REG_SP
+ || src.X_md || src.X_op == O_register || src.X_op == O_md1)
+ ill_op ();
+ q = frag_more (1);
+ *q = opcode;
+ emit_byte (& src, BFD_RELOC_Z80_DISP8);
+ return p;
+}
+
+static const char *
parse_lea_pea_args (const char * args, expressionS *op)
{
const char *p;
@@ -2700,13 +2915,76 @@ emit_mlt (char prefix, char opcode, const char * args)
ill_op ();
q = frag_more (2);
+ if (ins_ok & INS_Z80N)
+ {
+ if (arg.X_add_number != REG_DE)
+ ill_op ();
+ *q++ = 0xED;
+ *q = 0x30;
+ }
+ else
+ {
+ *q++ = prefix;
+ *q = opcode | ((arg.X_add_number & 3) << 4);
+ }
+
+ return p;
+}
+
+/* MUL D,E (Z80N only) */
+static const char *
+emit_mul (char prefix, char opcode, const char * args)
+{
+ expressionS r1, r2;
+ const char *p;
+ char *q;
+
+ p = parse_exp (args, & r1);
+ if (*p++ != ',')
+ error (_("bad instruction syntax"));
+ p = parse_exp (p, & r2);
+
+ if (r1.X_md != 0 || r1.X_op != O_register || r1.X_add_number != REG_D ||
+ r2.X_md != 0 || r2.X_op != O_register || r2.X_add_number != REG_E)
+ ill_op ();
+
+ q = frag_more (2);
*q++ = prefix;
- *q = opcode | ((arg.X_add_number & 3) << 4);
+ *q = opcode;
return p;
}
static const char *
+emit_nextreg (char prefix, char opcode ATTRIBUTE_UNUSED, const char * args)
+{
+ expressionS rr, nn;
+ const char *p;
+ char *q;
+
+ p = parse_exp (args, & rr);
+ if (*p++ != ',')
+ error (_("bad instruction syntax"));
+ p = parse_exp (p, & nn);
+ if (rr.X_md != 0 || rr.X_op == O_register || rr.X_op == O_md1 ||
+ nn.X_md != 0 || nn.X_op == O_md1)
+ ill_op ();
+ q = frag_more (2);
+ *q++ = prefix;
+ emit_byte (&rr, BFD_RELOC_8);
+ if (nn.X_op == O_register && nn.X_add_number == REG_A)
+ *q = 0x92;
+ else if (nn.X_op != O_register)
+ {
+ *q = 0x91;
+ emit_byte (&nn, BFD_RELOC_8);
+ }
+ else
+ ill_op ();
+ return p;
+}
+
+static const char *
emit_pea (char prefix, char opcode, const char * args)
{
expressionS arg;
@@ -2783,15 +3061,23 @@ emit_tst (char prefix, char opcode, const char *args)
if (arg_s.X_md)
ill_op ();
q = frag_more (2);
- *q++ = prefix;
- *q = opcode | 0x60;
+ if (ins_ok & INS_Z80N)
+ {
+ *q++ = 0xED;
+ *q = 0x27;
+ }
+ else
+ {
+ *q++ = prefix;
+ *q = opcode | 0x60;
+ }
emit_byte (& arg_s, BFD_RELOC_8);
}
return p;
}
static const char *
-emit_tstio (char prefix, char opcode, const char *args)
+emit_insn_n (char prefix, char opcode, const char *args)
{
expressionS arg;
const char *p;
@@ -3130,6 +3416,7 @@ const pseudo_typeS md_pseudo_table[] =
{ ".set", s_set, 0},
{ ".z180", set_inss, INS_Z180},
{ ".z80", set_inss, INS_Z80},
+ { ".z80n", set_inss, INS_Z80N},
{ "db" , emit_data, 1},
{ "d24", z80_cons, 3},
{ "d32", z80_cons, 4},
@@ -3152,6 +3439,11 @@ static table_t instab[] =
{ "add", 0x80, 0x09, emit_add, INS_ALL },
{ "and", 0x00, 0xA0, emit_s, INS_ALL },
{ "bit", 0xCB, 0x40, emit_bit, INS_ALL },
+ { "brlc", 0xED, 0x2C, emit_bshft,INS_Z80N },
+ { "bsla", 0xED, 0x28, emit_bshft,INS_Z80N },
+ { "bsra", 0xED, 0x29, emit_bshft,INS_Z80N },
+ { "bsrf", 0xED, 0x2B, emit_bshft,INS_Z80N },
+ { "bsrl", 0xED, 0x2A, emit_bshft,INS_Z80N },
{ "call", 0xCD, 0xC4, emit_jpcc, INS_ALL },
{ "ccf", 0x00, 0x3F, emit_insn, INS_ALL },
{ "cp", 0x00, 0xB8, emit_s, INS_ALL },
@@ -3191,15 +3483,24 @@ static table_t instab[] =
{ "ld", 0x00, 0x00, emit_ld, INS_ALL },
{ "ldd", 0xED, 0xA8, emit_lddldi,INS_ALL }, /* GBZ80 has special meaning */
{ "lddr", 0xED, 0xB8, emit_insn, INS_NOT_GBZ80 },
+ { "lddrx",0xED, 0xBC, emit_insn, INS_Z80N },
+ { "lddx", 0xED, 0xAC, emit_insn, INS_Z80N },
{ "ldh", 0xE0, 0x00, emit_ldh, INS_GBZ80 },
- { "ldhl", 0xE0, 0x00, emit_ldh, INS_GBZ80 },
+ { "ldhl", 0x00, 0xF8, emit_ldhl, INS_GBZ80 },
{ "ldi", 0xED, 0xA0, emit_lddldi,INS_ALL }, /* GBZ80 has special meaning */
{ "ldir", 0xED, 0xB0, emit_insn, INS_NOT_GBZ80 },
+ { "ldirx",0xED, 0xB4, emit_insn, INS_Z80N },
+ { "ldix", 0xED, 0xA4, emit_insn, INS_Z80N },
+ { "ldpirx",0xED,0xB7, emit_insn, INS_Z80N },
+ { "ldws", 0xED, 0xA5, emit_insn, INS_Z80N },
{ "lea", 0xED, 0x02, emit_lea, INS_EZ80 },
- { "mlt", 0xED, 0x4C, emit_mlt, INS_Z180|INS_EZ80 },
+ { "mirror",0xED,0x24, emit_insn, INS_Z80N },
+ { "mlt", 0xED, 0x4C, emit_mlt, INS_Z180|INS_EZ80|INS_Z80N },
+ { "mul", 0xED, 0x30, emit_mul, INS_Z80N },
{ "mulub",0xED, 0xC5, emit_mulub,INS_R800 },
{ "muluw",0xED, 0xC3, emit_muluw,INS_R800 },
- { "neg", 0xed, 0x44, emit_insn, INS_NOT_GBZ80 },
+ { "neg", 0xED, 0x44, emit_insn, INS_NOT_GBZ80 },
+ { "nextreg",0xED,0x91,emit_nextreg,INS_Z80N },
{ "nop", 0x00, 0x00, emit_insn, INS_ALL },
{ "or", 0x00, 0xB0, emit_s, INS_ALL },
{ "otd2r",0xED, 0xBC, emit_insn, INS_EZ80 },
@@ -3218,9 +3519,12 @@ static table_t instab[] =
{ "outd2",0xED, 0xAC, emit_insn, INS_EZ80 },
{ "outi", 0xED, 0xA3, emit_insn, INS_NOT_GBZ80 },
{ "outi2",0xED, 0xA4, emit_insn, INS_EZ80 },
+ { "outinb",0xED,0x90, emit_insn, INS_Z80N },
{ "pea", 0xED, 0x65, emit_pea, INS_EZ80 },
+ { "pixelad",0xED,0x94,emit_insn, INS_Z80N },
+ { "pixeldn",0xED,0x93,emit_insn, INS_Z80N },
{ "pop", 0x00, 0xC1, emit_pop, INS_ALL },
- { "push", 0x00, 0xC5, emit_pop, INS_ALL },
+ { "push", 0x00, 0xC5, emit_push, INS_ALL },
{ "res", 0xCB, 0x80, emit_bit, INS_ALL },
{ "ret", 0xC9, 0xC0, emit_retcc,INS_ALL },
{ "reti", 0xED, 0x4D, emit_reti, INS_ALL }, /*GBZ80 has its own opcode for it*/
@@ -3240,6 +3544,8 @@ static table_t instab[] =
{ "sbc", 0x98, 0x42, emit_adc, INS_ALL },
{ "scf", 0x00, 0x37, emit_insn, INS_ALL },
{ "set", 0xCB, 0xC0, emit_bit, INS_ALL },
+ { "setae",0xED, 0x95, emit_insn, INS_Z80N },
+ { "sl1", 0xCB, 0x30, emit_mr, INS_SLI },
{ "sla", 0xCB, 0x20, emit_mr, INS_ALL },
{ "sli", 0xCB, 0x30, emit_mr, INS_SLI },
{ "sll", 0xCB, 0x30, emit_mr, INS_SLI },
@@ -3248,10 +3554,12 @@ static table_t instab[] =
{ "srl", 0xCB, 0x38, emit_mr, INS_ALL },
{ "stmix",0xED, 0x7D, emit_insn, INS_EZ80 },
{ "stop", 0x00, 0x10, emit_insn, INS_GBZ80 },
- { "sub", 0x00, 0x90, emit_s, INS_ALL },
- { "swap", 0xCB, 0x30, emit_mr, INS_GBZ80 },
- { "tst", 0xED, 0x04, emit_tst, INS_Z180|INS_EZ80 },
- { "tstio",0xED, 0x74, emit_tstio,INS_Z180|INS_EZ80 },
+ { "sub", 0x00, 0x90, emit_sub, INS_ALL },
+ { "swap", 0xCB, 0x30, emit_swap, INS_GBZ80|INS_Z80N },
+ { "swapnib",0xED,0x23,emit_insn, INS_Z80N },
+ { "test", 0xED, 0x27, emit_insn_n, INS_Z80N },
+ { "tst", 0xED, 0x04, emit_tst, INS_Z180|INS_EZ80|INS_Z80N },
+ { "tstio",0xED, 0x74, emit_insn_n,INS_Z180|INS_EZ80 },
{ "xor", 0x00, 0xA8, emit_s, INS_ALL },
} ;
@@ -3294,139 +3602,146 @@ md_assemble (char *str)
insp = bsearch (&key, instab, ARRAY_SIZE (instab),
sizeof (instab[0]), key_cmp);
if (!insp || (insp->inss && !(insp->inss & ins_ok)))
- {
- as_bad (_("Unknown instruction '%s'"), buf);
- *frag_more (1) = 0;
- }
+ {
+ *frag_more (1) = 0;
+ as_bad (_("Unknown instruction `%s'"), buf);
+ }
else
{
p = insp->fp (insp->prefix, insp->opcode, p);
p = skip_space (p);
- if ((!err_flag) && *p)
- as_bad (_("junk at end of line, first unrecognized character is `%c'"),
- *p);
+ if ((!err_flag) && *p)
+ as_bad (_("junk at end of line, "
+ "first unrecognized character is `%c'"), *p);
}
}
end:
input_line_pointer = old_ptr;
}
+static int
+is_overflow (long value, unsigned bitsize)
+{
+ long fieldmask = (1 << bitsize) - 1;
+ long signmask = ~fieldmask;
+ long a = value & fieldmask;
+ long ss = a & signmask;
+ if (ss != 0 && ss != (signmask & fieldmask))
+ return 1;
+ return 0;
+}
+
void
-md_apply_fix (fixS * fixP, valueT* valP, segT seg ATTRIBUTE_UNUSED)
+md_apply_fix (fixS * fixP, valueT* valP, segT seg)
{
- long val = * (long *) valP;
+ long val = *valP;
char *p_lit = fixP->fx_where + fixP->fx_frag->fr_literal;
+ if (fixP->fx_addsy == NULL)
+ fixP->fx_done = 1;
+ else if (fixP->fx_pcrel)
+ {
+ segT s = S_GET_SEGMENT (fixP->fx_addsy);
+ if (s == seg || s == absolute_section)
+ {
+ val += S_GET_VALUE (fixP->fx_addsy);
+ fixP->fx_done = 1;
+ }
+ }
+
switch (fixP->fx_r_type)
{
case BFD_RELOC_8_PCREL:
- if (fixP->fx_addsy)
- {
- fixP->fx_no_overflow = 1;
- fixP->fx_done = 0;
- }
- else
- {
- fixP->fx_no_overflow = (-128 <= val && val < 128);
- if (!fixP->fx_no_overflow)
- as_bad_where (fixP->fx_file, fixP->fx_line,
- _("relative jump out of range"));
- *p_lit++ = val;
- fixP->fx_done = 1;
- }
+ case BFD_RELOC_Z80_DISP8:
+ case BFD_RELOC_8:
+ case BFD_RELOC_16:
+ case BFD_RELOC_24:
+ case BFD_RELOC_32:
+ case BFD_RELOC_Z80_16_BE:
+ fixP->fx_no_overflow = 0;
+ break;
+ default:
+ fixP->fx_no_overflow = 1;
break;
+ }
+ switch (fixP->fx_r_type)
+ {
+ case BFD_RELOC_8_PCREL:
case BFD_RELOC_Z80_DISP8:
- if (fixP->fx_addsy)
- {
- fixP->fx_no_overflow = 1;
- fixP->fx_done = 0;
- }
- else
- {
- fixP->fx_no_overflow = (-128 <= val && val < 128);
- if (!fixP->fx_no_overflow)
- as_bad_where (fixP->fx_file, fixP->fx_line,
- _("index offset out of range"));
- *p_lit++ = val;
- fixP->fx_done = 1;
- }
+ if (fixP->fx_done && (val < -0x80 || val > 0x7f))
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ _("8-bit signed offset out of range (%+ld)"), val);
+ *p_lit++ = val;
break;
case BFD_RELOC_Z80_BYTE0:
*p_lit++ = val;
- fixP->fx_no_overflow = 1;
- if (fixP->fx_addsy == NULL)
- fixP->fx_done = 1;
break;
case BFD_RELOC_Z80_BYTE1:
*p_lit++ = (val >> 8);
- fixP->fx_no_overflow = 1;
- if (fixP->fx_addsy == NULL)
- fixP->fx_done = 1;
break;
case BFD_RELOC_Z80_BYTE2:
*p_lit++ = (val >> 16);
- fixP->fx_no_overflow = 1;
- if (fixP->fx_addsy == NULL)
- fixP->fx_done = 1;
break;
case BFD_RELOC_Z80_BYTE3:
*p_lit++ = (val >> 24);
- fixP->fx_no_overflow = 1;
- if (fixP->fx_addsy == NULL)
- fixP->fx_done = 1;
break;
case BFD_RELOC_8:
- if (val > 255 || val < -128)
- as_warn_where (fixP->fx_file, fixP->fx_line, _("overflow"));
+ if (fixP->fx_done && is_overflow(val, 8))
+ as_warn_where (fixP->fx_file, fixP->fx_line,
+ _("8-bit overflow (%+ld)"), val);
*p_lit++ = val;
- fixP->fx_no_overflow = 1;
- if (fixP->fx_addsy == NULL)
- fixP->fx_done = 1;
break;
case BFD_RELOC_Z80_WORD1:
*p_lit++ = (val >> 16);
*p_lit++ = (val >> 24);
- fixP->fx_no_overflow = 1;
- if (fixP->fx_addsy == NULL)
- fixP->fx_done = 1;
break;
case BFD_RELOC_Z80_WORD0:
+ *p_lit++ = val;
+ *p_lit++ = (val >> 8);
+ break;
+
case BFD_RELOC_16:
+ if (fixP->fx_done && is_overflow(val, 16))
+ as_warn_where (fixP->fx_file, fixP->fx_line,
+ _("16-bit overflow (%+ld)"), val);
*p_lit++ = val;
*p_lit++ = (val >> 8);
- fixP->fx_no_overflow = 1;
- if (fixP->fx_addsy == NULL)
- fixP->fx_done = 1;
break;
case BFD_RELOC_24: /* Def24 may produce this. */
+ if (fixP->fx_done && is_overflow(val, 24))
+ as_warn_where (fixP->fx_file, fixP->fx_line,
+ _("24-bit overflow (%+ld)"), val);
*p_lit++ = val;
*p_lit++ = (val >> 8);
*p_lit++ = (val >> 16);
- fixP->fx_no_overflow = 1;
- if (fixP->fx_addsy == NULL)
- fixP->fx_done = 1;
break;
case BFD_RELOC_32: /* Def32 and .long may produce this. */
+ if (fixP->fx_done && is_overflow(val, 32))
+ as_warn_where (fixP->fx_file, fixP->fx_line,
+ _("32-bit overflow (%+ld)"), val);
*p_lit++ = val;
*p_lit++ = (val >> 8);
*p_lit++ = (val >> 16);
*p_lit++ = (val >> 24);
- if (fixP->fx_addsy == NULL)
- fixP->fx_done = 1;
+ break;
+
+ case BFD_RELOC_Z80_16_BE: /* Z80N PUSH nn instruction produce this. */
+ *p_lit++ = val >> 8;
+ *p_lit++ = val;
break;
default:
- printf (_("md_apply_fix: unknown r_type 0x%x\n"), fixP->fx_r_type);
+ printf (_("md_apply_fix: unknown reloc type 0x%x\n"), fixP->fx_r_type);
abort ();
}
}
@@ -3446,11 +3761,9 @@ tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED , fixS *fixp)
{
arelent *reloc;
- if (! bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type))
+ if (fixp->fx_subsy != NULL)
{
- as_bad_where (fixp->fx_file, fixp->fx_line,
- _("reloc %d not supported by object file format"),
- (int) fixp->fx_r_type);
+ as_bad_where (fixp->fx_file, fixp->fx_line, _("expression too complex"));
return NULL;
}
@@ -3458,8 +3771,19 @@ tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED , fixS *fixp)
reloc->sym_ptr_ptr = XNEW (asymbol *);
*reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
- reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
reloc->addend = fixp->fx_offset;
+ reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
+ if (reloc->howto == NULL)
+ {
+ as_bad_where (fixp->fx_file, fixp->fx_line,
+ _("reloc %d not supported by object file format"),
+ (int) fixp->fx_r_type);
+ return NULL;
+ }
+
+ if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
+ || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
+ reloc->address = fixp->fx_offset;
return reloc;
}
@@ -3712,3 +4036,49 @@ str_to_ieee754_d(char *litP, int *sizeP)
{
return ieee_md_atof ('d', litP, sizeP, FALSE);
}
+
+#ifdef TARGET_USE_CFIPOP
+/* Initialize the DWARF-2 unwind information for this procedure. */
+void
+z80_tc_frame_initial_instructions (void)
+{
+ static int sp_regno = -1;
+
+ if (sp_regno < 0)
+ sp_regno = z80_tc_regname_to_dw2regnum ("sp");
+
+ cfi_add_CFA_def_cfa (sp_regno, 0);
+}
+
+int
+z80_tc_regname_to_dw2regnum (const char *regname)
+{
+ static const char *regs[] =
+ { /* same registers as for GDB */
+ "af", "bc", "de", "hl",
+ "sp", "pc", "ix", "iy",
+ "af_", "bc_", "de_", "hl_",
+ "ir"
+ };
+ unsigned i;
+
+ for (i = 0; i < ARRAY_SIZE(regs); ++i)
+ if (!strcasecmp (regs[i], regname))
+ return i;
+
+ return -1;
+}
+#endif
+
+/* Implement DWARF2_ADDR_SIZE. */
+int
+z80_dwarf2_addr_size (const bfd *abfd)
+{
+ switch (bfd_get_mach (abfd))
+ {
+ case bfd_mach_ez80_adl:
+ return 3;
+ default:
+ return 2;
+ }
+}
diff --git a/gas/config/tc-z80.h b/gas/config/tc-z80.h
index 5749027..d169d09 100644
--- a/gas/config/tc-z80.h
+++ b/gas/config/tc-z80.h
@@ -29,7 +29,6 @@
#endif
#define BFD_ARCH TARGET_ARCH
#define COFF_MAGIC 0x5A80
-#define TARGET_MACH 0
#define TARGET_BYTES_BIG_ENDIAN 0
/* If you define this macro, GAS will warn about the
@@ -116,4 +115,24 @@ extern int z80_tc_label_is_local (const char *name);
#define elf_tc_final_processing z80_elf_final_processing
extern void z80_elf_final_processing (void);
+/* Define the column that represents the PC. */
+#define DWARF2_DEFAULT_RETURN_COLUMN 5
+
+/* The stack grows down, and is only byte aligned. */
+#define DWARF2_CIE_DATA_ALIGNMENT -1
+
+/* Z80 instructions are 1 or 4 bytes long. */
+#define DWARF2_LINE_MIN_INSN_LENGTH 1
+
+/* 16 bits addresses are used on Z80. */
+#define DWARF2_ADDR_SIZE(bfd) z80_dwarf2_addr_size(bfd)
+extern int z80_dwarf2_addr_size (const bfd *abfd);
+
+/* CFI hooks. */
+#define tc_cfi_frame_initial_instructions z80_tc_frame_initial_instructions
+extern void z80_tc_frame_initial_instructions (void);
+
+#define tc_regname_to_dw2regnum z80_tc_regname_to_dw2regnum
+extern int z80_tc_regname_to_dw2regnum (const char *regname);
+
#endif
diff --git a/gas/doc/c-z80.texi b/gas/doc/c-z80.texi
index dd6332d..e768e38 100644
--- a/gas/doc/c-z80.texi
+++ b/gas/doc/c-z80.texi
@@ -31,19 +31,19 @@
@table @gcctabopt
@cindex @code{-z80} command-line option, Z80
@item -z80
-Produce code for the Z80 processor. By default accepted undocumented
-operations with halves of index registers (@code{IXL}, @code{IXH}, @code{IYL}, @code{IYH}) and
-instuction @code{IN F,(C)}. Other useful undocumented instructions produces
-warnings. Undocumented instructions may not work on some CPUs, use
-them on your own risk.
+Produce code for the Zilog Z80 processor. By default accepted undocumented
+operations with halves of index registers (@code{IXL}, @code{IXH}, @code{IYL},
+@code{IYH}) and instuction @code{IN F,(C)}. Other useful undocumented
+instructions produces warnings. Undocumented instructions may not work on some
+CPUs, use them on your own risk.
@cindex @code{-r800} command-line option, Z80
@item -r800
-Produce code for the R800 processor.
+Produce code for the Ascii R800 processor.
@cindex @code{-z180} command-line option, Z80
@item -z180
-Produce code for the Z180 processor.
+Produce code for the Zilog Z180 processor.
@cindex @code{-ez80} command-line option, Z80
@item -ez80
@@ -53,6 +53,14 @@ Produce code for the eZ80 processor in Z80 memory mode by default.
@item -ez80-adl
Produce code for the eZ80 processor in ADL memory mode by default.
+@cindex @code{-gbz80} command-line option, Z80
+@item -gbz80
+Produce code for the GameBoy Z80 processor.
+
+@cindex @code{-z80n} command-line option, Z80
+@item -z80n
+Produce code for the Z80N processor.
+
@cindex @code{-local-prefix} command-line option, Z80
@item -local-prefix=@var{prefix}
Mark all labels with specified prefix as local. But such label can be
diff --git a/gas/testsuite/gas/z80/gbz80_all.d b/gas/testsuite/gas/z80/gbz80_all.d
new file mode 100644
index 0000000..0bb5db0
--- /dev/null
+++ b/gas/testsuite/gas/z80/gbz80_all.d
@@ -0,0 +1,514 @@
+#as: -gbz80
+#objdump: -d
+#name: GBZ80 instruction set
+
+.*: .*
+
+Disassembly of section .text:
+
+0+ <.text>:
+\s+[0-9a-f]+:\s+00\s+nop
+\s+[0-9a-f]+:\s+01 af be\s+ld bc,0xbeaf
+\s+[0-9a-f]+:\s+02\s+ld \(bc\),a
+\s+[0-9a-f]+:\s+03\s+inc bc
+\s+[0-9a-f]+:\s+04\s+inc b
+\s+[0-9a-f]+:\s+05\s+dec b
+\s+[0-9a-f]+:\s+06 fd\s+ld b,0xfd
+\s+[0-9a-f]+:\s+07\s+rlca
+\s+[0-9a-f]+:\s+08 af be\s+ld \(0xbeaf\),sp
+\s+[0-9a-f]+:\s+09\s+add hl,bc
+\s+[0-9a-f]+:\s+0a\s+ld a,\(bc\)
+\s+[0-9a-f]+:\s+0b\s+dec bc
+\s+[0-9a-f]+:\s+0c\s+inc c
+\s+[0-9a-f]+:\s+0d\s+dec c
+\s+[0-9a-f]+:\s+0e fd\s+ld c,0xfd
+\s+[0-9a-f]+:\s+0f\s+rrca
+\s+[0-9a-f]+:\s+10\s+stop
+\s+[0-9a-f]+:\s+11 af be\s+ld de,0xbeaf
+\s+[0-9a-f]+:\s+12\s+ld \(de\),a
+\s+[0-9a-f]+:\s+13\s+inc de
+\s+[0-9a-f]+:\s+14\s+inc d
+\s+[0-9a-f]+:\s+15\s+dec d
+\s+[0-9a-f]+:\s+16 fd\s+ld d,0xfd
+\s+[0-9a-f]+:\s+17\s+rla
+\s+[0-9a-f]+:\s+18 0a\s+jr 0x002d
+\s+[0-9a-f]+:\s+19\s+add hl,de
+\s+[0-9a-f]+:\s+1a\s+ld a,\(de\)
+\s+[0-9a-f]+:\s+1b\s+dec de
+\s+[0-9a-f]+:\s+1c\s+inc e
+\s+[0-9a-f]+:\s+1d\s+dec e
+\s+[0-9a-f]+:\s+1e fd\s+ld e,0xfd
+\s+[0-9a-f]+:\s+1f\s+rra
+\s+[0-9a-f]+:\s+20 0a\s+jr nz,0x0037
+\s+[0-9a-f]+:\s+21 af be\s+ld hl,0xbeaf
+\s+[0-9a-f]+:\s+22\s+ld \(hl\+\),a
+\s+[0-9a-f]+:\s+22\s+ld \(hl\+\),a
+\s+[0-9a-f]+:\s+23\s+inc hl
+\s+[0-9a-f]+:\s+24\s+inc h
+\s+[0-9a-f]+:\s+25\s+dec h
+\s+[0-9a-f]+:\s+26 fd\s+ld h,0xfd
+\s+[0-9a-f]+:\s+27\s+daa
+\s+[0-9a-f]+:\s+28 0a\s+jr z,0x0044
+\s+[0-9a-f]+:\s+29\s+add hl,hl
+\s+[0-9a-f]+:\s+2a\s+ld a,\(hl\+\)
+\s+[0-9a-f]+:\s+2a\s+ld a,\(hl\+\)
+\s+[0-9a-f]+:\s+2b\s+dec hl
+\s+[0-9a-f]+:\s+2c\s+inc l
+\s+[0-9a-f]+:\s+2d\s+dec l
+\s+[0-9a-f]+:\s+2e fd\s+ld l,0xfd
+\s+[0-9a-f]+:\s+2f\s+cpl
+\s+[0-9a-f]+:\s+30 0a\s+jr nc,0x004f
+\s+[0-9a-f]+:\s+31 af be\s+ld sp,0xbeaf
+\s+[0-9a-f]+:\s+32\s+ld \(hl-\),a
+\s+[0-9a-f]+:\s+32\s+ld \(hl-\),a
+\s+[0-9a-f]+:\s+33\s+inc sp
+\s+[0-9a-f]+:\s+34\s+inc \(hl\)
+\s+[0-9a-f]+:\s+35\s+dec \(hl\)
+\s+[0-9a-f]+:\s+36 fd\s+ld \(hl\),0xfd
+\s+[0-9a-f]+:\s+37\s+scf
+\s+[0-9a-f]+:\s+38 0a\s+jr c,0x005c
+\s+[0-9a-f]+:\s+39\s+add hl,sp
+\s+[0-9a-f]+:\s+3a\s+ld a,\(hl-\)
+\s+[0-9a-f]+:\s+3a\s+ld a,\(hl-\)
+\s+[0-9a-f]+:\s+3b\s+dec sp
+\s+[0-9a-f]+:\s+3c\s+inc a
+\s+[0-9a-f]+:\s+3d\s+dec a
+\s+[0-9a-f]+:\s+3e fd\s+ld a,0xfd
+\s+[0-9a-f]+:\s+3f\s+ccf
+\s+[0-9a-f]+:\s+40\s+ld b,b
+\s+[0-9a-f]+:\s+41\s+ld b,c
+\s+[0-9a-f]+:\s+42\s+ld b,d
+\s+[0-9a-f]+:\s+43\s+ld b,e
+\s+[0-9a-f]+:\s+44\s+ld b,h
+\s+[0-9a-f]+:\s+45\s+ld b,l
+\s+[0-9a-f]+:\s+46\s+ld b,\(hl\)
+\s+[0-9a-f]+:\s+47\s+ld b,a
+\s+[0-9a-f]+:\s+48\s+ld c,b
+\s+[0-9a-f]+:\s+49\s+ld c,c
+\s+[0-9a-f]+:\s+4a\s+ld c,d
+\s+[0-9a-f]+:\s+4b\s+ld c,e
+\s+[0-9a-f]+:\s+4c\s+ld c,h
+\s+[0-9a-f]+:\s+4d\s+ld c,l
+\s+[0-9a-f]+:\s+4e\s+ld c,\(hl\)
+\s+[0-9a-f]+:\s+4f\s+ld c,a
+\s+[0-9a-f]+:\s+50\s+ld d,b
+\s+[0-9a-f]+:\s+51\s+ld d,c
+\s+[0-9a-f]+:\s+52\s+ld d,d
+\s+[0-9a-f]+:\s+53\s+ld d,e
+\s+[0-9a-f]+:\s+54\s+ld d,h
+\s+[0-9a-f]+:\s+55\s+ld d,l
+\s+[0-9a-f]+:\s+56\s+ld d,\(hl\)
+\s+[0-9a-f]+:\s+57\s+ld d,a
+\s+[0-9a-f]+:\s+58\s+ld e,b
+\s+[0-9a-f]+:\s+59\s+ld e,c
+\s+[0-9a-f]+:\s+5a\s+ld e,d
+\s+[0-9a-f]+:\s+5b\s+ld e,e
+\s+[0-9a-f]+:\s+5c\s+ld e,h
+\s+[0-9a-f]+:\s+5d\s+ld e,l
+\s+[0-9a-f]+:\s+5e\s+ld e,\(hl\)
+\s+[0-9a-f]+:\s+5f\s+ld e,a
+\s+[0-9a-f]+:\s+60\s+ld h,b
+\s+[0-9a-f]+:\s+61\s+ld h,c
+\s+[0-9a-f]+:\s+62\s+ld h,d
+\s+[0-9a-f]+:\s+63\s+ld h,e
+\s+[0-9a-f]+:\s+64\s+ld h,h
+\s+[0-9a-f]+:\s+65\s+ld h,l
+\s+[0-9a-f]+:\s+66\s+ld h,\(hl\)
+\s+[0-9a-f]+:\s+67\s+ld h,a
+\s+[0-9a-f]+:\s+68\s+ld l,b
+\s+[0-9a-f]+:\s+69\s+ld l,c
+\s+[0-9a-f]+:\s+6a\s+ld l,d
+\s+[0-9a-f]+:\s+6b\s+ld l,e
+\s+[0-9a-f]+:\s+6c\s+ld l,h
+\s+[0-9a-f]+:\s+6d\s+ld l,l
+\s+[0-9a-f]+:\s+6e\s+ld l,\(hl\)
+\s+[0-9a-f]+:\s+6f\s+ld l,a
+\s+[0-9a-f]+:\s+70\s+ld \(hl\),b
+\s+[0-9a-f]+:\s+71\s+ld \(hl\),c
+\s+[0-9a-f]+:\s+72\s+ld \(hl\),d
+\s+[0-9a-f]+:\s+73\s+ld \(hl\),e
+\s+[0-9a-f]+:\s+74\s+ld \(hl\),h
+\s+[0-9a-f]+:\s+75\s+ld \(hl\),l
+\s+[0-9a-f]+:\s+76\s+halt
+\s+[0-9a-f]+:\s+77\s+ld \(hl\),a
+\s+[0-9a-f]+:\s+78\s+ld a,b
+\s+[0-9a-f]+:\s+79\s+ld a,c
+\s+[0-9a-f]+:\s+7a\s+ld a,d
+\s+[0-9a-f]+:\s+7b\s+ld a,e
+\s+[0-9a-f]+:\s+7c\s+ld a,h
+\s+[0-9a-f]+:\s+7d\s+ld a,l
+\s+[0-9a-f]+:\s+7e\s+ld a,\(hl\)
+\s+[0-9a-f]+:\s+7f\s+ld a,a
+\s+[0-9a-f]+:\s+80\s+add a,b
+\s+[0-9a-f]+:\s+81\s+add a,c
+\s+[0-9a-f]+:\s+82\s+add a,d
+\s+[0-9a-f]+:\s+83\s+add a,e
+\s+[0-9a-f]+:\s+84\s+add a,h
+\s+[0-9a-f]+:\s+85\s+add a,l
+\s+[0-9a-f]+:\s+86\s+add a,\(hl\)
+\s+[0-9a-f]+:\s+87\s+add a,a
+\s+[0-9a-f]+:\s+88\s+adc a,b
+\s+[0-9a-f]+:\s+89\s+adc a,c
+\s+[0-9a-f]+:\s+8a\s+adc a,d
+\s+[0-9a-f]+:\s+8b\s+adc a,e
+\s+[0-9a-f]+:\s+8c\s+adc a,h
+\s+[0-9a-f]+:\s+8d\s+adc a,l
+\s+[0-9a-f]+:\s+8e\s+adc a,\(hl\)
+\s+[0-9a-f]+:\s+8f\s+adc a,a
+\s+[0-9a-f]+:\s+90\s+sub a,b
+\s+[0-9a-f]+:\s+91\s+sub a,c
+\s+[0-9a-f]+:\s+92\s+sub a,d
+\s+[0-9a-f]+:\s+93\s+sub a,e
+\s+[0-9a-f]+:\s+94\s+sub a,h
+\s+[0-9a-f]+:\s+95\s+sub a,l
+\s+[0-9a-f]+:\s+96\s+sub a,\(hl\)
+\s+[0-9a-f]+:\s+97\s+sub a,a
+\s+[0-9a-f]+:\s+98\s+sbc a,b
+\s+[0-9a-f]+:\s+99\s+sbc a,c
+\s+[0-9a-f]+:\s+9a\s+sbc a,d
+\s+[0-9a-f]+:\s+9b\s+sbc a,e
+\s+[0-9a-f]+:\s+9c\s+sbc a,h
+\s+[0-9a-f]+:\s+9d\s+sbc a,l
+\s+[0-9a-f]+:\s+9e\s+sbc a,\(hl\)
+\s+[0-9a-f]+:\s+9f\s+sbc a,a
+\s+[0-9a-f]+:\s+a0\s+and b
+\s+[0-9a-f]+:\s+a1\s+and c
+\s+[0-9a-f]+:\s+a2\s+and d
+\s+[0-9a-f]+:\s+a3\s+and e
+\s+[0-9a-f]+:\s+a4\s+and h
+\s+[0-9a-f]+:\s+a5\s+and l
+\s+[0-9a-f]+:\s+a6\s+and \(hl\)
+\s+[0-9a-f]+:\s+a7\s+and a
+\s+[0-9a-f]+:\s+a8\s+xor b
+\s+[0-9a-f]+:\s+a9\s+xor c
+\s+[0-9a-f]+:\s+aa\s+xor d
+\s+[0-9a-f]+:\s+ab\s+xor e
+\s+[0-9a-f]+:\s+ac\s+xor h
+\s+[0-9a-f]+:\s+ad\s+xor l
+\s+[0-9a-f]+:\s+ae\s+xor \(hl\)
+\s+[0-9a-f]+:\s+af\s+xor a
+\s+[0-9a-f]+:\s+b0\s+or b
+\s+[0-9a-f]+:\s+b1\s+or c
+\s+[0-9a-f]+:\s+b2\s+or d
+\s+[0-9a-f]+:\s+b3\s+or e
+\s+[0-9a-f]+:\s+b4\s+or h
+\s+[0-9a-f]+:\s+b5\s+or l
+\s+[0-9a-f]+:\s+b6\s+or \(hl\)
+\s+[0-9a-f]+:\s+b7\s+or a
+\s+[0-9a-f]+:\s+b8\s+cp b
+\s+[0-9a-f]+:\s+b9\s+cp c
+\s+[0-9a-f]+:\s+ba\s+cp d
+\s+[0-9a-f]+:\s+bb\s+cp e
+\s+[0-9a-f]+:\s+bc\s+cp h
+\s+[0-9a-f]+:\s+bd\s+cp l
+\s+[0-9a-f]+:\s+be\s+cp \(hl\)
+\s+[0-9a-f]+:\s+bf\s+cp a
+\s+[0-9a-f]+:\s+c0\s+ret nz
+\s+[0-9a-f]+:\s+c1\s+pop bc
+\s+[0-9a-f]+:\s+c2 af be\s+jp nz,0xbeaf
+\s+[0-9a-f]+:\s+c3 af be\s+jp 0xbeaf
+\s+[0-9a-f]+:\s+c4 af be\s+call nz,0xbeaf
+\s+[0-9a-f]+:\s+c5\s+push bc
+\s+[0-9a-f]+:\s+c6 fd\s+add a,0xfd
+\s+[0-9a-f]+:\s+c7\s+rst 0x00
+\s+[0-9a-f]+:\s+c8\s+ret z
+\s+[0-9a-f]+:\s+c9\s+ret
+\s+[0-9a-f]+:\s+ca af be\s+jp z,0xbeaf
+\s+[0-9a-f]+:\s+00\s+nop
+\s+[0-9a-f]+:\s+cc af be\s+call z,0xbeaf
+\s+[0-9a-f]+:\s+cd af be\s+call 0xbeaf
+\s+[0-9a-f]+:\s+ce fd\s+adc a,0xfd
+\s+[0-9a-f]+:\s+cf\s+rst 0x08
+\s+[0-9a-f]+:\s+d0\s+ret nc
+\s+[0-9a-f]+:\s+d1\s+pop de
+\s+[0-9a-f]+:\s+d2 af be\s+jp nc,0xbeaf
+\s+[0-9a-f]+:\s+d4 af be\s+call nc,0xbeaf
+\s+[0-9a-f]+:\s+d5\s+push de
+\s+[0-9a-f]+:\s+d6 fd\s+sub a,0xfd
+\s+[0-9a-f]+:\s+d7\s+rst 0x10
+\s+[0-9a-f]+:\s+d8\s+ret c
+\s+[0-9a-f]+:\s+d9\s+reti
+\s+[0-9a-f]+:\s+da af be\s+jp c,0xbeaf
+\s+[0-9a-f]+:\s+dc af be\s+call c,0xbeaf
+\s+[0-9a-f]+:\s+de fd\s+sbc a,0xfd
+\s+[0-9a-f]+:\s+df\s+rst 0x18
+\s+[0-9a-f]+:\s+e0 fd\s+ldh \(0xfd\),a
+\s+[0-9a-f]+:\s+e1\s+pop hl
+\s+[0-9a-f]+:\s+e2\s+ldh \(c\),a
+\s+[0-9a-f]+:\s+e5\s+push hl
+\s+[0-9a-f]+:\s+e6 fd\s+and 0xfd
+\s+[0-9a-f]+:\s+e7\s+rst 0x20
+\s+[0-9a-f]+:\s+e8 f4\s+add sp,-12
+\s+[0-9a-f]+:\s+e9\s+jp \(hl\)
+\s+[0-9a-f]+:\s+ea af be\s+ld \(0xbeaf\),a
+\s+[0-9a-f]+:\s+ee fd\s+xor 0xfd
+\s+[0-9a-f]+:\s+ef\s+rst 0x28
+\s+[0-9a-f]+:\s+f0 fd\s+ldh a,\(0xfd\)
+\s+[0-9a-f]+:\s+f1\s+pop af
+\s+[0-9a-f]+:\s+f2\s+ldh a,\(c\)
+\s+[0-9a-f]+:\s+f3\s+di
+\s+[0-9a-f]+:\s+f5\s+push af
+\s+[0-9a-f]+:\s+f6 fd\s+or 0xfd
+\s+[0-9a-f]+:\s+f7\s+rst 0x30
+\s+[0-9a-f]+:\s+f8 f4\s+ldhl sp,-12
+\s+[0-9a-f]+:\s+f9\s+ld sp,hl
+\s+[0-9a-f]+:\s+fa af be\s+ld a,\(0xbeaf\)
+\s+[0-9a-f]+:\s+fb\s+ei
+\s+[0-9a-f]+:\s+fe fd\s+cp 0xfd
+\s+[0-9a-f]+:\s+ff\s+rst 0x38
+\s+[0-9a-f]+:\s+cb 00\s+rlc b
+\s+[0-9a-f]+:\s+cb 01\s+rlc c
+\s+[0-9a-f]+:\s+cb 02\s+rlc d
+\s+[0-9a-f]+:\s+cb 03\s+rlc e
+\s+[0-9a-f]+:\s+cb 04\s+rlc h
+\s+[0-9a-f]+:\s+cb 05\s+rlc l
+\s+[0-9a-f]+:\s+cb 06\s+rlc \(hl\)
+\s+[0-9a-f]+:\s+cb 07\s+rlc a
+\s+[0-9a-f]+:\s+cb 08\s+rrc b
+\s+[0-9a-f]+:\s+cb 09\s+rrc c
+\s+[0-9a-f]+:\s+cb 0a\s+rrc d
+\s+[0-9a-f]+:\s+cb 0b\s+rrc e
+\s+[0-9a-f]+:\s+cb 0c\s+rrc h
+\s+[0-9a-f]+:\s+cb 0d\s+rrc l
+\s+[0-9a-f]+:\s+cb 0e\s+rrc \(hl\)
+\s+[0-9a-f]+:\s+cb 0f\s+rrc a
+\s+[0-9a-f]+:\s+cb 10\s+rl b
+\s+[0-9a-f]+:\s+cb 11\s+rl c
+\s+[0-9a-f]+:\s+cb 12\s+rl d
+\s+[0-9a-f]+:\s+cb 13\s+rl e
+\s+[0-9a-f]+:\s+cb 14\s+rl h
+\s+[0-9a-f]+:\s+cb 15\s+rl l
+\s+[0-9a-f]+:\s+cb 16\s+rl \(hl\)
+\s+[0-9a-f]+:\s+cb 17\s+rl a
+\s+[0-9a-f]+:\s+cb 18\s+rr b
+\s+[0-9a-f]+:\s+cb 19\s+rr c
+\s+[0-9a-f]+:\s+cb 1a\s+rr d
+\s+[0-9a-f]+:\s+cb 1b\s+rr e
+\s+[0-9a-f]+:\s+cb 1c\s+rr h
+\s+[0-9a-f]+:\s+cb 1d\s+rr l
+\s+[0-9a-f]+:\s+cb 1e\s+rr \(hl\)
+\s+[0-9a-f]+:\s+cb 1f\s+rr a
+\s+[0-9a-f]+:\s+cb 20\s+sla b
+\s+[0-9a-f]+:\s+cb 21\s+sla c
+\s+[0-9a-f]+:\s+cb 22\s+sla d
+\s+[0-9a-f]+:\s+cb 23\s+sla e
+\s+[0-9a-f]+:\s+cb 24\s+sla h
+\s+[0-9a-f]+:\s+cb 25\s+sla l
+\s+[0-9a-f]+:\s+cb 26\s+sla \(hl\)
+\s+[0-9a-f]+:\s+cb 27\s+sla a
+\s+[0-9a-f]+:\s+cb 28\s+sra b
+\s+[0-9a-f]+:\s+cb 29\s+sra c
+\s+[0-9a-f]+:\s+cb 2a\s+sra d
+\s+[0-9a-f]+:\s+cb 2b\s+sra e
+\s+[0-9a-f]+:\s+cb 2c\s+sra h
+\s+[0-9a-f]+:\s+cb 2d\s+sra l
+\s+[0-9a-f]+:\s+cb 2e\s+sra \(hl\)
+\s+[0-9a-f]+:\s+cb 2f\s+sra a
+\s+[0-9a-f]+:\s+cb 30\s+swap b
+\s+[0-9a-f]+:\s+cb 31\s+swap c
+\s+[0-9a-f]+:\s+cb 32\s+swap d
+\s+[0-9a-f]+:\s+cb 33\s+swap e
+\s+[0-9a-f]+:\s+cb 34\s+swap h
+\s+[0-9a-f]+:\s+cb 35\s+swap l
+\s+[0-9a-f]+:\s+cb 36\s+swap \(hl\)
+\s+[0-9a-f]+:\s+cb 37\s+swap a
+\s+[0-9a-f]+:\s+cb 38\s+srl b
+\s+[0-9a-f]+:\s+cb 39\s+srl c
+\s+[0-9a-f]+:\s+cb 3a\s+srl d
+\s+[0-9a-f]+:\s+cb 3b\s+srl e
+\s+[0-9a-f]+:\s+cb 3c\s+srl h
+\s+[0-9a-f]+:\s+cb 3d\s+srl l
+\s+[0-9a-f]+:\s+cb 3e\s+srl \(hl\)
+\s+[0-9a-f]+:\s+cb 3f\s+srl a
+\s+[0-9a-f]+:\s+cb 40\s+bit 0,b
+\s+[0-9a-f]+:\s+cb 41\s+bit 0,c
+\s+[0-9a-f]+:\s+cb 42\s+bit 0,d
+\s+[0-9a-f]+:\s+cb 43\s+bit 0,e
+\s+[0-9a-f]+:\s+cb 44\s+bit 0,h
+\s+[0-9a-f]+:\s+cb 45\s+bit 0,l
+\s+[0-9a-f]+:\s+cb 46\s+bit 0,\(hl\)
+\s+[0-9a-f]+:\s+cb 47\s+bit 0,a
+\s+[0-9a-f]+:\s+cb 48\s+bit 1,b
+\s+[0-9a-f]+:\s+cb 49\s+bit 1,c
+\s+[0-9a-f]+:\s+cb 4a\s+bit 1,d
+\s+[0-9a-f]+:\s+cb 4b\s+bit 1,e
+\s+[0-9a-f]+:\s+cb 4c\s+bit 1,h
+\s+[0-9a-f]+:\s+cb 4d\s+bit 1,l
+\s+[0-9a-f]+:\s+cb 4e\s+bit 1,\(hl\)
+\s+[0-9a-f]+:\s+cb 4f\s+bit 1,a
+\s+[0-9a-f]+:\s+cb 50\s+bit 2,b
+\s+[0-9a-f]+:\s+cb 51\s+bit 2,c
+\s+[0-9a-f]+:\s+cb 52\s+bit 2,d
+\s+[0-9a-f]+:\s+cb 53\s+bit 2,e
+\s+[0-9a-f]+:\s+cb 54\s+bit 2,h
+\s+[0-9a-f]+:\s+cb 55\s+bit 2,l
+\s+[0-9a-f]+:\s+cb 56\s+bit 2,\(hl\)
+\s+[0-9a-f]+:\s+cb 57\s+bit 2,a
+\s+[0-9a-f]+:\s+cb 58\s+bit 3,b
+\s+[0-9a-f]+:\s+cb 59\s+bit 3,c
+\s+[0-9a-f]+:\s+cb 5a\s+bit 3,d
+\s+[0-9a-f]+:\s+cb 5b\s+bit 3,e
+\s+[0-9a-f]+:\s+cb 5c\s+bit 3,h
+\s+[0-9a-f]+:\s+cb 5d\s+bit 3,l
+\s+[0-9a-f]+:\s+cb 5e\s+bit 3,\(hl\)
+\s+[0-9a-f]+:\s+cb 5f\s+bit 3,a
+\s+[0-9a-f]+:\s+cb 60\s+bit 4,b
+\s+[0-9a-f]+:\s+cb 61\s+bit 4,c
+\s+[0-9a-f]+:\s+cb 62\s+bit 4,d
+\s+[0-9a-f]+:\s+cb 63\s+bit 4,e
+\s+[0-9a-f]+:\s+cb 64\s+bit 4,h
+\s+[0-9a-f]+:\s+cb 65\s+bit 4,l
+\s+[0-9a-f]+:\s+cb 66\s+bit 4,\(hl\)
+\s+[0-9a-f]+:\s+cb 67\s+bit 4,a
+\s+[0-9a-f]+:\s+cb 68\s+bit 5,b
+\s+[0-9a-f]+:\s+cb 69\s+bit 5,c
+\s+[0-9a-f]+:\s+cb 6a\s+bit 5,d
+\s+[0-9a-f]+:\s+cb 6b\s+bit 5,e
+\s+[0-9a-f]+:\s+cb 6c\s+bit 5,h
+\s+[0-9a-f]+:\s+cb 6d\s+bit 5,l
+\s+[0-9a-f]+:\s+cb 6e\s+bit 5,\(hl\)
+\s+[0-9a-f]+:\s+cb 6f\s+bit 5,a
+\s+[0-9a-f]+:\s+cb 70\s+bit 6,b
+\s+[0-9a-f]+:\s+cb 71\s+bit 6,c
+\s+[0-9a-f]+:\s+cb 72\s+bit 6,d
+\s+[0-9a-f]+:\s+cb 73\s+bit 6,e
+\s+[0-9a-f]+:\s+cb 74\s+bit 6,h
+\s+[0-9a-f]+:\s+cb 75\s+bit 6,l
+\s+[0-9a-f]+:\s+cb 76\s+bit 6,\(hl\)
+\s+[0-9a-f]+:\s+cb 77\s+bit 6,a
+\s+[0-9a-f]+:\s+cb 78\s+bit 7,b
+\s+[0-9a-f]+:\s+cb 79\s+bit 7,c
+\s+[0-9a-f]+:\s+cb 7a\s+bit 7,d
+\s+[0-9a-f]+:\s+cb 7b\s+bit 7,e
+\s+[0-9a-f]+:\s+cb 7c\s+bit 7,h
+\s+[0-9a-f]+:\s+cb 7d\s+bit 7,l
+\s+[0-9a-f]+:\s+cb 7e\s+bit 7,\(hl\)
+\s+[0-9a-f]+:\s+cb 7f\s+bit 7,a
+\s+[0-9a-f]+:\s+cb 80\s+res 0,b
+\s+[0-9a-f]+:\s+cb 81\s+res 0,c
+\s+[0-9a-f]+:\s+cb 82\s+res 0,d
+\s+[0-9a-f]+:\s+cb 83\s+res 0,e
+\s+[0-9a-f]+:\s+cb 84\s+res 0,h
+\s+[0-9a-f]+:\s+cb 85\s+res 0,l
+\s+[0-9a-f]+:\s+cb 86\s+res 0,\(hl\)
+\s+[0-9a-f]+:\s+cb 87\s+res 0,a
+\s+[0-9a-f]+:\s+cb 88\s+res 1,b
+\s+[0-9a-f]+:\s+cb 89\s+res 1,c
+\s+[0-9a-f]+:\s+cb 8a\s+res 1,d
+\s+[0-9a-f]+:\s+cb 8b\s+res 1,e
+\s+[0-9a-f]+:\s+cb 8c\s+res 1,h
+\s+[0-9a-f]+:\s+cb 8d\s+res 1,l
+\s+[0-9a-f]+:\s+cb 8e\s+res 1,\(hl\)
+\s+[0-9a-f]+:\s+cb 8f\s+res 1,a
+\s+[0-9a-f]+:\s+cb 90\s+res 2,b
+\s+[0-9a-f]+:\s+cb 91\s+res 2,c
+\s+[0-9a-f]+:\s+cb 92\s+res 2,d
+\s+[0-9a-f]+:\s+cb 93\s+res 2,e
+\s+[0-9a-f]+:\s+cb 94\s+res 2,h
+\s+[0-9a-f]+:\s+cb 95\s+res 2,l
+\s+[0-9a-f]+:\s+cb 96\s+res 2,\(hl\)
+\s+[0-9a-f]+:\s+cb 97\s+res 2,a
+\s+[0-9a-f]+:\s+cb 98\s+res 3,b
+\s+[0-9a-f]+:\s+cb 99\s+res 3,c
+\s+[0-9a-f]+:\s+cb 9a\s+res 3,d
+\s+[0-9a-f]+:\s+cb 9b\s+res 3,e
+\s+[0-9a-f]+:\s+cb 9c\s+res 3,h
+\s+[0-9a-f]+:\s+cb 9d\s+res 3,l
+\s+[0-9a-f]+:\s+cb 9e\s+res 3,\(hl\)
+\s+[0-9a-f]+:\s+cb 9f\s+res 3,a
+\s+[0-9a-f]+:\s+cb a0\s+res 4,b
+\s+[0-9a-f]+:\s+cb a1\s+res 4,c
+\s+[0-9a-f]+:\s+cb a2\s+res 4,d
+\s+[0-9a-f]+:\s+cb a3\s+res 4,e
+\s+[0-9a-f]+:\s+cb a4\s+res 4,h
+\s+[0-9a-f]+:\s+cb a5\s+res 4,l
+\s+[0-9a-f]+:\s+cb a6\s+res 4,\(hl\)
+\s+[0-9a-f]+:\s+cb a7\s+res 4,a
+\s+[0-9a-f]+:\s+cb a8\s+res 5,b
+\s+[0-9a-f]+:\s+cb a9\s+res 5,c
+\s+[0-9a-f]+:\s+cb aa\s+res 5,d
+\s+[0-9a-f]+:\s+cb ab\s+res 5,e
+\s+[0-9a-f]+:\s+cb ac\s+res 5,h
+\s+[0-9a-f]+:\s+cb ad\s+res 5,l
+\s+[0-9a-f]+:\s+cb ae\s+res 5,\(hl\)
+\s+[0-9a-f]+:\s+cb af\s+res 5,a
+\s+[0-9a-f]+:\s+cb b0\s+res 6,b
+\s+[0-9a-f]+:\s+cb b1\s+res 6,c
+\s+[0-9a-f]+:\s+cb b2\s+res 6,d
+\s+[0-9a-f]+:\s+cb b3\s+res 6,e
+\s+[0-9a-f]+:\s+cb b4\s+res 6,h
+\s+[0-9a-f]+:\s+cb b5\s+res 6,l
+\s+[0-9a-f]+:\s+cb b6\s+res 6,\(hl\)
+\s+[0-9a-f]+:\s+cb b7\s+res 6,a
+\s+[0-9a-f]+:\s+cb b8\s+res 7,b
+\s+[0-9a-f]+:\s+cb b9\s+res 7,c
+\s+[0-9a-f]+:\s+cb ba\s+res 7,d
+\s+[0-9a-f]+:\s+cb bb\s+res 7,e
+\s+[0-9a-f]+:\s+cb bc\s+res 7,h
+\s+[0-9a-f]+:\s+cb bd\s+res 7,l
+\s+[0-9a-f]+:\s+cb be\s+res 7,\(hl\)
+\s+[0-9a-f]+:\s+cb bf\s+res 7,a
+\s+[0-9a-f]+:\s+cb c0\s+set 0,b
+\s+[0-9a-f]+:\s+cb c1\s+set 0,c
+\s+[0-9a-f]+:\s+cb c2\s+set 0,d
+\s+[0-9a-f]+:\s+cb c3\s+set 0,e
+\s+[0-9a-f]+:\s+cb c4\s+set 0,h
+\s+[0-9a-f]+:\s+cb c5\s+set 0,l
+\s+[0-9a-f]+:\s+cb c6\s+set 0,\(hl\)
+\s+[0-9a-f]+:\s+cb c7\s+set 0,a
+\s+[0-9a-f]+:\s+cb c8\s+set 1,b
+\s+[0-9a-f]+:\s+cb c9\s+set 1,c
+\s+[0-9a-f]+:\s+cb ca\s+set 1,d
+\s+[0-9a-f]+:\s+cb cb\s+set 1,e
+\s+[0-9a-f]+:\s+cb cc\s+set 1,h
+\s+[0-9a-f]+:\s+cb cd\s+set 1,l
+\s+[0-9a-f]+:\s+cb ce\s+set 1,\(hl\)
+\s+[0-9a-f]+:\s+cb cf\s+set 1,a
+\s+[0-9a-f]+:\s+cb d0\s+set 2,b
+\s+[0-9a-f]+:\s+cb d1\s+set 2,c
+\s+[0-9a-f]+:\s+cb d2\s+set 2,d
+\s+[0-9a-f]+:\s+cb d3\s+set 2,e
+\s+[0-9a-f]+:\s+cb d4\s+set 2,h
+\s+[0-9a-f]+:\s+cb d5\s+set 2,l
+\s+[0-9a-f]+:\s+cb d6\s+set 2,\(hl\)
+\s+[0-9a-f]+:\s+cb d7\s+set 2,a
+\s+[0-9a-f]+:\s+cb d8\s+set 3,b
+\s+[0-9a-f]+:\s+cb d9\s+set 3,c
+\s+[0-9a-f]+:\s+cb da\s+set 3,d
+\s+[0-9a-f]+:\s+cb db\s+set 3,e
+\s+[0-9a-f]+:\s+cb dc\s+set 3,h
+\s+[0-9a-f]+:\s+cb dd\s+set 3,l
+\s+[0-9a-f]+:\s+cb de\s+set 3,\(hl\)
+\s+[0-9a-f]+:\s+cb df\s+set 3,a
+\s+[0-9a-f]+:\s+cb e0\s+set 4,b
+\s+[0-9a-f]+:\s+cb e1\s+set 4,c
+\s+[0-9a-f]+:\s+cb e2\s+set 4,d
+\s+[0-9a-f]+:\s+cb e3\s+set 4,e
+\s+[0-9a-f]+:\s+cb e4\s+set 4,h
+\s+[0-9a-f]+:\s+cb e5\s+set 4,l
+\s+[0-9a-f]+:\s+cb e6\s+set 4,\(hl\)
+\s+[0-9a-f]+:\s+cb e7\s+set 4,a
+\s+[0-9a-f]+:\s+cb e8\s+set 5,b
+\s+[0-9a-f]+:\s+cb e9\s+set 5,c
+\s+[0-9a-f]+:\s+cb ea\s+set 5,d
+\s+[0-9a-f]+:\s+cb eb\s+set 5,e
+\s+[0-9a-f]+:\s+cb ec\s+set 5,h
+\s+[0-9a-f]+:\s+cb ed\s+set 5,l
+\s+[0-9a-f]+:\s+cb ee\s+set 5,\(hl\)
+\s+[0-9a-f]+:\s+cb ef\s+set 5,a
+\s+[0-9a-f]+:\s+cb f0\s+set 6,b
+\s+[0-9a-f]+:\s+cb f1\s+set 6,c
+\s+[0-9a-f]+:\s+cb f2\s+set 6,d
+\s+[0-9a-f]+:\s+cb f3\s+set 6,e
+\s+[0-9a-f]+:\s+cb f4\s+set 6,h
+\s+[0-9a-f]+:\s+cb f5\s+set 6,l
+\s+[0-9a-f]+:\s+cb f6\s+set 6,\(hl\)
+\s+[0-9a-f]+:\s+cb f7\s+set 6,a
+\s+[0-9a-f]+:\s+cb f8\s+set 7,b
+\s+[0-9a-f]+:\s+cb f9\s+set 7,c
+\s+[0-9a-f]+:\s+cb fa\s+set 7,d
+\s+[0-9a-f]+:\s+cb fb\s+set 7,e
+\s+[0-9a-f]+:\s+cb fc\s+set 7,h
+\s+[0-9a-f]+:\s+cb fd\s+set 7,l
+\s+[0-9a-f]+:\s+cb fe\s+set 7,\(hl\)
+\s+[0-9a-f]+:\s+cb ff\s+set 7,a
diff --git a/gas/testsuite/gas/z80/gbz80_all.s b/gas/testsuite/gas/z80/gbz80_all.s
new file mode 100644
index 0000000..8e9085e
--- /dev/null
+++ b/gas/testsuite/gas/z80/gbz80_all.s
@@ -0,0 +1,519 @@
+ .text
+ .org 0
+;; Game Boy Z80 opcode test
+ nop
+ ld bc,0xbeaf
+ ld (bc),a
+ inc bc
+ inc b
+ dec b
+ ld b,0xfd
+ rlca
+ ld (0xbeaf),sp
+ add hl,bc
+ ld a,(bc)
+ dec bc
+ inc c
+ dec c
+ ld c,0xfd
+ rrca
+ stop
+ ld de,0xbeaf
+ ld (de),a
+ inc de
+ inc d
+ dec d
+ ld d,0xfd
+ rla
+ jr .+12
+ add hl,de
+ ld a,(de)
+ dec de
+ inc e
+ dec e
+ ld e,0xfd
+ rra
+ jr nz,.+12
+ ld hl,0xbeaf
+ ldi (hl),a
+ ld (hl+),a
+ inc hl
+ inc h
+ dec h
+ ld h,0xfd
+ daa
+ jr z,.+12
+ add hl,hl
+ ldi a,(hl)
+ ld a,(hl+)
+ dec hl
+ inc l
+ dec l
+ ld l,0xfd
+ cpl
+ jr nc,.+12
+ ld sp,0xbeaf
+ ldd (hl),a
+ ld (hl-),a
+ inc sp
+ inc (hl)
+ dec (hl)
+ ld (hl),0xfd
+ scf
+ jr c,.+12
+ add hl,sp
+ ldd a,(hl)
+ ld a,(hl-)
+ dec sp
+ inc a
+ dec a
+ ld a,0xfd
+ ccf
+ ld b,b
+ ld b,c
+ ld b,d
+ ld b,e
+ ld b,h
+ ld b,l
+ ld b,(hl)
+ ld b,a
+ ld c,b
+ ld c,c
+ ld c,d
+ ld c,e
+ ld c,h
+ ld c,l
+ ld c,(hl)
+ ld c,a
+ ld d,b
+ ld d,c
+ ld d,d
+ ld d,e
+ ld d,h
+ ld d,l
+ ld d,(hl)
+ ld d,a
+ ld e,b
+ ld e,c
+ ld e,d
+ ld e,e
+ ld e,h
+ ld e,l
+ ld e,(hl)
+ ld e,a
+ ld h,b
+ ld h,c
+ ld h,d
+ ld h,e
+ ld h,h
+ ld h,l
+ ld h,(hl)
+ ld h,a
+ ld l,b
+ ld l,c
+ ld l,d
+ ld l,e
+ ld l,h
+ ld l,l
+ ld l,(hl)
+ ld l,a
+ ld (hl),b
+ ld (hl),c
+ ld (hl),d
+ ld (hl),e
+ ld (hl),h
+ ld (hl),l
+ halt
+ ld (hl),a
+ ld a,b
+ ld a,c
+ ld a,d
+ ld a,e
+ ld a,h
+ ld a,l
+ ld a,(hl)
+ ld a,a
+ add a,b
+ add a,c
+ add a,d
+ add a,e
+ add a,h
+ add a,l
+ add a,(hl)
+ add a,a
+ adc a,b
+ adc a,c
+ adc a,d
+ adc a,e
+ adc a,h
+ adc a,l
+ adc a,(hl)
+ adc a,a
+ sub a,b
+ sub a,c
+ sub a,d
+ sub a,e
+ sub a,h
+ sub a,l
+ sub a,(hl)
+ sub a,a
+ sbc a,b
+ sbc a,c
+ sbc a,d
+ sbc a,e
+ sbc a,h
+ sbc a,l
+ sbc a,(hl)
+ sbc a,a
+ and b
+ and c
+ and d
+ and e
+ and h
+ and l
+ and (hl)
+ and a
+ xor b
+ xor c
+ xor d
+ xor e
+ xor h
+ xor l
+ xor (hl)
+ xor a
+ or b
+ or c
+ or d
+ or e
+ or h
+ or l
+ or (hl)
+ or a
+ cp b
+ cp c
+ cp d
+ cp e
+ cp h
+ cp l
+ cp (hl)
+ cp a
+ ret nz
+ pop bc
+ jp nz,0xbeaf
+ jp 0xbeaf
+ call nz,0xbeaf
+ push bc
+ add a,0xfd
+ rst 0
+ ret z
+ ret
+ jp z,0xbeaf
+ nop ;CB prefix
+ call z,0xbeaf
+ call 0xbeaf
+ adc a,0xfd
+ rst 0x08
+ ret nc
+ pop de
+ jp nc,0xbeaf
+ ;xx
+ call nc,0xbeaf
+ push de
+ sub a,0xfd
+ rst 0x10
+ ret c
+ reti
+ jp c,0xbeaf
+ ;xx
+ call c,0xbeaf
+ ;xx
+ sbc a,0xfd
+ rst 0x18
+ ldh (0xfd),a
+ pop hl
+ ldh (c),a
+ ;xx
+ ;xx
+ push hl
+ and 0xfd
+ rst 0x20
+ add sp,-12
+ jp (hl)
+ ld (0xbeaf),a
+ ;xx
+ ;xx
+ ;xx
+ xor 0xfd
+ rst 0x28
+ ldh a,(0xfd)
+ pop af
+ ldh a,(c)
+ di
+ ;xx
+ push af
+ or 0xfd
+ rst 0x30
+ ldhl sp,-12
+ ld sp,hl
+ ld a,(0xbeaf)
+ ei
+ ;xx
+ ;xx
+ cp 0xfd
+ rst 0x38
+ rlc b
+ rlc c
+ rlc d
+ rlc e
+ rlc h
+ rlc l
+ rlc (hl)
+ rlc a
+ rrc b
+ rrc c
+ rrc d
+ rrc e
+ rrc h
+ rrc l
+ rrc (hl)
+ rrc a
+ rl b
+ rl c
+ rl d
+ rl e
+ rl h
+ rl l
+ rl (hl)
+ rl a
+ rr b
+ rr c
+ rr d
+ rr e
+ rr h
+ rr l
+ rr (hl)
+ rr a
+ sla b
+ sla c
+ sla d
+ sla e
+ sla h
+ sla l
+ sla (hl)
+ sla a
+ sra b
+ sra c
+ sra d
+ sra e
+ sra h
+ sra l
+ sra (hl)
+ sra a
+ swap b
+ swap c
+ swap d
+ swap e
+ swap h
+ swap l
+ swap (hl)
+ swap a
+ srl b
+ srl c
+ srl d
+ srl e
+ srl h
+ srl l
+ srl (hl)
+ srl a
+ bit 0,b
+ bit 0,c
+ bit 0,d
+ bit 0,e
+ bit 0,h
+ bit 0,l
+ bit 0,(hl)
+ bit 0,a
+ bit 1,b
+ bit 1,c
+ bit 1,d
+ bit 1,e
+ bit 1,h
+ bit 1,l
+ bit 1,(hl)
+ bit 1,a
+ bit 2,b
+ bit 2,c
+ bit 2,d
+ bit 2,e
+ bit 2,h
+ bit 2,l
+ bit 2,(hl)
+ bit 2,a
+ bit 3,b
+ bit 3,c
+ bit 3,d
+ bit 3,e
+ bit 3,h
+ bit 3,l
+ bit 3,(hl)
+ bit 3,a
+ bit 4,b
+ bit 4,c
+ bit 4,d
+ bit 4,e
+ bit 4,h
+ bit 4,l
+ bit 4,(hl)
+ bit 4,a
+ bit 5,b
+ bit 5,c
+ bit 5,d
+ bit 5,e
+ bit 5,h
+ bit 5,l
+ bit 5,(hl)
+ bit 5,a
+ bit 6,b
+ bit 6,c
+ bit 6,d
+ bit 6,e
+ bit 6,h
+ bit 6,l
+ bit 6,(hl)
+ bit 6,a
+ bit 7,b
+ bit 7,c
+ bit 7,d
+ bit 7,e
+ bit 7,h
+ bit 7,l
+ bit 7,(hl)
+ bit 7,a
+ res 0,b
+ res 0,c
+ res 0,d
+ res 0,e
+ res 0,h
+ res 0,l
+ res 0,(hl)
+ res 0,a
+ res 1,b
+ res 1,c
+ res 1,d
+ res 1,e
+ res 1,h
+ res 1,l
+ res 1,(hl)
+ res 1,a
+ res 2,b
+ res 2,c
+ res 2,d
+ res 2,e
+ res 2,h
+ res 2,l
+ res 2,(hl)
+ res 2,a
+ res 3,b
+ res 3,c
+ res 3,d
+ res 3,e
+ res 3,h
+ res 3,l
+ res 3,(hl)
+ res 3,a
+ res 4,b
+ res 4,c
+ res 4,d
+ res 4,e
+ res 4,h
+ res 4,l
+ res 4,(hl)
+ res 4,a
+ res 5,b
+ res 5,c
+ res 5,d
+ res 5,e
+ res 5,h
+ res 5,l
+ res 5,(hl)
+ res 5,a
+ res 6,b
+ res 6,c
+ res 6,d
+ res 6,e
+ res 6,h
+ res 6,l
+ res 6,(hl)
+ res 6,a
+ res 7,b
+ res 7,c
+ res 7,d
+ res 7,e
+ res 7,h
+ res 7,l
+ res 7,(hl)
+ res 7,a
+ set 0,b
+ set 0,c
+ set 0,d
+ set 0,e
+ set 0,h
+ set 0,l
+ set 0,(hl)
+ set 0,a
+ set 1,b
+ set 1,c
+ set 1,d
+ set 1,e
+ set 1,h
+ set 1,l
+ set 1,(hl)
+ set 1,a
+ set 2,b
+ set 2,c
+ set 2,d
+ set 2,e
+ set 2,h
+ set 2,l
+ set 2,(hl)
+ set 2,a
+ set 3,b
+ set 3,c
+ set 3,d
+ set 3,e
+ set 3,h
+ set 3,l
+ set 3,(hl)
+ set 3,a
+ set 4,b
+ set 4,c
+ set 4,d
+ set 4,e
+ set 4,h
+ set 4,l
+ set 4,(hl)
+ set 4,a
+ set 5,b
+ set 5,c
+ set 5,d
+ set 5,e
+ set 5,h
+ set 5,l
+ set 5,(hl)
+ set 5,a
+ set 6,b
+ set 6,c
+ set 6,d
+ set 6,e
+ set 6,h
+ set 6,l
+ set 6,(hl)
+ set 6,a
+ set 7,b
+ set 7,c
+ set 7,d
+ set 7,e
+ set 7,h
+ set 7,l
+ set 7,(hl)
+ set 7,a
diff --git a/gas/testsuite/gas/z80/z80.exp b/gas/testsuite/gas/z80/z80.exp
index 6ba13fc..31f6113 100644
--- a/gas/testsuite/gas/z80/z80.exp
+++ b/gas/testsuite/gas/z80/z80.exp
@@ -92,6 +92,12 @@ if [istarget z80-*-*] then {
run_dump_test "ez80_adl_suf"
#test for eZ80 opcode prefixes as multiple bytes before instruction
run_dump_test "ez80_pref_dis"
+#test for GBZ80 instruction set
+ run_dump_test "gbz80_all"
+#test for Z80N instruction set
+ run_dump_test "z80n_all"
+#test for Z80N push nn relocation test
+ run_dump_test "z80n_reloc"
# test for SDCC compatibility mode
run_dump_test "sdcc"
# test for colonless labels
diff --git a/gas/testsuite/gas/z80/z80n_all.d b/gas/testsuite/gas/z80/z80n_all.d
new file mode 100644
index 0000000..3412905
--- /dev/null
+++ b/gas/testsuite/gas/z80/z80n_all.d
@@ -0,0 +1,1208 @@
+#as: -z80n
+#objdump: -d
+
+.*:[ ]+file format (coff|elf32)\-z80
+
+
+Disassembly of section \.text:
+
+00000000 <\.text>:
+[ ]+0:[ ]+8e[ ]+adc a,\(hl\)
+[ ]+1:[ ]+dd 8e 09[ ]+adc a,\(ix\+9\)
+[ ]+4:[ ]+fd 8e 09[ ]+adc a,\(iy\+9\)
+[ ]+7:[ ]+ce 03[ ]+adc a,0x03
+[ ]+9:[ ]+8f[ ]+adc a,a
+[ ]+a:[ ]+88[ ]+adc a,b
+[ ]+b:[ ]+89[ ]+adc a,c
+[ ]+c:[ ]+8a[ ]+adc a,d
+[ ]+d:[ ]+8b[ ]+adc a,e
+[ ]+e:[ ]+8c[ ]+adc a,h
+[ ]+f:[ ]+8d[ ]+adc a,l
+[ ]+10:[ ]+ed 4a[ ]+adc hl,bc
+[ ]+12:[ ]+ed 5a[ ]+adc hl,de
+[ ]+14:[ ]+ed 6a[ ]+adc hl,hl
+[ ]+16:[ ]+ed 7a[ ]+adc hl,sp
+[ ]+18:[ ]+86[ ]+add a,\(hl\)
+[ ]+19:[ ]+dd 86 09[ ]+add a,\(ix\+9\)
+[ ]+1c:[ ]+fd 86 09[ ]+add a,\(iy\+9\)
+[ ]+1f:[ ]+c6 03[ ]+add a,0x03
+[ ]+21:[ ]+87[ ]+add a,a
+[ ]+22:[ ]+80[ ]+add a,b
+[ ]+23:[ ]+81[ ]+add a,c
+[ ]+24:[ ]+82[ ]+add a,d
+[ ]+25:[ ]+83[ ]+add a,e
+[ ]+26:[ ]+84[ ]+add a,h
+[ ]+27:[ ]+85[ ]+add a,l
+[ ]+28:[ ]+09[ ]+add hl,bc
+[ ]+29:[ ]+19[ ]+add hl,de
+[ ]+2a:[ ]+29[ ]+add hl,hl
+[ ]+2b:[ ]+39[ ]+add hl,sp
+[ ]+2c:[ ]+dd 09[ ]+add ix,bc
+[ ]+2e:[ ]+dd 19[ ]+add ix,de
+[ ]+30:[ ]+dd 29[ ]+add ix,ix
+[ ]+32:[ ]+dd 39[ ]+add ix,sp
+[ ]+34:[ ]+fd 09[ ]+add iy,bc
+[ ]+36:[ ]+fd 19[ ]+add iy,de
+[ ]+38:[ ]+fd 29[ ]+add iy,iy
+[ ]+3a:[ ]+fd 39[ ]+add iy,sp
+[ ]+3c:[ ]+a6[ ]+and \(hl\)
+[ ]+3d:[ ]+dd a6 09[ ]+and \(ix\+9\)
+[ ]+40:[ ]+fd a6 09[ ]+and \(iy\+9\)
+[ ]+43:[ ]+e6 03[ ]+and 0x03
+[ ]+45:[ ]+a7[ ]+and a
+[ ]+46:[ ]+a0[ ]+and b
+[ ]+47:[ ]+a1[ ]+and c
+[ ]+48:[ ]+a2[ ]+and d
+[ ]+49:[ ]+a3[ ]+and e
+[ ]+4a:[ ]+a4[ ]+and h
+[ ]+4b:[ ]+a5[ ]+and l
+[ ]+4c:[ ]+cb 46[ ]+bit 0,\(hl\)
+[ ]+4e:[ ]+dd cb 09 46[ ]+bit 0,\(ix\+9\)
+[ ]+52:[ ]+fd cb 09 46[ ]+bit 0,\(iy\+9\)
+[ ]+56:[ ]+cb 47[ ]+bit 0,a
+[ ]+58:[ ]+cb 40[ ]+bit 0,b
+[ ]+5a:[ ]+cb 41[ ]+bit 0,c
+[ ]+5c:[ ]+cb 42[ ]+bit 0,d
+[ ]+5e:[ ]+cb 43[ ]+bit 0,e
+[ ]+60:[ ]+cb 44[ ]+bit 0,h
+[ ]+62:[ ]+cb 45[ ]+bit 0,l
+[ ]+64:[ ]+cb 4e[ ]+bit 1,\(hl\)
+[ ]+66:[ ]+dd cb 09 4e[ ]+bit 1,\(ix\+9\)
+[ ]+6a:[ ]+fd cb 09 4e[ ]+bit 1,\(iy\+9\)
+[ ]+6e:[ ]+cb 4f[ ]+bit 1,a
+[ ]+70:[ ]+cb 48[ ]+bit 1,b
+[ ]+72:[ ]+cb 49[ ]+bit 1,c
+[ ]+74:[ ]+cb 4a[ ]+bit 1,d
+[ ]+76:[ ]+cb 4b[ ]+bit 1,e
+[ ]+78:[ ]+cb 4c[ ]+bit 1,h
+[ ]+7a:[ ]+cb 4d[ ]+bit 1,l
+[ ]+7c:[ ]+cb 56[ ]+bit 2,\(hl\)
+[ ]+7e:[ ]+dd cb 09 56[ ]+bit 2,\(ix\+9\)
+[ ]+82:[ ]+fd cb 09 56[ ]+bit 2,\(iy\+9\)
+[ ]+86:[ ]+cb 57[ ]+bit 2,a
+[ ]+88:[ ]+cb 50[ ]+bit 2,b
+[ ]+8a:[ ]+cb 51[ ]+bit 2,c
+[ ]+8c:[ ]+cb 52[ ]+bit 2,d
+[ ]+8e:[ ]+cb 53[ ]+bit 2,e
+[ ]+90:[ ]+cb 54[ ]+bit 2,h
+[ ]+92:[ ]+cb 55[ ]+bit 2,l
+[ ]+94:[ ]+cb 5e[ ]+bit 3,\(hl\)
+[ ]+96:[ ]+dd cb 09 5e[ ]+bit 3,\(ix\+9\)
+[ ]+9a:[ ]+fd cb 09 5e[ ]+bit 3,\(iy\+9\)
+[ ]+9e:[ ]+cb 5f[ ]+bit 3,a
+[ ]+a0:[ ]+cb 58[ ]+bit 3,b
+[ ]+a2:[ ]+cb 59[ ]+bit 3,c
+[ ]+a4:[ ]+cb 5a[ ]+bit 3,d
+[ ]+a6:[ ]+cb 5b[ ]+bit 3,e
+[ ]+a8:[ ]+cb 5c[ ]+bit 3,h
+[ ]+aa:[ ]+cb 5d[ ]+bit 3,l
+[ ]+ac:[ ]+cb 66[ ]+bit 4,\(hl\)
+[ ]+ae:[ ]+dd cb 09 66[ ]+bit 4,\(ix\+9\)
+[ ]+b2:[ ]+fd cb 09 66[ ]+bit 4,\(iy\+9\)
+[ ]+b6:[ ]+cb 67[ ]+bit 4,a
+[ ]+b8:[ ]+cb 60[ ]+bit 4,b
+[ ]+ba:[ ]+cb 61[ ]+bit 4,c
+[ ]+bc:[ ]+cb 62[ ]+bit 4,d
+[ ]+be:[ ]+cb 63[ ]+bit 4,e
+[ ]+c0:[ ]+cb 64[ ]+bit 4,h
+[ ]+c2:[ ]+cb 65[ ]+bit 4,l
+[ ]+c4:[ ]+cb 6e[ ]+bit 5,\(hl\)
+[ ]+c6:[ ]+dd cb 09 6e[ ]+bit 5,\(ix\+9\)
+[ ]+ca:[ ]+fd cb 09 6e[ ]+bit 5,\(iy\+9\)
+[ ]+ce:[ ]+cb 6f[ ]+bit 5,a
+[ ]+d0:[ ]+cb 68[ ]+bit 5,b
+[ ]+d2:[ ]+cb 69[ ]+bit 5,c
+[ ]+d4:[ ]+cb 6a[ ]+bit 5,d
+[ ]+d6:[ ]+cb 6b[ ]+bit 5,e
+[ ]+d8:[ ]+cb 6c[ ]+bit 5,h
+[ ]+da:[ ]+cb 6d[ ]+bit 5,l
+[ ]+dc:[ ]+cb 76[ ]+bit 6,\(hl\)
+[ ]+de:[ ]+dd cb 09 76[ ]+bit 6,\(ix\+9\)
+[ ]+e2:[ ]+fd cb 09 76[ ]+bit 6,\(iy\+9\)
+[ ]+e6:[ ]+cb 77[ ]+bit 6,a
+[ ]+e8:[ ]+cb 70[ ]+bit 6,b
+[ ]+ea:[ ]+cb 71[ ]+bit 6,c
+[ ]+ec:[ ]+cb 72[ ]+bit 6,d
+[ ]+ee:[ ]+cb 73[ ]+bit 6,e
+[ ]+f0:[ ]+cb 74[ ]+bit 6,h
+[ ]+f2:[ ]+cb 75[ ]+bit 6,l
+[ ]+f4:[ ]+cb 7e[ ]+bit 7,\(hl\)
+[ ]+f6:[ ]+dd cb 09 7e[ ]+bit 7,\(ix\+9\)
+[ ]+fa:[ ]+fd cb 09 7e[ ]+bit 7,\(iy\+9\)
+[ ]+fe:[ ]+cb 7f[ ]+bit 7,a
+[ ]+100:[ ]+cb 78[ ]+bit 7,b
+[ ]+102:[ ]+cb 79[ ]+bit 7,c
+[ ]+104:[ ]+cb 7a[ ]+bit 7,d
+[ ]+106:[ ]+cb 7b[ ]+bit 7,e
+[ ]+108:[ ]+cb 7c[ ]+bit 7,h
+[ ]+10a:[ ]+cb 7d[ ]+bit 7,l
+[ ]+10c:[ ]+cd 34 12[ ]+call 0x1234
+[ ]+10f:[ ]+dc 34 12[ ]+call c,0x1234
+[ ]+112:[ ]+fc 34 12[ ]+call m,0x1234
+[ ]+115:[ ]+d4 34 12[ ]+call nc,0x1234
+[ ]+118:[ ]+c4 34 12[ ]+call nz,0x1234
+[ ]+11b:[ ]+f4 34 12[ ]+call p,0x1234
+[ ]+11e:[ ]+ec 34 12[ ]+call pe,0x1234
+[ ]+121:[ ]+e4 34 12[ ]+call po,0x1234
+[ ]+124:[ ]+cc 34 12[ ]+call z,0x1234
+[ ]+127:[ ]+3f[ ]+ccf
+[ ]+128:[ ]+be[ ]+cp \(hl\)
+[ ]+129:[ ]+dd be 09[ ]+cp \(ix\+9\)
+[ ]+12c:[ ]+fd be 09[ ]+cp \(iy\+9\)
+[ ]+12f:[ ]+fe 03[ ]+cp 0x03
+[ ]+131:[ ]+bf[ ]+cp a
+[ ]+132:[ ]+b8[ ]+cp b
+[ ]+133:[ ]+b9[ ]+cp c
+[ ]+134:[ ]+ba[ ]+cp d
+[ ]+135:[ ]+bb[ ]+cp e
+[ ]+136:[ ]+bc[ ]+cp h
+[ ]+137:[ ]+bd[ ]+cp l
+[ ]+138:[ ]+ed a9[ ]+cpd
+[ ]+13a:[ ]+ed b9[ ]+cpdr
+[ ]+13c:[ ]+ed a1[ ]+cpi
+[ ]+13e:[ ]+ed b1[ ]+cpir
+[ ]+140:[ ]+2f[ ]+cpl
+[ ]+141:[ ]+27[ ]+daa
+[ ]+142:[ ]+35[ ]+dec \(hl\)
+[ ]+143:[ ]+dd 35 09[ ]+dec \(ix\+9\)
+[ ]+146:[ ]+fd 35 09[ ]+dec \(iy\+9\)
+[ ]+149:[ ]+3d[ ]+dec a
+[ ]+14a:[ ]+05[ ]+dec b
+[ ]+14b:[ ]+0b[ ]+dec bc
+[ ]+14c:[ ]+0d[ ]+dec c
+[ ]+14d:[ ]+15[ ]+dec d
+[ ]+14e:[ ]+1b[ ]+dec de
+[ ]+14f:[ ]+1d[ ]+dec e
+[ ]+150:[ ]+25[ ]+dec h
+[ ]+151:[ ]+2b[ ]+dec hl
+[ ]+152:[ ]+dd 2b[ ]+dec ix
+[ ]+154:[ ]+fd 2b[ ]+dec iy
+[ ]+156:[ ]+2d[ ]+dec l
+[ ]+157:[ ]+3b[ ]+dec sp
+[ ]+158:[ ]+f3[ ]+di
+[ ]+159:[ ]+10 05[ ]+djnz 0x0160
+[ ]+15b:[ ]+fb[ ]+ei
+[ ]+15c:[ ]+e3[ ]+ex \(sp\),hl
+[ ]+15d:[ ]+dd e3[ ]+ex \(sp\),ix
+[ ]+15f:[ ]+fd e3[ ]+ex \(sp\),iy
+[ ]+161:[ ]+08[ ]+ex af,af'
+[ ]+162:[ ]+eb[ ]+ex de,hl
+[ ]+163:[ ]+d9[ ]+exx
+[ ]+164:[ ]+76[ ]+halt
+[ ]+165:[ ]+ed 46[ ]+im 0
+[ ]+167:[ ]+ed 56[ ]+im 1
+[ ]+169:[ ]+ed 5e[ ]+im 2
+[ ]+16b:[ ]+ed 78[ ]+in a,\(c\)
+[ ]+16d:[ ]+db 03[ ]+in a,\(0x03\)
+[ ]+16f:[ ]+ed 40[ ]+in b,\(c\)
+[ ]+171:[ ]+ed 48[ ]+in c,\(c\)
+[ ]+173:[ ]+ed 50[ ]+in d,\(c\)
+[ ]+175:[ ]+ed 58[ ]+in e,\(c\)
+[ ]+177:[ ]+ed 60[ ]+in h,\(c\)
+[ ]+179:[ ]+ed 68[ ]+in l,\(c\)
+[ ]+17b:[ ]+34[ ]+inc \(hl\)
+[ ]+17c:[ ]+dd 34 09[ ]+inc \(ix\+9\)
+[ ]+17f:[ ]+fd 34 09[ ]+inc \(iy\+9\)
+[ ]+182:[ ]+3c[ ]+inc a
+[ ]+183:[ ]+04[ ]+inc b
+[ ]+184:[ ]+03[ ]+inc bc
+[ ]+185:[ ]+0c[ ]+inc c
+[ ]+186:[ ]+14[ ]+inc d
+[ ]+187:[ ]+13[ ]+inc de
+[ ]+188:[ ]+1c[ ]+inc e
+[ ]+189:[ ]+24[ ]+inc h
+[ ]+18a:[ ]+23[ ]+inc hl
+[ ]+18b:[ ]+dd 23[ ]+inc ix
+[ ]+18d:[ ]+fd 23[ ]+inc iy
+[ ]+18f:[ ]+2c[ ]+inc l
+[ ]+190:[ ]+33[ ]+inc sp
+[ ]+191:[ ]+ed aa[ ]+ind
+[ ]+193:[ ]+ed ba[ ]+indr
+[ ]+195:[ ]+ed a2[ ]+ini
+[ ]+197:[ ]+ed b2[ ]+inir
+[ ]+199:[ ]+e9[ ]+jp \(hl\)
+[ ]+19a:[ ]+dd e9[ ]+jp \(ix\)
+[ ]+19c:[ ]+fd e9[ ]+jp \(iy\)
+[ ]+19e:[ ]+c3 34 12[ ]+jp 0x1234
+[ ]+1a1:[ ]+da 34 12[ ]+jp c,0x1234
+[ ]+1a4:[ ]+fa 34 12[ ]+jp m,0x1234
+[ ]+1a7:[ ]+d2 34 12[ ]+jp nc,0x1234
+[ ]+1aa:[ ]+c2 34 12[ ]+jp nz,0x1234
+[ ]+1ad:[ ]+f2 34 12[ ]+jp p,0x1234
+[ ]+1b0:[ ]+ea 34 12[ ]+jp pe,0x1234
+[ ]+1b3:[ ]+e2 34 12[ ]+jp po,0x1234
+[ ]+1b6:[ ]+ca 34 12[ ]+jp z,0x1234
+[ ]+1b9:[ ]+18 05[ ]+jr 0x01c0
+[ ]+1bb:[ ]+38 05[ ]+jr c,0x01c2
+[ ]+1bd:[ ]+30 05[ ]+jr nc,0x01c4
+[ ]+1bf:[ ]+20 05[ ]+jr nz,0x01c6
+[ ]+1c1:[ ]+28 05[ ]+jr z,0x01c8
+[ ]+1c3:[ ]+32 34 12[ ]+ld \(0x1234\),a
+[ ]+1c6:[ ]+ed 43 34 12[ ]+ld \(0x1234\),bc
+[ ]+1ca:[ ]+ed 53 34 12[ ]+ld \(0x1234\),de
+[ ]+1ce:[ ]+22 34 12[ ]+ld \(0x1234\),hl
+[ ]+1d1:[ ]+dd 22 34 12[ ]+ld \(0x1234\),ix
+[ ]+1d5:[ ]+fd 22 34 12[ ]+ld \(0x1234\),iy
+[ ]+1d9:[ ]+ed 73 34 12[ ]+ld \(0x1234\),sp
+[ ]+1dd:[ ]+02[ ]+ld \(bc\),a
+[ ]+1de:[ ]+12[ ]+ld \(de\),a
+[ ]+1df:[ ]+36 03[ ]+ld \(hl\),0x03
+[ ]+1e1:[ ]+77[ ]+ld \(hl\),a
+[ ]+1e2:[ ]+70[ ]+ld \(hl\),b
+[ ]+1e3:[ ]+71[ ]+ld \(hl\),c
+[ ]+1e4:[ ]+72[ ]+ld \(hl\),d
+[ ]+1e5:[ ]+73[ ]+ld \(hl\),e
+[ ]+1e6:[ ]+74[ ]+ld \(hl\),h
+[ ]+1e7:[ ]+75[ ]+ld \(hl\),l
+[ ]+1e8:[ ]+dd 36 09 03[ ]+ld \(ix\+9\),0x03
+[ ]+1ec:[ ]+dd 77 09[ ]+ld \(ix\+9\),a
+[ ]+1ef:[ ]+dd 70 09[ ]+ld \(ix\+9\),b
+[ ]+1f2:[ ]+dd 71 09[ ]+ld \(ix\+9\),c
+[ ]+1f5:[ ]+dd 72 09[ ]+ld \(ix\+9\),d
+[ ]+1f8:[ ]+dd 73 09[ ]+ld \(ix\+9\),e
+[ ]+1fb:[ ]+dd 74 09[ ]+ld \(ix\+9\),h
+[ ]+1fe:[ ]+dd 75 09[ ]+ld \(ix\+9\),l
+[ ]+201:[ ]+fd 36 09 03[ ]+ld \(iy\+9\),0x03
+[ ]+205:[ ]+fd 77 09[ ]+ld \(iy\+9\),a
+[ ]+208:[ ]+fd 70 09[ ]+ld \(iy\+9\),b
+[ ]+20b:[ ]+fd 71 09[ ]+ld \(iy\+9\),c
+[ ]+20e:[ ]+fd 72 09[ ]+ld \(iy\+9\),d
+[ ]+211:[ ]+fd 73 09[ ]+ld \(iy\+9\),e
+[ ]+214:[ ]+fd 74 09[ ]+ld \(iy\+9\),h
+[ ]+217:[ ]+fd 75 09[ ]+ld \(iy\+9\),l
+[ ]+21a:[ ]+3a 34 12[ ]+ld a,\(0x1234\)
+[ ]+21d:[ ]+0a[ ]+ld a,\(bc\)
+[ ]+21e:[ ]+1a[ ]+ld a,\(de\)
+[ ]+21f:[ ]+7e[ ]+ld a,\(hl\)
+[ ]+220:[ ]+dd 7e 09[ ]+ld a,\(ix\+9\)
+[ ]+223:[ ]+fd 7e 09[ ]+ld a,\(iy\+9\)
+[ ]+226:[ ]+3e 03[ ]+ld a,0x03
+[ ]+228:[ ]+7f[ ]+ld a,a
+[ ]+229:[ ]+78[ ]+ld a,b
+[ ]+22a:[ ]+79[ ]+ld a,c
+[ ]+22b:[ ]+7a[ ]+ld a,d
+[ ]+22c:[ ]+7b[ ]+ld a,e
+[ ]+22d:[ ]+7c[ ]+ld a,h
+[ ]+22e:[ ]+ed 57[ ]+ld a,i
+[ ]+230:[ ]+7d[ ]+ld a,l
+[ ]+231:[ ]+ed 5f[ ]+ld a,r
+[ ]+233:[ ]+46[ ]+ld b,\(hl\)
+[ ]+234:[ ]+dd 46 09[ ]+ld b,\(ix\+9\)
+[ ]+237:[ ]+fd 46 09[ ]+ld b,\(iy\+9\)
+[ ]+23a:[ ]+06 03[ ]+ld b,0x03
+[ ]+23c:[ ]+47[ ]+ld b,a
+[ ]+23d:[ ]+40[ ]+ld b,b
+[ ]+23e:[ ]+41[ ]+ld b,c
+[ ]+23f:[ ]+42[ ]+ld b,d
+[ ]+240:[ ]+43[ ]+ld b,e
+[ ]+241:[ ]+44[ ]+ld b,h
+[ ]+242:[ ]+45[ ]+ld b,l
+[ ]+243:[ ]+ed 4b 34 12[ ]+ld bc,\(0x1234\)
+[ ]+247:[ ]+01 34 12[ ]+ld bc,0x1234
+[ ]+24a:[ ]+4e[ ]+ld c,\(hl\)
+[ ]+24b:[ ]+dd 4e 09[ ]+ld c,\(ix\+9\)
+[ ]+24e:[ ]+fd 4e 09[ ]+ld c,\(iy\+9\)
+[ ]+251:[ ]+0e 03[ ]+ld c,0x03
+[ ]+253:[ ]+4f[ ]+ld c,a
+[ ]+254:[ ]+48[ ]+ld c,b
+[ ]+255:[ ]+49[ ]+ld c,c
+[ ]+256:[ ]+4a[ ]+ld c,d
+[ ]+257:[ ]+4b[ ]+ld c,e
+[ ]+258:[ ]+4c[ ]+ld c,h
+[ ]+259:[ ]+4d[ ]+ld c,l
+[ ]+25a:[ ]+56[ ]+ld d,\(hl\)
+[ ]+25b:[ ]+dd 56 09[ ]+ld d,\(ix\+9\)
+[ ]+25e:[ ]+fd 56 09[ ]+ld d,\(iy\+9\)
+[ ]+261:[ ]+16 03[ ]+ld d,0x03
+[ ]+263:[ ]+57[ ]+ld d,a
+[ ]+264:[ ]+50[ ]+ld d,b
+[ ]+265:[ ]+51[ ]+ld d,c
+[ ]+266:[ ]+52[ ]+ld d,d
+[ ]+267:[ ]+53[ ]+ld d,e
+[ ]+268:[ ]+54[ ]+ld d,h
+[ ]+269:[ ]+55[ ]+ld d,l
+[ ]+26a:[ ]+ed 5b 34 12[ ]+ld de,\(0x1234\)
+[ ]+26e:[ ]+11 34 12[ ]+ld de,0x1234
+[ ]+271:[ ]+5e[ ]+ld e,\(hl\)
+[ ]+272:[ ]+dd 5e 09[ ]+ld e,\(ix\+9\)
+[ ]+275:[ ]+fd 5e 09[ ]+ld e,\(iy\+9\)
+[ ]+278:[ ]+1e 03[ ]+ld e,0x03
+[ ]+27a:[ ]+5f[ ]+ld e,a
+[ ]+27b:[ ]+58[ ]+ld e,b
+[ ]+27c:[ ]+59[ ]+ld e,c
+[ ]+27d:[ ]+5a[ ]+ld e,d
+[ ]+27e:[ ]+5b[ ]+ld e,e
+[ ]+27f:[ ]+5c[ ]+ld e,h
+[ ]+280:[ ]+5d[ ]+ld e,l
+[ ]+281:[ ]+66[ ]+ld h,\(hl\)
+[ ]+282:[ ]+dd 66 09[ ]+ld h,\(ix\+9\)
+[ ]+285:[ ]+fd 66 09[ ]+ld h,\(iy\+9\)
+[ ]+288:[ ]+26 03[ ]+ld h,0x03
+[ ]+28a:[ ]+67[ ]+ld h,a
+[ ]+28b:[ ]+60[ ]+ld h,b
+[ ]+28c:[ ]+61[ ]+ld h,c
+[ ]+28d:[ ]+62[ ]+ld h,d
+[ ]+28e:[ ]+63[ ]+ld h,e
+[ ]+28f:[ ]+64[ ]+ld h,h
+[ ]+290:[ ]+65[ ]+ld h,l
+[ ]+291:[ ]+2a 34 12[ ]+ld hl,\(0x1234\)
+[ ]+294:[ ]+21 34 12[ ]+ld hl,0x1234
+[ ]+297:[ ]+ed 47[ ]+ld i,a
+[ ]+299:[ ]+dd 2a 34 12[ ]+ld ix,\(0x1234\)
+[ ]+29d:[ ]+dd 21 34 12[ ]+ld ix,0x1234
+[ ]+2a1:[ ]+fd 2a 34 12[ ]+ld iy,\(0x1234\)
+[ ]+2a5:[ ]+fd 21 34 12[ ]+ld iy,0x1234
+[ ]+2a9:[ ]+6e[ ]+ld l,\(hl\)
+[ ]+2aa:[ ]+dd 6e 09[ ]+ld l,\(ix\+9\)
+[ ]+2ad:[ ]+fd 6e 09[ ]+ld l,\(iy\+9\)
+[ ]+2b0:[ ]+2e 03[ ]+ld l,0x03
+[ ]+2b2:[ ]+6f[ ]+ld l,a
+[ ]+2b3:[ ]+68[ ]+ld l,b
+[ ]+2b4:[ ]+69[ ]+ld l,c
+[ ]+2b5:[ ]+6a[ ]+ld l,d
+[ ]+2b6:[ ]+6b[ ]+ld l,e
+[ ]+2b7:[ ]+6c[ ]+ld l,h
+[ ]+2b8:[ ]+6d[ ]+ld l,l
+[ ]+2b9:[ ]+ed 4f[ ]+ld r,a
+[ ]+2bb:[ ]+ed 7b 34 12[ ]+ld sp,\(0x1234\)
+[ ]+2bf:[ ]+31 34 12[ ]+ld sp,0x1234
+[ ]+2c2:[ ]+f9[ ]+ld sp,hl
+[ ]+2c3:[ ]+dd f9[ ]+ld sp,ix
+[ ]+2c5:[ ]+fd f9[ ]+ld sp,iy
+[ ]+2c7:[ ]+ed a8[ ]+ldd
+[ ]+2c9:[ ]+ed b8[ ]+lddr
+[ ]+2cb:[ ]+ed a0[ ]+ldi
+[ ]+2cd:[ ]+ed b0[ ]+ldir
+[ ]+2cf:[ ]+ed 44[ ]+neg
+[ ]+2d1:[ ]+00[ ]+nop
+[ ]+2d2:[ ]+b6[ ]+or \(hl\)
+[ ]+2d3:[ ]+dd b6 09[ ]+or \(ix\+9\)
+[ ]+2d6:[ ]+fd b6 09[ ]+or \(iy\+9\)
+[ ]+2d9:[ ]+f6 03[ ]+or 0x03
+[ ]+2db:[ ]+b7[ ]+or a
+[ ]+2dc:[ ]+b0[ ]+or b
+[ ]+2dd:[ ]+b1[ ]+or c
+[ ]+2de:[ ]+b2[ ]+or d
+[ ]+2df:[ ]+b3[ ]+or e
+[ ]+2e0:[ ]+b4[ ]+or h
+[ ]+2e1:[ ]+b5[ ]+or l
+[ ]+2e2:[ ]+ed bb[ ]+otdr
+[ ]+2e4:[ ]+ed b3[ ]+otir
+[ ]+2e6:[ ]+ed 79[ ]+out \(c\),a
+[ ]+2e8:[ ]+ed 41[ ]+out \(c\),b
+[ ]+2ea:[ ]+ed 49[ ]+out \(c\),c
+[ ]+2ec:[ ]+ed 51[ ]+out \(c\),d
+[ ]+2ee:[ ]+ed 59[ ]+out \(c\),e
+[ ]+2f0:[ ]+ed 61[ ]+out \(c\),h
+[ ]+2f2:[ ]+ed 69[ ]+out \(c\),l
+[ ]+2f4:[ ]+d3 03[ ]+out \(0x03\),a
+[ ]+2f6:[ ]+ed ab[ ]+outd
+[ ]+2f8:[ ]+ed a3[ ]+outi
+[ ]+2fa:[ ]+f1[ ]+pop af
+[ ]+2fb:[ ]+c1[ ]+pop bc
+[ ]+2fc:[ ]+d1[ ]+pop de
+[ ]+2fd:[ ]+e1[ ]+pop hl
+[ ]+2fe:[ ]+dd e1[ ]+pop ix
+[ ]+300:[ ]+fd e1[ ]+pop iy
+[ ]+302:[ ]+f5[ ]+push af
+[ ]+303:[ ]+c5[ ]+push bc
+[ ]+304:[ ]+d5[ ]+push de
+[ ]+305:[ ]+e5[ ]+push hl
+[ ]+306:[ ]+dd e5[ ]+push ix
+[ ]+308:[ ]+fd e5[ ]+push iy
+[ ]+30a:[ ]+cb 86[ ]+res 0,\(hl\)
+[ ]+30c:[ ]+dd cb 09 86[ ]+res 0,\(ix\+9\)
+[ ]+310:[ ]+fd cb 09 86[ ]+res 0,\(iy\+9\)
+[ ]+314:[ ]+cb 87[ ]+res 0,a
+[ ]+316:[ ]+cb 80[ ]+res 0,b
+[ ]+318:[ ]+cb 81[ ]+res 0,c
+[ ]+31a:[ ]+cb 82[ ]+res 0,d
+[ ]+31c:[ ]+cb 83[ ]+res 0,e
+[ ]+31e:[ ]+cb 84[ ]+res 0,h
+[ ]+320:[ ]+cb 85[ ]+res 0,l
+[ ]+322:[ ]+cb 8e[ ]+res 1,\(hl\)
+[ ]+324:[ ]+dd cb 09 8e[ ]+res 1,\(ix\+9\)
+[ ]+328:[ ]+fd cb 09 8e[ ]+res 1,\(iy\+9\)
+[ ]+32c:[ ]+cb 8f[ ]+res 1,a
+[ ]+32e:[ ]+cb 88[ ]+res 1,b
+[ ]+330:[ ]+cb 89[ ]+res 1,c
+[ ]+332:[ ]+cb 8a[ ]+res 1,d
+[ ]+334:[ ]+cb 8b[ ]+res 1,e
+[ ]+336:[ ]+cb 8c[ ]+res 1,h
+[ ]+338:[ ]+cb 8d[ ]+res 1,l
+[ ]+33a:[ ]+cb 96[ ]+res 2,\(hl\)
+[ ]+33c:[ ]+dd cb 09 96[ ]+res 2,\(ix\+9\)
+[ ]+340:[ ]+fd cb 09 96[ ]+res 2,\(iy\+9\)
+[ ]+344:[ ]+cb 97[ ]+res 2,a
+[ ]+346:[ ]+cb 90[ ]+res 2,b
+[ ]+348:[ ]+cb 91[ ]+res 2,c
+[ ]+34a:[ ]+cb 92[ ]+res 2,d
+[ ]+34c:[ ]+cb 93[ ]+res 2,e
+[ ]+34e:[ ]+cb 94[ ]+res 2,h
+[ ]+350:[ ]+cb 95[ ]+res 2,l
+[ ]+352:[ ]+cb 9e[ ]+res 3,\(hl\)
+[ ]+354:[ ]+dd cb 09 9e[ ]+res 3,\(ix\+9\)
+[ ]+358:[ ]+fd cb 09 9e[ ]+res 3,\(iy\+9\)
+[ ]+35c:[ ]+cb 9f[ ]+res 3,a
+[ ]+35e:[ ]+cb 98[ ]+res 3,b
+[ ]+360:[ ]+cb 99[ ]+res 3,c
+[ ]+362:[ ]+cb 9a[ ]+res 3,d
+[ ]+364:[ ]+cb 9b[ ]+res 3,e
+[ ]+366:[ ]+cb 9c[ ]+res 3,h
+[ ]+368:[ ]+cb 9d[ ]+res 3,l
+[ ]+36a:[ ]+cb a6[ ]+res 4,\(hl\)
+[ ]+36c:[ ]+dd cb 09 a6[ ]+res 4,\(ix\+9\)
+[ ]+370:[ ]+fd cb 09 a6[ ]+res 4,\(iy\+9\)
+[ ]+374:[ ]+cb a7[ ]+res 4,a
+[ ]+376:[ ]+cb a0[ ]+res 4,b
+[ ]+378:[ ]+cb a1[ ]+res 4,c
+[ ]+37a:[ ]+cb a2[ ]+res 4,d
+[ ]+37c:[ ]+cb a3[ ]+res 4,e
+[ ]+37e:[ ]+cb a4[ ]+res 4,h
+[ ]+380:[ ]+cb a5[ ]+res 4,l
+[ ]+382:[ ]+cb ae[ ]+res 5,\(hl\)
+[ ]+384:[ ]+dd cb 09 ae[ ]+res 5,\(ix\+9\)
+[ ]+388:[ ]+fd cb 09 ae[ ]+res 5,\(iy\+9\)
+[ ]+38c:[ ]+cb af[ ]+res 5,a
+[ ]+38e:[ ]+cb a8[ ]+res 5,b
+[ ]+390:[ ]+cb a9[ ]+res 5,c
+[ ]+392:[ ]+cb aa[ ]+res 5,d
+[ ]+394:[ ]+cb ab[ ]+res 5,e
+[ ]+396:[ ]+cb ac[ ]+res 5,h
+[ ]+398:[ ]+cb ad[ ]+res 5,l
+[ ]+39a:[ ]+cb b6[ ]+res 6,\(hl\)
+[ ]+39c:[ ]+dd cb 09 b6[ ]+res 6,\(ix\+9\)
+[ ]+3a0:[ ]+fd cb 09 b6[ ]+res 6,\(iy\+9\)
+[ ]+3a4:[ ]+cb b7[ ]+res 6,a
+[ ]+3a6:[ ]+cb b0[ ]+res 6,b
+[ ]+3a8:[ ]+cb b1[ ]+res 6,c
+[ ]+3aa:[ ]+cb b2[ ]+res 6,d
+[ ]+3ac:[ ]+cb b3[ ]+res 6,e
+[ ]+3ae:[ ]+cb b4[ ]+res 6,h
+[ ]+3b0:[ ]+cb b5[ ]+res 6,l
+[ ]+3b2:[ ]+cb be[ ]+res 7,\(hl\)
+[ ]+3b4:[ ]+dd cb 09 be[ ]+res 7,\(ix\+9\)
+[ ]+3b8:[ ]+fd cb 09 be[ ]+res 7,\(iy\+9\)
+[ ]+3bc:[ ]+cb bf[ ]+res 7,a
+[ ]+3be:[ ]+cb b8[ ]+res 7,b
+[ ]+3c0:[ ]+cb b9[ ]+res 7,c
+[ ]+3c2:[ ]+cb ba[ ]+res 7,d
+[ ]+3c4:[ ]+cb bb[ ]+res 7,e
+[ ]+3c6:[ ]+cb bc[ ]+res 7,h
+[ ]+3c8:[ ]+cb bd[ ]+res 7,l
+[ ]+3ca:[ ]+c9[ ]+ret
+[ ]+3cb:[ ]+d8[ ]+ret c
+[ ]+3cc:[ ]+f8[ ]+ret m
+[ ]+3cd:[ ]+d0[ ]+ret nc
+[ ]+3ce:[ ]+c0[ ]+ret nz
+[ ]+3cf:[ ]+f0[ ]+ret p
+[ ]+3d0:[ ]+e8[ ]+ret pe
+[ ]+3d1:[ ]+e0[ ]+ret po
+[ ]+3d2:[ ]+c8[ ]+ret z
+[ ]+3d3:[ ]+ed 4d[ ]+reti
+[ ]+3d5:[ ]+ed 45[ ]+retn
+[ ]+3d7:[ ]+cb 16[ ]+rl \(hl\)
+[ ]+3d9:[ ]+dd cb 09 16[ ]+rl \(ix\+9\)
+[ ]+3dd:[ ]+fd cb 09 16[ ]+rl \(iy\+9\)
+[ ]+3e1:[ ]+cb 17[ ]+rl a
+[ ]+3e3:[ ]+cb 10[ ]+rl b
+[ ]+3e5:[ ]+cb 1[...]
[diff truncated at 100000 bytes]
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