[binutils-gdb] [PATCH 51/57][Arm][OBJDUMP] Add support for MVE instructions: lctp, letp, wlstp and dlstp

[Andre Simoes Dias Vieira]

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=d052b9b7cb90e0f76e35b0cf3c44e9b168b158c2

commit d052b9b7cb90e0f76e35b0cf3c44e9b168b158c2
Author: Andre Vieira <andre.simoesdiasvieira@arm.com>
Date:   Thu May 16 14:41:41 2019 +0100

    [PATCH 51/57][Arm][OBJDUMP] Add support for MVE instructions: lctp, letp, wlstp and dlstp
    
    opcodes/ChangeLog:
    2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
    	    Michael Collison <michael.collison@arm.com>
    
    	* arm-dis.c (thumb32_opcodes): Add new instructions.
    	(print_insn_thumb32): Handle new instructions.

Diff:
---
 opcodes/ChangeLog |  6 ++++++
 opcodes/arm-dis.c | 21 ++++++++++++++++++---
 2 files changed, 24 insertions(+), 3 deletions(-)

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 3c6573d..e1ca14b 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,6 +1,12 @@
 2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
 	    Michael Collison <michael.collison@arm.com>
 
+	* arm-dis.c (thumb32_opcodes): Add new instructions.
+	(print_insn_thumb32): Handle new instructions.
+
+2019-05-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+	    Michael Collison <michael.collison@arm.com>
+
 	* arm-dis.c (enum mve_instructions): Add new instructions.
 	(enum mve_undefined): Add new reasons.
 	(is_mve_encoding_conflict): Handle new instructions.
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 05fad18..22e7af5 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -3949,13 +3949,21 @@ static const struct opcode32 thumb32_opcodes[] =
   /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
      instructions.  */
   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
-    0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
-  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
-    0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
+    0xf00fe001, 0xffffffff, "lctp%c"},
   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
     0xf02fc001, 0xfffff001, "le\t%P"},
   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
     0xf00fc001, 0xfffff001, "le\tlr, %P"},
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+    0xf01fc001, 0xfffff001, "letp\tlr, %P"},
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+    0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+    0xf000c001, 0xffc0f001, "wlstp.%20-21s\tlr, %16-19S, %Q"},
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+    0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+    0xf000e001, 0xffc0ffff, "dlstp.%20-21s\tlr, %16-19S"},
 
   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
     0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
@@ -10171,6 +10179,13 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
 
 		  switch (*c)
 		    {
+		    case 's':
+		      if (val <= 3)
+			func (stream, "%s", mve_vec_sizename[val]);
+		      else
+			func (stream, "<undef size>");
+		      break;
+
 		    case 'd':
 		      func (stream, "%lu", val);
 		      value_in_comment = val;