[binutils-gdb] [binutils][aarch64] New SVE_SHLIMM_UNPRED_22 operand.
Matthew Malcomson
matmal01@sourceware.org
Thu May 9 09:31:00 GMT 2019
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=28ed815ad2b0cb93eede83022269d6a60b9cdf31
commit 28ed815ad2b0cb93eede83022269d6a60b9cdf31
Author: Matthew Malcomson <matthew.malcomson@arm.com>
Date: Thu May 9 10:29:27 2019 +0100
[binutils][aarch64] New SVE_SHLIMM_UNPRED_22 operand.
New operand describes a shift-left immediate encoded in bits
22:20-19:18-16 where UInt(bits) - esize == shift.
This operand is useful for instructions like sshllb.
gas/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c (parse_operands): Handle new SVE_SHLIMM_UNPRED_22
operand.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): New SVE_SHLIMM_UNPRED_22
operand.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
for SVE_SHLIMM_UNPRED_22.
(aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
operand.
Diff:
---
gas/ChangeLog | 5 +++++
gas/config/tc-aarch64.c | 1 +
include/ChangeLog | 5 +++++
include/opcode/aarch64.h | 1 +
opcodes/ChangeLog | 11 +++++++++++
opcodes/aarch64-asm-2.c | 23 ++++++++++++-----------
opcodes/aarch64-dis-2.c | 23 ++++++++++++-----------
opcodes/aarch64-opc-2.c | 1 +
opcodes/aarch64-opc.c | 2 ++
opcodes/aarch64-tbl.h | 3 +++
10 files changed, 53 insertions(+), 22 deletions(-)
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 9e08aef..2a37acf 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,10 @@
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
+ * config/tc-aarch64.c (parse_operands): Handle new SVE_SHLIMM_UNPRED_22
+ operand.
+
+2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
+
* config/tc-aarch64.c (parse_operands): Handle new SVE_Zm4_11_INDEX
operand.
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 5193c5d..7b9ebbd 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -5786,6 +5786,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
case AARCH64_OPND_SVE_LIMM_MOV:
case AARCH64_OPND_SVE_SHLIMM_PRED:
case AARCH64_OPND_SVE_SHLIMM_UNPRED:
+ case AARCH64_OPND_SVE_SHLIMM_UNPRED_22:
case AARCH64_OPND_SVE_SHRIMM_PRED:
case AARCH64_OPND_SVE_SHRIMM_UNPRED:
case AARCH64_OPND_SVE_SHRIMM_UNPRED_22:
diff --git a/include/ChangeLog b/include/ChangeLog
index 8a990f3..be6240e 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,5 +1,10 @@
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
+ * opcode/aarch64.h (enum aarch64_opnd): New SVE_SHLIMM_UNPRED_22
+ operand.
+
+2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
+
* opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_tsz_bhs
iclass.
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index e354e65..a4520da 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -392,6 +392,7 @@ enum aarch64_opnd
AARCH64_OPND_SVE_Rn_SP, /* Integer Rn or SP, alt. SVE position. */
AARCH64_OPND_SVE_SHLIMM_PRED, /* SVE shift left amount (predicated). */
AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated). */
+ AARCH64_OPND_SVE_SHLIMM_UNPRED_22, /* SVE 3 bit shift left unpred. */
AARCH64_OPND_SVE_SHRIMM_PRED, /* SVE shift right amount (predicated). */
AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated). */
AARCH64_OPND_SVE_SHRIMM_UNPRED_22, /* SVE 3 bit shift right unpred. */
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index bb823cd..86b3f42 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,16 @@
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
+ * aarch64-asm-2.c: Regenerated.
+ * aarch64-dis-2.c: Regenerated.
+ * aarch64-opc-2.c: Regenerated.
+ * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
+ for SVE_SHLIMM_UNPRED_22.
+ (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
+ * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
+ operand.
+
+2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
+
* aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
sve_size_tsz_bhs iclass encode.
* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
index b2a101f..20472ae 100644
--- a/opcodes/aarch64-asm-2.c
+++ b/opcodes/aarch64-asm-2.c
@@ -638,7 +638,6 @@ aarch64_insert_operand (const aarch64_operand *self,
case 169:
case 170:
case 171:
- case 185:
case 186:
case 187:
case 188:
@@ -647,8 +646,9 @@ aarch64_insert_operand (const aarch64_operand *self,
case 191:
case 192:
case 193:
- case 199:
- case 202:
+ case 194:
+ case 200:
+ case 203:
return aarch64_ins_regno (self, info, code, inst, errors);
case 14:
return aarch64_ins_reg_extended (self, info, code, inst, errors);
@@ -660,7 +660,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case 32:
case 33:
case 34:
- case 205:
+ case 206:
return aarch64_ins_reglane (self, info, code, inst, errors);
case 35:
return aarch64_ins_reglist (self, info, code, inst, errors);
@@ -696,7 +696,6 @@ aarch64_insert_operand (const aarch64_operand *self,
case 82:
case 159:
case 161:
- case 177:
case 178:
case 179:
case 180:
@@ -704,7 +703,8 @@ aarch64_insert_operand (const aarch64_operand *self,
case 182:
case 183:
case 184:
- case 204:
+ case 185:
+ case 205:
return aarch64_ins_imm (self, info, code, inst, errors);
case 43:
case 44:
@@ -842,21 +842,22 @@ aarch64_insert_operand (const aarch64_operand *self,
return aarch64_ins_sve_scale (self, info, code, inst, errors);
case 172:
case 173:
- return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
case 174:
+ return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
case 175:
case 176:
+ case 177:
return aarch64_ins_sve_shrimm (self, info, code, inst, errors);
- case 194:
case 195:
case 196:
case 197:
case 198:
+ case 199:
return aarch64_ins_sve_quad_index (self, info, code, inst, errors);
- case 200:
- return aarch64_ins_sve_index (self, info, code, inst, errors);
case 201:
- case 203:
+ return aarch64_ins_sve_index (self, info, code, inst, errors);
+ case 202:
+ case 204:
return aarch64_ins_sve_reglist (self, info, code, inst, errors);
default: assert (0); abort ();
}
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index 16faf59..3dccd6d 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -20069,7 +20069,6 @@ aarch64_extract_operand (const aarch64_operand *self,
case 169:
case 170:
case 171:
- case 185:
case 186:
case 187:
case 188:
@@ -20078,8 +20077,9 @@ aarch64_extract_operand (const aarch64_operand *self,
case 191:
case 192:
case 193:
- case 199:
- case 202:
+ case 194:
+ case 200:
+ case 203:
return aarch64_ext_regno (self, info, code, inst, errors);
case 9:
return aarch64_ext_regrt_sysins (self, info, code, inst, errors);
@@ -20095,7 +20095,7 @@ aarch64_extract_operand (const aarch64_operand *self,
case 32:
case 33:
case 34:
- case 205:
+ case 206:
return aarch64_ext_reglane (self, info, code, inst, errors);
case 35:
return aarch64_ext_reglist (self, info, code, inst, errors);
@@ -20132,7 +20132,6 @@ aarch64_extract_operand (const aarch64_operand *self,
case 82:
case 159:
case 161:
- case 177:
case 178:
case 179:
case 180:
@@ -20140,7 +20139,8 @@ aarch64_extract_operand (const aarch64_operand *self,
case 182:
case 183:
case 184:
- case 204:
+ case 185:
+ case 205:
return aarch64_ext_imm (self, info, code, inst, errors);
case 43:
case 44:
@@ -20280,21 +20280,22 @@ aarch64_extract_operand (const aarch64_operand *self,
return aarch64_ext_sve_scale (self, info, code, inst, errors);
case 172:
case 173:
- return aarch64_ext_sve_shlimm (self, info, code, inst, errors);
case 174:
+ return aarch64_ext_sve_shlimm (self, info, code, inst, errors);
case 175:
case 176:
+ case 177:
return aarch64_ext_sve_shrimm (self, info, code, inst, errors);
- case 194:
case 195:
case 196:
case 197:
case 198:
+ case 199:
return aarch64_ext_sve_quad_index (self, info, code, inst, errors);
- case 200:
- return aarch64_ext_sve_index (self, info, code, inst, errors);
case 201:
- case 203:
+ return aarch64_ext_sve_index (self, info, code, inst, errors);
+ case 202:
+ case 204:
return aarch64_ext_sve_reglist (self, info, code, inst, errors);
default: assert (0); abort ();
}
diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c
index 4aec870..178d210 100644
--- a/opcodes/aarch64-opc-2.c
+++ b/opcodes/aarch64-opc-2.c
@@ -198,6 +198,7 @@ const struct aarch64_operand aarch64_operands[] =
{AARCH64_OPND_CLASS_INT_REG, "SVE_Rn_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Rn}, "an integer register or SP"},
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHLIMM_PRED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_SVE_imm5}, "a shift-left immediate operand"},
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHLIMM_UNPRED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_imm5}, "a shift-left immediate operand"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHLIMM_UNPRED_22", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_sz, FLD_SVE_tszl_19, FLD_SVE_imm3}, "a shift-left immediate operand"},
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHRIMM_PRED", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_SVE_imm5}, "a shift-right immediate operand"},
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHRIMM_UNPRED", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_imm5}, "a shift-right immediate operand"},
{AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHRIMM_UNPRED_22", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_sz, FLD_SVE_tszl_19, FLD_SVE_imm3}, "a shift-right immediate operand"},
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index fac7111..00ff94d 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -2531,6 +2531,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
case AARCH64_OPND_SVE_SHLIMM_PRED:
case AARCH64_OPND_SVE_SHLIMM_UNPRED:
+ case AARCH64_OPND_SVE_SHLIMM_UNPRED_22:
size = aarch64_get_qualifier_esize (opnds[idx - 1].qualifier);
if (!value_in_range_p (opnd->imm.value, 0, 8 * size - 1))
{
@@ -3358,6 +3359,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
case AARCH64_OPND_SIMM5:
case AARCH64_OPND_SVE_SHLIMM_PRED:
case AARCH64_OPND_SVE_SHLIMM_UNPRED:
+ case AARCH64_OPND_SVE_SHLIMM_UNPRED_22:
case AARCH64_OPND_SVE_SHRIMM_PRED:
case AARCH64_OPND_SVE_SHRIMM_UNPRED:
case AARCH64_OPND_SVE_SHRIMM_UNPRED_22:
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index d45c2f6..eef7998 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -4923,6 +4923,9 @@ struct aarch64_opcode aarch64_opcode_table[] =
F(FLD_SVE_tszh,FLD_SVE_imm5), "a shift-left immediate operand") \
Y(IMMEDIATE, sve_shlimm, "SVE_SHLIMM_UNPRED", 0, \
F(FLD_SVE_tszh,FLD_imm5), "a shift-left immediate operand") \
+ Y(IMMEDIATE, sve_shlimm, "SVE_SHLIMM_UNPRED_22", 0, \
+ F(FLD_SVE_sz, FLD_SVE_tszl_19, FLD_SVE_imm3), \
+ "a shift-left immediate operand") \
Y(IMMEDIATE, sve_shrimm, "SVE_SHRIMM_PRED", 1 << OPD_F_OD_LSB, \
F(FLD_SVE_tszh,FLD_SVE_imm5), "a shift-right immediate operand") \
Y(IMMEDIATE, sve_shrimm, "SVE_SHRIMM_UNPRED", 1 << OPD_F_OD_LSB, \
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