[binutils-gdb] i386: Issue a warning to IRET without suffix for .code16gcc
H.J.Lu
hjl@sourceware.org
Thu May 2 17:50:00 GMT 2019
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=06f74c5cb868cfd37af3e680d29784c217700bdf
commit 06f74c5cb868cfd37af3e680d29784c217700bdf
Author: H.J. Lu <hjl.tools@gmail.com>
Date: Thu May 2 10:46:55 2019 -0700
i386: Issue a warning to IRET without suffix for .code16gcc
The .code16gcc directive to support 16-bit mode with 32-bit address.
For IRET without a suffix, generate 16-bit IRET with a warning to
return from an interrupt handler in 16-bit mode.
PR gas/24485
* config/tc-i386.c (process_suffix): Issue a warning to IRET
without a suffix for .code16gcc.
* testsuite/gas/i386/jump16.s: Add tests for iretX.
* testsuite/gas/i386/jump16.d: Updated.
* testsuite/gas/i386/jump16.e: New file.
Diff:
---
gas/ChangeLog | 9 +++++++++
gas/config/tc-i386.c | 20 +++++++++++++-------
gas/testsuite/gas/i386/jump16.d | 5 +++++
gas/testsuite/gas/i386/jump16.e | 3 +++
gas/testsuite/gas/i386/jump16.s | 16 ++++++++++++++++
5 files changed, 46 insertions(+), 7 deletions(-)
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 2dd2cf3..8a82fde 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,12 @@
+2019-05-02 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/24485
+ * config/tc-i386.c (process_suffix): Issue a warning to IRET
+ without a suffix for .code16gcc.
+ * testsuite/gas/i386/jump16.s: Add tests for iretX.
+ * testsuite/gas/i386/jump16.d: Updated.
+ * testsuite/gas/i386/jump16.e: New file.
+
2019-05-01 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (parse_operands): Add case for
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 032b1d3..7159432 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -6242,7 +6242,19 @@ process_suffix (void)
/* exclude fldenv/frstor/fsave/fstenv */
&& i.tm.opcode_modifier.no_ssuf)
{
- i.suffix = stackop_size;
+ if (stackop_size == LONG_MNEM_SUFFIX
+ && i.tm.base_opcode == 0xcf)
+ {
+ /* stackop_size is set to LONG_MNEM_SUFFIX for the
+ .code16gcc directive to support 16-bit mode with
+ 32-bit address. For IRET without a suffix, generate
+ 16-bit IRET (opcode 0xcf) to return from an interrupt
+ handler. */
+ i.suffix = WORD_MNEM_SUFFIX;
+ as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
+ }
+ else
+ i.suffix = stackop_size;
}
else if (intel_syntax
&& !i.suffix
@@ -6352,13 +6364,7 @@ process_suffix (void)
if (!add_prefix (ADDR_PREFIX_OPCODE))
return 0;
}
- /* stackop_size is set to LONG_MNEM_SUFFIX for the .code16gcc
- directive to support 16bit mode with 32-bit address. Since
- IRET (opcode 0xcf) in 16bit mode returns from an interrupt
- in 16bit mode, we shouldn't add DATA_PREFIX_OPCODE here. */
else if (i.suffix != QWORD_MNEM_SUFFIX
- && (stackop_size != LONG_MNEM_SUFFIX
- || i.tm.base_opcode != 0xcf)
&& !i.tm.opcode_modifier.ignoresize
&& !i.tm.opcode_modifier.floatmf
&& !i.tm.opcode_modifier.vex
diff --git a/gas/testsuite/gas/i386/jump16.d b/gas/testsuite/gas/i386/jump16.d
index 7a1dc76..c883eba 100644
--- a/gas/testsuite/gas/i386/jump16.d
+++ b/gas/testsuite/gas/i386/jump16.d
@@ -1,5 +1,6 @@
#name: i386 jump16
#objdump: -drw -mi8086
+#warning_output: jump16.e
.*: file format .*i386.*
@@ -69,4 +70,8 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: ea 00 00 90 90 ljmp \$0x9090,\$0x0 f2: (R_386_)?16 xxx
[ ]*[a-f0-9]+: cf iret
[ ]*[a-f0-9]+: cf iret
+[ ]*[a-f0-9]+: 66 cf iretl
+[ ]*[a-f0-9]+: cf iret
+[ ]*[a-f0-9]+: cf iret
+[ ]*[a-f0-9]+: 66 cf iretl
#pass
diff --git a/gas/testsuite/gas/i386/jump16.e b/gas/testsuite/gas/i386/jump16.e
new file mode 100644
index 0000000..2ad7ea0
--- /dev/null
+++ b/gas/testsuite/gas/i386/jump16.e
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*:77: Warning: generating 16-bit `iret' for .code16gcc directive
+.*:88: Warning: generating 16-bit `iret' for .code16gcc directive
diff --git a/gas/testsuite/gas/i386/jump16.s b/gas/testsuite/gas/i386/jump16.s
index aff5665..fb9e830 100644
--- a/gas/testsuite/gas/i386/jump16.s
+++ b/gas/testsuite/gas/i386/jump16.s
@@ -72,8 +72,24 @@
jmp 0x9090,xxx
jmp 0x9090:xxx
+ .att_syntax
.code16gcc
iret
+ iretw
+ iretl
.code16
iret
+ iretw
+ iretl
+
+ .intel_syntax noprefix
+.code16gcc
+ iret
+ iretw
+ iretd
+
+.code16
+ iret
+ iretw
+ iretd
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