[binutils-gdb] i386: Document memory size reference in assembler

[H.J.Lu]

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=aa108c0c462e43ab77a1f178d8c8d2277ac73a57

commit aa108c0c462e43ab77a1f178d8c8d2277ac73a57
Author: Lili Cui <lili.cui@intel.com>
Date:   Wed Jun 26 15:12:58 2019 -0700

    i386: Document memory size reference in assembler
    
    	* doc/c-i386.texi: Document x/y/z instruction sufffixes in AT&T
    	syntax and xmmword/ymmword/zmmword/fword/tbyte/oword ptr in
    	Intel syntax.

Diff:
---
 gas/ChangeLog       |  6 ++++++
 gas/doc/c-i386.texi | 15 ++++++++++-----
 2 files changed, 16 insertions(+), 5 deletions(-)

diff --git a/gas/ChangeLog b/gas/ChangeLog
index bcc193e..c1b4625 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,9 @@
+2019-06-26  Lili Cui  <lili.cui@intel.com>
+
+	* doc/c-i386.texi: Document x/y/z instruction sufffixes in AT&T
+	syntax and xmmword/ymmword/zmmword/fword/tbyte/oword ptr in
+	Intel syntax.
+
 2019-06-25  Faraz Shahbazker  <fshahbazker@wavecomp.com>
 
 	* config/tc-mips.c (macro) <M_LI>: Re-order MTHC1 with
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index 908c6ca..80bbcbe 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -590,11 +590,16 @@ instruction, do @emph{not} have reversed order.  @ref{i386-Bugs}.
 In AT&T syntax the size of memory operands is determined from the last
 character of the instruction mnemonic.  Mnemonic suffixes of @samp{b},
 @samp{w}, @samp{l} and @samp{q} specify byte (8-bit), word (16-bit), long
-(32-bit) and quadruple word (64-bit) memory references.  Intel syntax accomplishes
-this by prefixing memory operands (@emph{not} the instruction mnemonics) with
-@samp{byte ptr}, @samp{word ptr}, @samp{dword ptr} and @samp{qword ptr}.  Thus,
-Intel @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T
-syntax.
+(32-bit) and quadruple word (64-bit) memory references.  Mnemonic suffixes
+of @samp{x}, @samp{y} and @samp{z} specify xmm (128-bit vector), ymm
+(256-bit vector) and zmm (512-bit vector) memory references, only when there's
+no other way to disambiguate an instruction.  Intel syntax accomplishes this by
+prefixing memory operands (@emph{not} the instruction mnemonics) with
+@samp{byte ptr}, @samp{word ptr}, @samp{dword ptr}, @samp{qword ptr},
+@samp{xmmword ptr}, @samp{ymmword ptr} and @samp{zmmword ptr}.  Thus, Intel
+syntax @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T
+syntax.  In Intel syntax, @samp{fword ptr}, @samp{tbyte ptr} and
+@samp{oword ptr} specify 48-bit, 80-bit and 128-bit memory references.
 
 In 64-bit code, @samp{movabs} can be used to encode the @samp{mov}
 instruction with the 64-bit displacement or immediate operand.