[binutils-gdb] x86: Set VexW=3 on AVX vrsqrtss

[H.J.Lu]

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=db4cc66567397498a9e9eaedb8d0bb8889744ef7

commit db4cc66567397498a9e9eaedb8d0bb8889744ef7
Author: H.J. Lu <hjl.tools@gmail.com>
Date:   Sat Sep 15 17:09:08 2018 -0700

    x86: Set VexW=3 on AVX vrsqrtss
    
    AVX vrsqrtss is a VEX WIG instruction.
    
    	* i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
    	* i386-tbl.h: Regenerated.

Diff:
---
 opcodes/ChangeLog    | 5 +++++
 opcodes/i386-opc.tbl | 2 +-
 opcodes/i386-tbl.h   | 2 +-
 3 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 408512c..ca03df8 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,10 @@
 2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
 
+	* i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
+	* i386-tbl.h: Regenerated.
+
+2018-09-15  H.J. Lu  <hongjiu.lu@intel.com>
+
 	PR gas/23665
 	* i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
 	VEX_LEN_0FD6_P_2 entries.
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index d37a08c..d8fe824 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -2195,7 +2195,7 @@ vroundps, 3, 0x6608, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=3|CheckRegSize|
 vroundsd, 4, 0x660b, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=2|VexVVVV=1|VexW=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, Qword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
 vroundss, 4, 0x660a, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=2|VexVVVV=1|VexW=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
 vrsqrtps, 2, 0x52, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=3|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
-vrsqrtss, 3, 0xf352, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
+vrsqrtss, 3, 0xf352, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM }
 vshufpd, 4, 0x66c6, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=3|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
 vshufps, 4, 0xc6, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=3|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM }
 vsqrtpd, 2, 0x6651, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=3|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM }
diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index f99daa0..0b1d2a4 100644
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -45524,7 +45524,7 @@ const insn_template i386_optab[] =
         0, 0, 0, 0, 0, 0 } },
     { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-      3, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+      3, 1, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
       0, 0 },
     { { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
 	  0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0,