https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=2ac435d46608be7ef90f80aaf9ff48443aea571e
commit 2ac435d46608be7ef90f80aaf9ff48443aea571e
Author: Sudakshina Das <sudi.das@arm.com>
Date: Wed Sep 26 10:52:51 2018 +0100
[PATCH, BINUTILS, AARCH64, 4/9] Add Execution and Data Restriction instructions
This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order)
This patch adds the prediction restriction instructions (that is, cfp,
dvp, cpp). These instructions are retrospectively made optional for
all versions of the architecture from ARMv8.0 to ARMv8.4 and is
mandatory from ARMv8.5. Hence adding a new +predres which can be used
by the older architectures.
*** include/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_PREDRES): New.
(AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_PREDRES by default.
(aarch64_opnd): Add AARCH64_OPND_SYSREG_SR.
(aarch64_sys_regs_sr): Declare new table.
*** opcodes/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* aarch64-dis.c (aarch64_ext_sysins_op): Add case for
AARCH64_OPND_SYSREG_SR.
* aarch64-opc.c (aarch64_print_operand): Likewise.
(aarch64_sys_regs_sr): Define table.
(aarch64_sys_ins_reg_supported_p): Check for RCTX with
AARCH64_FEATURE_PREDRES.
* aarch64-tbl.h (aarch64_feature_predres): New.
(PREDRES, PREDRES_INSN): New.
(aarch64_opcode_table): Add entries for cfp, dvp and cpp.
(AARCH64_OPERANDS): Add new description for SYSREG_SR.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
*** gas/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (aarch64_sys_regs_sr_hsh): New.
(parse_operands): Add entry for AARCH64_OPND_SYSREG_SR.
(md_begin): Allocate and initialize aarch64_sys_regs_sr_hsh
with aarch64_sys_regs_sr.
(aarch64_features): Add new "predres" option for older
architectures.
* doc/c-aarch64.texi: Document the same.
* testsuite/gas/aarch64/sysreg-4.s: New.
* testsuite/gas/aarch64/sysreg-4.d: New.
* testsuite/gas/aarch64/illegal-sysreg-4.d: New.
* testsuite/gas/aarch64/illegal-sysreg-4.l: New.
* testsuite/gas/aarch64/predres.s: New.
* testsuite/gas/aarch64/predres.d: New.
Diff:
---
gas/ChangeLog | 16 +
gas/config/tc-aarch64.c | 17 +
gas/doc/c-aarch64.texi | 2 +
gas/testsuite/gas/aarch64/illegal-sysreg-4.d | 3 +
gas/testsuite/gas/aarch64/illegal-sysreg-4.l | 7 +
gas/testsuite/gas/aarch64/predres.d | 11 +
gas/testsuite/gas/aarch64/predres.s | 5 +
gas/testsuite/gas/aarch64/sysreg-4.d | 12 +
gas/testsuite/gas/aarch64/sysreg-4.s | 5 +
include/ChangeLog | 7 +
include/opcode/aarch64.h | 7 +-
opcodes/ChangeLog | 16 +
opcodes/aarch64-asm-2.c | 274 ++--
opcodes/aarch64-dis-2.c | 1896 +++++++++++++-------------
opcodes/aarch64-dis.c | 6 +
opcodes/aarch64-opc-2.c | 17 +-
opcodes/aarch64-opc.c | 17 +
opcodes/aarch64-tbl.h | 10 +
18 files changed, 1238 insertions(+), 1090 deletions(-)
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 9a83fad..6fa3e72 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,21 @@
2018-10-09 Sudakshina Das <sudi.das@arm.com>
+ * config/tc-aarch64.c (aarch64_sys_regs_sr_hsh): New.
+ (parse_operands): Add entry for AARCH64_OPND_SYSREG_SR.
+ (md_begin): Allocate and initialize aarch64_sys_regs_sr_hsh
+ with aarch64_sys_regs_sr.
+ (aarch64_features): Add new "predres" option for older
+ architectures.
+ * doc/c-aarch64.texi: Document the same.
+ * testsuite/gas/aarch64/sysreg-4.s: New.
+ * testsuite/gas/aarch64/sysreg-4.d: New.
+ * testsuite/gas/aarch64/illegal-sysreg-4.d: New.
+ * testsuite/gas/aarch64/illegal-sysreg-4.l: New.
+ * testsuite/gas/aarch64/predres.s: New.
+ * testsuite/gas/aarch64/predres.d: New.
+
+2018-10-09 Sudakshina Das <sudi.das@arm.com>
+
* config/tc-aarch64.c (aarch64_features): Add new "sb" option
for older architectures.
* doc/c-aarch64.texi: Document the same.
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 045ad52..8621a33 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -462,6 +462,7 @@ static struct hash_control *aarch64_sys_regs_ic_hsh;
static struct hash_control *aarch64_sys_regs_dc_hsh;
static struct hash_control *aarch64_sys_regs_at_hsh;
static struct hash_control *aarch64_sys_regs_tlbi_hsh;
+static struct hash_control *aarch64_sys_regs_sr_hsh;
static struct hash_control *aarch64_reg_hsh;
static struct hash_control *aarch64_barrier_opt_hsh;
static struct hash_control *aarch64_nzcv_hsh;
@@ -6422,14 +6423,22 @@ parse_operands (char *str, const aarch64_opcode *opcode)
inst.base.operands[i].sysins_op =
parse_sys_ins_reg (&str, aarch64_sys_regs_ic_hsh);
goto sys_reg_ins;
+
case AARCH64_OPND_SYSREG_DC:
inst.base.operands[i].sysins_op =
parse_sys_ins_reg (&str, aarch64_sys_regs_dc_hsh);
goto sys_reg_ins;
+
case AARCH64_OPND_SYSREG_AT:
inst.base.operands[i].sysins_op =
parse_sys_ins_reg (&str, aarch64_sys_regs_at_hsh);
goto sys_reg_ins;
+
+ case AARCH64_OPND_SYSREG_SR:
+ inst.base.operands[i].sysins_op =
+ parse_sys_ins_reg (&str, aarch64_sys_regs_sr_hsh);
+ goto sys_reg_ins;
+
case AARCH64_OPND_SYSREG_TLBI:
inst.base.operands[i].sysins_op =
parse_sys_ins_reg (&str, aarch64_sys_regs_tlbi_hsh);
@@ -8439,6 +8448,7 @@ md_begin (void)
|| (aarch64_sys_regs_dc_hsh = hash_new ()) == NULL
|| (aarch64_sys_regs_at_hsh = hash_new ()) == NULL
|| (aarch64_sys_regs_tlbi_hsh = hash_new ()) == NULL
+ || (aarch64_sys_regs_sr_hsh = hash_new ()) == NULL
|| (aarch64_reg_hsh = hash_new ()) == NULL
|| (aarch64_barrier_opt_hsh = hash_new ()) == NULL
|| (aarch64_nzcv_hsh = hash_new ()) == NULL
@@ -8477,6 +8487,11 @@ md_begin (void)
aarch64_sys_regs_tlbi[i].name,
(void *) (aarch64_sys_regs_tlbi + i));
+ for (i = 0; aarch64_sys_regs_sr[i].name != NULL; i++)
+ checked_hash_insert (aarch64_sys_regs_sr_hsh,
+ aarch64_sys_regs_sr[i].name,
+ (void *) (aarch64_sys_regs_sr + i));
+
for (i = 0; i < ARRAY_SIZE (reg_names); i++)
checked_hash_insert (aarch64_reg_hsh, reg_names[i].name,
(void *) (reg_names + i));
@@ -8749,6 +8764,8 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
AARCH64_ARCH_NONE},
{"sb", AARCH64_FEATURE (AARCH64_FEATURE_SB, 0),
AARCH64_ARCH_NONE},
+ {"predres", AARCH64_FEATURE (AARCH64_FEATURE_PREDRES, 0),
+ AARCH64_ARCH_NONE},
{"aes", AARCH64_FEATURE (AARCH64_FEATURE_AES, 0),
AARCH64_ARCH_NONE},
{"sm4", AARCH64_FEATURE (AARCH64_FEATURE_SM4, 0),
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 8a116a4..dd5fbf4 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -183,6 +183,8 @@ automatically cause those extensions to be disabled.
This implies @code{fp16}.
@item @code{sb} @tab ARMv8-A @tab ARMv8.5-A or later
@tab Enable the speculation barrier instruction sb.
+@item @code{predres} @tab ARMv8-A @tab ARMv8.5-A or later
+ @tab Enable the Execution and Data and Prediction instructions.
@end multitable
@node AArch64 Syntax
diff --git a/gas/testsuite/gas/aarch64/illegal-sysreg-4.d b/gas/testsuite/gas/aarch64/illegal-sysreg-4.d
new file mode 100644
index 0000000..e181566
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-sysreg-4.d
@@ -0,0 +1,3 @@
+#as: -march=armv8-a
+#source: sysreg-4.s
+#error_output: illegal-sysreg-4.l
diff --git a/gas/testsuite/gas/aarch64/illegal-sysreg-4.l b/gas/testsuite/gas/aarch64/illegal-sysreg-4.l
new file mode 100644
index 0000000..68471a1
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-sysreg-4.l
@@ -0,0 +1,7 @@
+[^:]*: Assembler messages:
+[^:]*:[0-9]+: Error: selected processor does not support system register name 'rctx'
+[^:]*:[0-9]+: Error: selected processor does not support `cfp rctx,x1'
+[^:]*:[0-9]+: Error: selected processor does not support system register name 'rctx'
+[^:]*:[0-9]+: Error: selected processor does not support `dvp rctx,x2'
+[^:]*:[0-9]+: Error: selected processor does not support system register name 'rctx'
+[^:]*:[0-9]+: Error: selected processor does not support `cpp rctx,x3'
diff --git a/gas/testsuite/gas/aarch64/predres.d b/gas/testsuite/gas/aarch64/predres.d
new file mode 100644
index 0000000..e4f13a0
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/predres.d
@@ -0,0 +1,11 @@
+#as: -march=armv8-a+predres
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+.*: d50b7381 cfp rctx, x1
+.*: d50b73a2 dvp rctx, x2
+.*: d50b73e3 cpp rctx, x3
diff --git a/gas/testsuite/gas/aarch64/predres.s b/gas/testsuite/gas/aarch64/predres.s
new file mode 100644
index 0000000..55ad909
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/predres.s
@@ -0,0 +1,5 @@
+/* File to test the +predres option. */
+func:
+ cfp rctx, x1
+ dvp rctx, x2
+ cpp rctx, x3
diff --git a/gas/testsuite/gas/aarch64/sysreg-4.d b/gas/testsuite/gas/aarch64/sysreg-4.d
new file mode 100644
index 0000000..f3ea5d1
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sysreg-4.d
@@ -0,0 +1,12 @@
+#source: sysreg-4.s
+#as: -march=armv8.5-a
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+.*: d50b7381 cfp rctx, x1
+.*: d50b73a2 dvp rctx, x2
+.*: d50b73e3 cpp rctx, x3
diff --git a/gas/testsuite/gas/aarch64/sysreg-4.s b/gas/testsuite/gas/aarch64/sysreg-4.s
new file mode 100644
index 0000000..6ec069a
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sysreg-4.s
@@ -0,0 +1,5 @@
+/* sysreg-4.s Test file for ARMv8.5 system registers. */
+func:
+ cfp rctx, x1
+ dvp rctx, x2
+ cpp rctx, x3
diff --git a/include/ChangeLog b/include/ChangeLog
index 679a34d..be7072a 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,5 +1,12 @@
2018-10-09 Sudakshina Das <sudi.das@arm.com>
+ * opcode/aarch64.h (AARCH64_FEATURE_PREDRES): New.
+ (AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_PREDRES by default.
+ (aarch64_opnd): Add AARCH64_OPND_SYSREG_SR.
+ (aarch64_sys_regs_sr): Declare new table.
+
+2018-10-09 Sudakshina Das <sudi.das@arm.com>
+
* opcode/aarch64.h (AARCH64_FEATURE_SB): New.
(AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_SB by default.
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 7e113e4..7b542c9 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -70,6 +70,8 @@ typedef uint32_t aarch64_insn;
#define AARCH64_FEATURE_FRINTTS 0x8000000000ULL
/* SB instruction. */
#define AARCH64_FEATURE_SB 0x10000000000ULL
+/* Execution and Data Prediction Restriction instructions. */
+#define AARCH64_FEATURE_PREDRES 0x20000000000ULL
/* Architectures are the sum of the base and extensions. */
#define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
@@ -97,7 +99,8 @@ typedef uint32_t aarch64_insn;
AARCH64_FEATURE_V8_5 \
| AARCH64_FEATURE_FLAGMANIP \
| AARCH64_FEATURE_FRINTTS \
- | AARCH64_FEATURE_SB)
+ | AARCH64_FEATURE_SB \
+ | AARCH64_FEATURE_PREDRES)
#define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0)
@@ -272,6 +275,7 @@ enum aarch64_opnd
AARCH64_OPND_SYSREG_DC, /* System register <dc_op> operand. */
AARCH64_OPND_SYSREG_IC, /* System register <ic_op> operand. */
AARCH64_OPND_SYSREG_TLBI, /* System register <tlbi_op> operand. */
+ AARCH64_OPND_SYSREG_SR, /* System register RCTX operand. */
AARCH64_OPND_BARRIER, /* Barrier operand. */
AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */
AARCH64_OPND_PRFOP, /* Prefetch operation. */
@@ -915,6 +919,7 @@ extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
+extern const aarch64_sys_ins_reg aarch64_sys_regs_sr [];
/* Shift/extending operator kinds.
N.B. order is important; keep aarch64_operand_modifiers synced. */
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 935b832..8a5cbf5 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,21 @@
2018-10-09 Sudakshina Das <sudi.das@arm.com>
+ * aarch64-dis.c (aarch64_ext_sysins_op): Add case for
+ AARCH64_OPND_SYSREG_SR.
+ * aarch64-opc.c (aarch64_print_operand): Likewise.
+ (aarch64_sys_regs_sr): Define table.
+ (aarch64_sys_ins_reg_supported_p): Check for RCTX with
+ AARCH64_FEATURE_PREDRES.
+ * aarch64-tbl.h (aarch64_feature_predres): New.
+ (PREDRES, PREDRES_INSN): New.
+ (aarch64_opcode_table): Add entries for cfp, dvp and cpp.
+ (AARCH64_OPERANDS): Add new description for SYSREG_SR.
+ * aarch64-asm-2.c: Regenerate.
+ * aarch64-dis-2.c: Regenerate.
+ * aarch64-opc-2.c: Regenerate.
+
+2018-10-09 Sudakshina Das <sudi.das@arm.com>
+
* aarch64-tbl.h (aarch64_feature_sb): New.
(SB, SB_INSN): New.
(aarch64_opcode_table): Add entry for sb.
diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
index 7ad929e..221513a 100644
--- a/opcodes/aarch64-asm-2.c
+++ b/opcodes/aarch64-asm-2.c
@@ -422,14 +422,14 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
case 1162: /* movz */
value = 1162; /* --> movz. */
break;
- case 1205: /* autibsp */
- case 1204: /* autibz */
- case 1203: /* autiasp */
- case 1202: /* autiaz */
- case 1201: /* pacibsp */
- case 1200: /* pacibz */
- case 1199: /* paciasp */
- case 1198: /* paciaz */
+ case 1208: /* autibsp */
+ case 1207: /* autibz */
+ case 1206: /* autiasp */
+ case 1205: /* autiaz */
+ case 1204: /* pacibsp */
+ case 1203: /* pacibz */
+ case 1202: /* paciasp */
+ case 1201: /* paciaz */
case 1182: /* psb */
case 1181: /* esb */
case 1180: /* autib1716 */
@@ -452,6 +452,9 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
case 1184: /* dsb */
value = 1184; /* --> dsb. */
break;
+ case 1197: /* cpp */
+ case 1196: /* dvp */
+ case 1195: /* cfp */
case 1194: /* tlbi */
case 1193: /* ic */
case 1192: /* dc */
@@ -459,124 +462,124 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
case 1190: /* sys */
value = 1190; /* --> sys. */
break;
- case 2003: /* bic */
- case 1253: /* and */
- value = 1253; /* --> and. */
+ case 2006: /* bic */
+ case 1256: /* and */
+ value = 1256; /* --> and. */
break;
- case 1236: /* mov */
- case 1255: /* and */
- value = 1255; /* --> and. */
- break;
- case 1240: /* movs */
- case 1256: /* ands */
- value = 1256; /* --> ands. */
+ case 1239: /* mov */
+ case 1258: /* and */
+ value = 1258; /* --> and. */
break;
- case 2004: /* cmple */
- case 1291: /* cmpge */
- value = 1291; /* --> cmpge. */
+ case 1243: /* movs */
+ case 1259: /* ands */
+ value = 1259; /* --> ands. */
break;
- case 2007: /* cmplt */
- case 1294: /* cmpgt */
- value = 1294; /* --> cmpgt. */
+ case 2007: /* cmple */
+ case 1294: /* cmpge */
+ value = 1294; /* --> cmpge. */
break;
- case 2005: /* cmplo */
- case 1296: /* cmphi */
- value = 1296; /* --> cmphi. */
+ case 2010: /* cmplt */
+ case 1297: /* cmpgt */
+ value = 1297; /* --> cmpgt. */
break;
- case 2006: /* cmpls */
- case 1299: /* cmphs */
- value = 1299; /* --> cmphs. */
+ case 2008: /* cmplo */
+ case 1299: /* cmphi */
+ value = 1299; /* --> cmphi. */
break;
- case 1233: /* mov */
- case 1321: /* cpy */
- value = 1321; /* --> cpy. */
+ case 2009: /* cmpls */
+ case 1302: /* cmphs */
+ value = 1302; /* --> cmphs. */
break;
- case 1235: /* mov */
- case 1322: /* cpy */
- value = 1322; /* --> cpy. */
+ case 1236: /* mov */
+ case 1324: /* cpy */
+ value = 1324; /* --> cpy. */
break;
- case 2014: /* fmov */
case 1238: /* mov */
- case 1323: /* cpy */
- value = 1323; /* --> cpy. */
- break;
- case 1228: /* mov */
- case 1335: /* dup */
- value = 1335; /* --> dup. */
+ case 1325: /* cpy */
+ value = 1325; /* --> cpy. */
break;
- case 1230: /* mov */
- case 1227: /* mov */
- case 1336: /* dup */
- value = 1336; /* --> dup. */
- break;
- case 2013: /* fmov */
- case 1232: /* mov */
- case 1337: /* dup */
- value = 1337; /* --> dup. */
+ case 2017: /* fmov */
+ case 1241: /* mov */
+ case 1326: /* cpy */
+ value = 1326; /* --> cpy. */
break;
case 1231: /* mov */
- case 1338: /* dupm */
- value = 1338; /* --> dupm. */
+ case 1338: /* dup */
+ value = 1338; /* --> dup. */
break;
- case 2008: /* eon */
- case 1340: /* eor */
- value = 1340; /* --> eor. */
+ case 1233: /* mov */
+ case 1230: /* mov */
+ case 1339: /* dup */
+ value = 1339; /* --> dup. */
break;
- case 1241: /* not */
- case 1342: /* eor */
- value = 1342; /* --> eor. */
+ case 2016: /* fmov */
+ case 1235: /* mov */
+ case 1340: /* dup */
+ value = 1340; /* --> dup. */
break;
- case 1242: /* nots */
- case 1343: /* eors */
- value = 1343; /* --> eors. */
+ case 1234: /* mov */
+ case 1341: /* dupm */
+ value = 1341; /* --> dupm. */
break;
- case 2009: /* facle */
- case 1348: /* facge */
- value = 1348; /* --> facge. */
+ case 2011: /* eon */
+ case 1343: /* eor */
+ value = 1343; /* --> eor. */
break;
- case 2010: /* faclt */
- case 1349: /* facgt */
- value = 1349; /* --> facgt. */
+ case 1244: /* not */
+ case 1345: /* eor */
+ value = 1345; /* --> eor. */
break;
- case 2011: /* fcmle */
- case 1362: /* fcmge */
- value = 1362; /* --> fcmge. */
+ case 1245: /* nots */
+ case 1346: /* eors */
+ value = 1346; /* --> eors. */
break;
- case 2012: /* fcmlt */
- case 1364: /* fcmgt */
- value = 1364; /* --> fcmgt. */
+ case 2012: /* facle */
+ case 1351: /* facge */
+ value = 1351; /* --> facge. */
break;
- case 1225: /* fmov */
- case 1370: /* fcpy */
- value = 1370; /* --> fcpy. */
+ case 2013: /* faclt */
+ case 1352: /* facgt */
+ value = 1352; /* --> facgt. */
break;
- case 1224: /* fmov */
- case 1393: /* fdup */
- value = 1393; /* --> fdup. */
+ case 2014: /* fcmle */
+ case 1365: /* fcmge */
+ value = 1365; /* --> fcmge. */
break;
- case 1226: /* mov */
- case 1724: /* orr */
- value = 1724; /* --> orr. */
+ case 2015: /* fcmlt */
+ case 1367: /* fcmgt */
+ value = 1367; /* --> fcmgt. */
break;
- case 2015: /* orn */
- case 1725: /* orr */
- value = 1725; /* --> orr. */
+ case 1228: /* fmov */
+ case 1373: /* fcpy */
+ value = 1373; /* --> fcpy. */
+ break;
+ case 1227: /* fmov */
+ case 1396: /* fdup */
+ value = 1396; /* --> fdup. */
break;
case 1229: /* mov */
case 1727: /* orr */
value = 1727; /* --> orr. */
break;
- case 1239: /* movs */
- case 1728: /* orrs */
- value = 1728; /* --> orrs. */
+ case 2018: /* orn */
+ case 1728: /* orr */
+ value = 1728; /* --> orr. */
break;
- case 1234: /* mov */
- case 1790: /* sel */
- value = 1790; /* --> sel. */
+ case 1232: /* mov */
+ case 1730: /* orr */
+ value = 1730; /* --> orr. */
+ break;
+ case 1242: /* movs */
+ case 1731: /* orrs */
+ value = 1731; /* --> orrs. */
break;
case 1237: /* mov */
- case 1791: /* sel */
- value = 1791; /* --> sel. */
+ case 1793: /* sel */
+ value = 1793; /* --> sel. */
+ break;
+ case 1240: /* mov */
+ case 1794: /* sel */
+ value = 1794; /* --> sel. */
break;
default: return NULL;
}
@@ -619,7 +622,6 @@ aarch64_insert_operand (const aarch64_operand *self,
case 27:
case 28:
case 29:
- case 153:
case 154:
case 155:
case 156:
@@ -629,7 +631,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case 160:
case 161:
case 162:
- case 175:
+ case 163:
case 176:
case 177:
case 178:
@@ -638,8 +640,9 @@ aarch64_insert_operand (const aarch64_operand *self,
case 181:
case 182:
case 183:
- case 187:
- case 190:
+ case 184:
+ case 188:
+ case 191:
return aarch64_ins_regno (self, info, code, inst, errors);
case 13:
return aarch64_ins_reg_extended (self, info, code, inst, errors);
@@ -651,7 +654,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case 31:
case 32:
case 33:
- case 192:
+ case 193:
return aarch64_ins_reglane (self, info, code, inst, errors);
case 34:
return aarch64_ins_reglist (self, info, code, inst, errors);
@@ -683,9 +686,8 @@ aarch64_insert_operand (const aarch64_operand *self,
case 77:
case 78:
case 79:
- case 150:
- case 152:
- case 167:
+ case 151:
+ case 153:
case 168:
case 169:
case 170:
@@ -693,6 +695,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case 172:
case 173:
case 174:
+ case 175:
return aarch64_ins_imm (self, info, code, inst, errors);
case 42:
case 43:
@@ -702,10 +705,10 @@ aarch64_insert_operand (const aarch64_operand *self,
case 46:
return aarch64_ins_advsimd_imm_modified (self, info, code, inst, errors);
case 50:
- case 141:
+ case 142:
return aarch64_ins_fpimm (self, info, code, inst, errors);
case 65:
- case 148:
+ case 149:
return aarch64_ins_limm (self, info, code, inst, errors);
case 66:
return aarch64_ins_aimm (self, info, code, inst, errors);
@@ -715,10 +718,10 @@ aarch64_insert_operand (const aarch64_operand *self,
return aarch64_ins_fbits (self, info, code, inst, errors);
case 70:
case 71:
- case 146:
+ case 147:
return aarch64_ins_imm_rotate2 (self, info, code, inst, errors);
case 72:
- case 145:
+ case 146:
return aarch64_ins_imm_rotate1 (self, info, code, inst, errors);
case 73:
case 74:
@@ -748,31 +751,31 @@ aarch64_insert_operand (const aarch64_operand *self,
case 93:
case 94:
case 95:
- return aarch64_ins_sysins_op (self, info, code, inst, errors);
case 96:
+ return aarch64_ins_sysins_op (self, info, code, inst, errors);
case 97:
- return aarch64_ins_barrier (self, info, code, inst, errors);
case 98:
- return aarch64_ins_prfop (self, info, code, inst, errors);
+ return aarch64_ins_barrier (self, info, code, inst, errors);
case 99:
- return aarch64_ins_hint (self, info, code, inst, errors);
+ return aarch64_ins_prfop (self, info, code, inst, errors);
case 100:
- return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors);
+ return aarch64_ins_hint (self, info, code, inst, errors);
case 101:
+ return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors);
case 102:
case 103:
case 104:
- return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors);
case 105:
- return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors);
+ return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors);
case 106:
- return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors);
+ return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors);
case 107:
+ return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors);
case 108:
case 109:
case 110:
- return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors);
case 111:
+ return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors);
case 112:
case 113:
case 114:
@@ -785,8 +788,8 @@ aarch64_insert_operand (const aarch64_operand *self,
case 121:
case 122:
case 123:
- return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors);
case 124:
+ return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors);
case 125:
case 126:
case 127:
@@ -794,48 +797,49 @@ aarch64_insert_operand (const aarch64_operand *self,
case 129:
case 130:
case 131:
- return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors);
case 132:
+ return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors);
case 133:
case 134:
case 135:
- return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors);
case 136:
- return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors);
+ return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors);
case 137:
- return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors);
+ return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors);
case 138:
- return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors);
+ return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors);
case 139:
- return aarch64_ins_sve_aimm (self, info, code, inst, errors);
+ return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors);
case 140:
+ return aarch64_ins_sve_aimm (self, info, code, inst, errors);
+ case 141:
return aarch64_ins_sve_asimm (self, info, code, inst, errors);
- case 142:
- return aarch64_ins_sve_float_half_one (self, info, code, inst, errors);
case 143:
- return aarch64_ins_sve_float_half_two (self, info, code, inst, errors);
+ return aarch64_ins_sve_float_half_one (self, info, code, inst, errors);
case 144:
+ return aarch64_ins_sve_float_half_two (self, info, code, inst, errors);
+ case 145:
return aarch64_ins_sve_float_zero_one (self, info, code, inst, errors);
- case 147:
+ case 148:
return aarch64_ins_inv_limm (self, info, code, inst, errors);
- case 149:
+ case 150:
return aarch64_ins_sve_limm_mov (self, info, code, inst, errors);
- case 151:
+ case 152:
return aarch64_ins_sve_scale (self, info, code, inst, errors);
- case 163:
case 164:
- return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
case 165:
+ return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
case 166:
+ case 167:
return aarch64_ins_sve_shrimm (self, info, code, inst, errors);
- case 184:
case 185:
case 186:
+ case 187:
return aarch64_ins_sve_quad_index (self, info, code, inst, errors);
- case 188:
- return aarch64_ins_sve_index (self, info, code, inst, errors);
case 189:
- case 191:
+ return aarch64_ins_sve_index (self, info, code, inst, errors);
+ case 190:
+ case 192:
return aarch64_ins_sve_reglist (self, info, code, inst, errors);
default: assert (0); abort ();
}
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index d174f74..4b54e32 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -2340,7 +2340,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0001100100xxxxxxxxxxxxxxxxxxxxxx
stlurb. */
- return 2057;
+ return 2060;
}
else
{
@@ -2348,7 +2348,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
1001100100xxxxxxxxxxxxxxxxxxxxxx
stlur. */
- return 2065;
+ return 2068;
}
}
else
@@ -2359,7 +2359,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0101100100xxxxxxxxxxxxxxxxxxxxxx
stlurh. */
- return 2061;
+ return 2064;
}
else
{
@@ -2367,7 +2367,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
1101100100xxxxxxxxxxxxxxxxxxxxxx
stlur. */
- return 2068;
+ return 2071;
}
}
}
@@ -2414,7 +2414,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0001100101xxxxxxxxxxxxxxxxxxxxxx
ldapurb. */
- return 2058;
+ return 2061;
}
else
{
@@ -2422,7 +2422,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
1001100101xxxxxxxxxxxxxxxxxxxxxx
ldapur. */
- return 2066;
+ return 2069;
}
}
else
@@ -2433,7 +2433,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0101100101xxxxxxxxxxxxxxxxxxxxxx
ldapurh. */
- return 2062;
+ return 2065;
}
else
{
@@ -2441,7 +2441,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
1101100101xxxxxxxxxxxxxxxxxxxxxx
ldapur. */
- return 2069;
+ return 2072;
}
}
}
@@ -2491,7 +2491,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
0001100110xxxxxxxxxxxxxxxxxxxxxx
ldapursb. */
- return 2060;
+ return 2063;
}
else
{
@@ -2499,7 +2499,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
1001100110xxxxxxxxxxxxxxxxxxxxxx
ldapursw. */
- return 2067;
+ return 2070;
}
}
else
@@ -2508,7 +2508,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x101100110xxxxxxxxxxxxxxxxxxxxxx
ldapursh. */
- return 2064;
+ return 2067;
}
}
else
@@ -2519,7 +2519,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x001100111xxxxxxxxxxxxxxxxxxxxxx
ldapursb. */
- return 2059;
+ return 2062;
}
else
{
@@ -2527,7 +2527,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x101100111xxxxxxxxxxxxxxxxxxxxxx
ldapursh. */
- return 2063;
+ return 2066;
}
}
}
@@ -2920,7 +2920,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx11010x00xxxxxx0xx10xxxxxxxxxx
setf8. */
- return 2055;
+ return 2058;
}
else
{
@@ -2928,7 +2928,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx11010x00xxxxxx1xx10xxxxxxxxxx
setf16. */
- return 2056;
+ return 2059;
}
}
else
@@ -3074,7 +3074,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
xxx11010000xxxxxxxxx01xxxxxxxxxx
rmif. */
- return 2054;
+ return 2057;
}
else
{
@@ -3601,7 +3601,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx000000000xxxxxxxxxxxxx
add. */
- return 1246;
+ return 1249;
}
else
{
@@ -3609,7 +3609,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx010000000xxxxxxxxxxxxx
mul. */
- return 1715;
+ return 1718;
}
}
else
@@ -3620,7 +3620,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx001000000xxxxxxxxxxxxx
smax. */
- return 1794;
+ return 1797;
}
else
{
@@ -3628,7 +3628,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx011000000xxxxxxxxxxxxx
orr. */
- return 1726;
+ return 1729;
}
}
}
@@ -3640,7 +3640,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx0x0100000xxxxxxxxxxxxx
sdiv. */
- return 1785;
+ return 1788;
}
else
{
@@ -3648,7 +3648,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx0x1100000xxxxxxxxxxxxx
sabd. */
- return 1776;
+ return 1779;
}
}
}
@@ -3662,7 +3662,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx0x0010000xxxxxxxxxxxxx
smulh. */
- return 1799;
+ return 1802;
}
else
{
@@ -3672,7 +3672,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx001010000xxxxxxxxxxxxx
smin. */
- return 1797;
+ return 1800;
}
else
{
@@ -3680,7 +3680,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx011010000xxxxxxxxxxxxx
and. */
- return 1254;
+ return 1257;
}
}
}
@@ -3690,7 +3690,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx0xx110000xxxxxxxxxxxxx
sdivr. */
- return 1786;
+ return 1789;
}
}
}
@@ -3706,7 +3706,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx0x0001000xxxxxxxxxxxxx
sub. */
- return 1915;
+ return 1918;
}
else
{
@@ -3716,7 +3716,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx001001000xxxxxxxxxxxxx
umax. */
- return 1943;
+ return 1946;
}
else
{
@@ -3724,7 +3724,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx011001000xxxxxxxxxxxxx
eor. */
- return 1341;
+ return 1344;
}
}
}
@@ -3736,7 +3736,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx0x0101000xxxxxxxxxxxxx
udiv. */
- return 1937;
+ return 1940;
}
else
{
@@ -3744,7 +3744,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx0x1101000xxxxxxxxxxxxx
uabd. */
- return 1928;
+ return 1931;
}
}
}
@@ -3760,7 +3760,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx000011000xxxxxxxxxxxxx
subr. */
- return 1917;
+ return 1920;
}
else
{
@@ -3768,7 +3768,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx010011000xxxxxxxxxxxxx
umulh. */
- return 1948;
+ return 1951;
}
}
else
@@ -3779,7 +3779,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx001011000xxxxxxxxxxxxx
umin. */
- return 1946;
+ return 1949;
}
else
{
@@ -3787,7 +3787,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx011011000xxxxxxxxxxxxx
bic. */
- return 1266;
+ return 1269;
}
}
}
@@ -3797,7 +3797,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx0xx111000xxxxxxxxxxxxx
udivr. */
- return 1938;
+ return 1941;
}
}
}
@@ -3810,7 +3810,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
100001x00x0xxxxx000xxxxxxxxxxxxx
ld1sb. */
- return 1528;
+ return 1531;
}
else
{
@@ -3818,7 +3818,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
100001x01x0xxxxx000xxxxxxxxxxxxx
ld1sh. */
- return 1539;
+ return 1542;
}
}
}
@@ -3830,7 +3830,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10001x00x0xxxxx000xxxxxxxxxxxxx
ld1sb. */
- return 1532;
+ return 1535;
}
else
{
@@ -3842,7 +3842,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x01x0xxxxx000xx0xxxxxxxxxx
sdot. */
- return 1787;
+ return 1790;
}
else
{
@@ -3850,7 +3850,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x01x0xxxxx000xx1xxxxxxxxxx
udot. */
- return 1939;
+ return 1942;
}
}
else
@@ -3859,7 +3859,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
110001x01x0xxxxx000xxxxxxxxxxxxx
ld1sh. */
- return 1543;
+ return 1546;
}
}
}
@@ -3880,7 +3880,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx1xxxxx000000xxxxxxxxxx
add. */
- return 1244;
+ return 1247;
}
else
{
@@ -3888,7 +3888,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx1xxxxx000100xxxxxxxxxx
sqadd. */
- return 1801;
+ return 1804;
}
}
else
@@ -3897,7 +3897,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx1xxxxx000x10xxxxxxxxxx
sqsub. */
- return 1831;
+ return 1834;
}
}
else
@@ -3910,7 +3910,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx1xxxxx000001xxxxxxxxxx
sub. */
- return 1913;
+ return 1916;
}
else
{
@@ -3918,7 +3918,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx1xxxxx000101xxxxxxxxxx
uqadd. */
- return 1949;
+ return 1952;
}
}
else
@@ -3927,7 +3927,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx1xxxxx000x11xxxxxxxxxx
uqsub. */
- return 1979;
+ return 1982;
}
}
}
@@ -3939,7 +3939,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
100001x00x1xxxxx000xxxxxxxxxxxxx
prfb. */
- return 1734;
+ return 1737;
}
else
{
@@ -3947,7 +3947,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
100001x01x1xxxxx000xxxxxxxxxxxxx
ld1sh. */
- return 1540;
+ return 1543;
}
}
}
@@ -3959,7 +3959,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10001x00x1xxxxx000xxxxxxxxxxxxx
prfb. */
- return 1735;
+ return 1738;
}
else
{
@@ -3973,7 +3973,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0101xxxxx000xx0xxxxxxxxxx
sdot. */
- return 1788;
+ return 1791;
}
else
{
@@ -3981,7 +3981,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0111xxxxx000xx0xxxxxxxxxx
sdot. */
- return 1789;
+ return 1792;
}
}
else
@@ -3992,7 +3992,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0101xxxxx000xx1xxxxxxxxxx
udot. */
- return 1940;
+ return 1943;
}
else
{
@@ -4000,7 +4000,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
010001x0111xxxxx000xx1xxxxxxxxxx
udot. */
- return 1941;
+ return 1944;
}
}
}
@@ -4010,7 +4010,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
110001x01x1xxxxx000xxxxxxxxxxxxx
ld1sh. */
- return 1544;
+ return 1547;
}
}
}
@@ -4036,7 +4036,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx0000x0100xxxxxxxxxxxxx
asr. */
- return 1262;
+ return 1265;
}
else
{
@@ -4044,7 +4044,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx0100x0100xxxxxxxxxxxxx
asr. */
- return 1260;
+ return 1263;
}
}
else
@@ -4053,7 +4053,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx0x10x0100xxxxxxxxxxxxx
asr. */
- return 1261;
+ return 1264;
}
}
else
@@ -4064,7 +4064,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx00x1x0100xxxxxxxxxxxxx
asrd. */
- return 1263;
+ return 1266;
}
else
{
@@ -4072,7 +4072,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx01x1x0100xxxxxxxxxxxxx
asrr. */
- return 1264;
+ return 1267;
}
}
}
@@ -4090,7 +4090,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx000001100xxxxxxxxxxxxx
lsr. */
- return 1706;
+ return 1709;
}
else
{
@@ -4098,7 +4098,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx010001100xxxxxxxxxxxxx
lsr. */
- return 1704;
+ return 1707;
}
}
else
@@ -4107,7 +4107,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx0x1001100xxxxxxxxxxxxx
lsr. */
- return 1705;
+ return 1708;
}
}
else
@@ -4116,7 +4116,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx0xx101100xxxxxxxxxxxxx
lsrr. */
- return 1707;
+ return 1710;
}
}
else
@@ -4131,7 +4131,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx000011100xxxxxxxxxxxxx
lsl. */
- return 1700;
+ return 1703;
}
else
{
@@ -4139,7 +4139,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx010011100xxxxxxxxxxxxx
lsl. */
- return 1698;
+ return 1701;
}
}
else
@@ -4148,7 +4148,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx0x1011100xxxxxxxxxxxxx
lsl. */
- return 1699;
+ return 1702;
}
}
else
@@ -4157,7 +4157,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx0xx111100xxxxxxxxxxxxx
lslr. */
- return 1701;
+ return 1704;
}
}
}
@@ -4172,7 +4172,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx1xxxxx1000x0xxxxxxxxxx
asr. */
- return 1258;
+ return 1261;
}
else
{
@@ -4180,7 +4180,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx1xxxxx1001x0xxxxxxxxxx
asr. */
- return 1259;
+ return 1262;
}
}
else
@@ -4193,7 +4193,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx1xxxxx100001xxxxxxxxxx
lsr. */
- return 1702;
+ return 1705;
}
else
{
@@ -4201,7 +4201,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx1xxxxx100101xxxxxxxxxx
lsr. */
- return 1703;
+ return 1706;
}
}
else
@@ -4212,7 +4212,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx1xxxxx100011xxxxxxxxxx
lsl. */
- return 1696;
+ return 1699;
}
else
{
@@ -4220,7 +4220,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx1xxxxx100111xxxxxxxxxx
lsl. */
- return 1697;
+ return 1700;
}
}
}
@@ -4236,7 +4236,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
100001x000xxxxxx100xxxxxxxxxxxxx
ld1sb. */
- return 1534;
+ return 1537;
}
else
{
@@ -4244,7 +4244,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
100001x010xxxxxx100xxxxxxxxxxxxx
ld1sh. */
- return 1547;
+ return 1550;
}
}
else
@@ -4255,7 +4255,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
100001x001xxxxxx100xxxxxxxxxxxxx
ld1rb. */
- return 1504;
+ return 1507;
}
else
{
@@ -4263,7 +4263,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
100001x011xxxxxx100xxxxxxxxxxxxx
ld1rsw. */
- return 1525;
+ return 1528;
}
}
}
@@ -4278,7 +4278,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10001x00x0xxxxx100xxxxxxxxxxxxx
ld1sb. */
- return 1533;
+ return 1536;
}
else
{
@@ -4286,7 +4286,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10001x01x0xxxxx100xxxxxxxxxxxxx
ld1sh. */
- return 1545;
+ return 1548;
}
}
else
@@ -4299,7 +4299,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10001x0001xxxxx100xxxxxxxxxxxxx
ld1sb. */
- return 1538;
+ return 1541;
}
else
{
@@ -4307,7 +4307,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10001x0101xxxxx100xxxxxxxxxxxxx
ld1sh. */
- return 1550;
+ return 1553;
}
}
else
@@ -4318,7 +4318,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10001x0011xxxxx100xxxxxxxxxxxxx
prfb. */
- return 1736;
+ return 1739;
}
else
{
@@ -4326,7 +4326,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10001x0111xxxxx100xxxxxxxxxxxxx
ld1sh. */
- return 1546;
+ return 1549;
}
}
}
@@ -4347,7 +4347,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx0xxxxx010xxxxxxxxxxxxx
mla. */
- return 1709;
+ return 1712;
}
else
{
@@ -4357,7 +4357,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
100001x00x0xxxxx010xxxxxxxxxxxxx
ld1b. */
- return 1470;
+ return 1473;
}
else
{
@@ -4365,7 +4365,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
100001x01x0xxxxx010xxxxxxxxxxxxx
ld1h. */
- return 1490;
+ return 1493;
}
}
}
@@ -4377,7 +4377,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10001x00x0xxxxx010xxxxxxxxxxxxx
ld1b. */
- return 1475;
+ return 1478;
}
else
{
@@ -4385,7 +4385,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10001x01x0xxxxx010xxxxxxxxxxxxx
ld1h. */
- return 1495;
+ return 1498;
}
}
}
@@ -4405,7 +4405,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx1xxxxx010000xxxxxxxxxx
index. */
- return 1461;
+ return 1464;
}
else
{
@@ -4413,7 +4413,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx1xxxxx010001xxxxxxxxxx
index. */
- return 1462;
+ return 1465;
}
}
else
@@ -4426,7 +4426,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0001xxxxx01010xxxxxxxxxxx
addvl. */
- return 1248;
+ return 1251;
}
else
{
@@ -4434,7 +4434,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0101xxxxx01010xxxxxxxxxxx
rdvl. */
- return 1770;
+ return 1773;
}
}
else
@@ -4443,7 +4443,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0x11xxxxx01010xxxxxxxxxxx
addpl. */
- return 1247;
+ return 1250;
}
}
}
@@ -4455,7 +4455,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx1xxxxx010x10xxxxxxxxxx
index. */
- return 1463;
+ return 1466;
}
else
{
@@ -4463,7 +4463,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx1xxxxx010x11xxxxxxxxxx
index. */
- return 1460;
+ return 1463;
}
}
}
@@ -4475,7 +4475,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
100001x00x1xxxxx010xxxxxxxxxxxxx
prfw. */
- return 1754;
+ return 1757;
}
else
{
@@ -4483,7 +4483,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
100001x01x1xxxxx010xxxxxxxxxxxxx
ld1h. */
- return 1491;
+ return 1494;
}
}
}
@@ -4495,7 +4495,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10001x00x1xxxxx010xxxxxxxxxxxxx
prfw. */
- return 1756;
+ return 1759;
}
else
{
@@ -4503,7 +4503,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
x10001x01x1xxxxx010xxxxxxxxxxxxx
ld1h. */
- return 1496;
+ return 1499;
}
}
}
@@ -4520,7 +4520,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0xx0xxxxx110xxxxxxxxxxxxx
mad. */
- return 1708;
+ return 1711;
}
else
{
@@ -4536,7 +4536,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0x010xxxx110x00xxxxxxxxxx
sqincw. */
- return 1828;
+ return 1831;
}
else
{
@@ -4546,7 +4546,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x00110xxxx110x00xxxxxxxxxx
sqinch. */
- return 1822;
+ return 1825;
}
else
{
@@ -4554,7 +4554,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x01110xxxx110x00xxxxxxxxxx
sqincd. */
- return 1819;
+ return 1822;
}
}
}
@@ -4566,7 +4566,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0x011xxxx110x00xxxxxxxxxx
incw. */
- return 1458;
+ return 1461;
}
else
{
@@ -4576,7 +4576,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x00111xxxx110x00xxxxxxxxxx
inch. */
- return 1454;
+ return 1457;
}
else
{
@@ -4584,7 +4584,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x01111xxxx110x00xxxxxxxxxx
incd. */
- return 1452;
+ return 1455;
}
}
}
@@ -4597,7 +4597,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0x01xxxxx110x10xxxxxxxxxx
sqdecw. */
- return 1814;
+ return 1817;
}
else
{
@@ -4607,7 +4607,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0011xxxxx110x10xxxxxxxxxx
sqdech. */
- return 1808;
+ return 1811;
}
else
{
@@ -4615,7 +4615,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0111xxxxx110x10xxxxxxxxxx
sqdecd. */
- return 1805;
+ return 1808;
}
}
}
@@ -4632,7 +4632,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0x010xxxx110x01xxxxxxxxxx
uqincw. */
- return 1976;
+ return 1979;
}
else
{
@@ -4642,7 +4642,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x00110xxxx110x01xxxxxxxxxx
uqinch. */
- return 1970;
+ return 1973;
}
else
{
@@ -4650,7 +4650,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x01110xxxx110x01xxxxxxxxxx
uqincd. */
- return 1967;
+ return 1970;
}
}
}
@@ -4662,7 +4662,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0x011xxxx110x01xxxxxxxxxx
decw. */
- return 1333;
+ return 1336;
}
else
{
@@ -4672,7 +4672,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x00111xxxx110x01xxxxxxxxxx
dech. */
- return 1329;
+ return 1332;
}
else
{
@@ -4680,7 +4680,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x01111xxxx110x01xxxxxxxxxx
decd. */
- return 1327;
+ return 1330;
}
}
}
@@ -4693,7 +4693,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0x01xxxxx110x11xxxxxxxxxx
uqdecw. */
- return 1962;
+ return 1965;
}
else
{
@@ -4703,7 +4703,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0011xxxxx110x11xxxxxxxxxx
uqdech. */
- return 1956;
+ return 1959;
}
else
{
@@ -4711,7 +4711,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
10987654321098765432109876543210
000001x0111xxxxx110x11xxxxxxxxxx
uqdecd. */
- return 1953;
+ return 1956;
}
}
}
@@ -4730,7 +4730,7 @@ aarch64_opcode_lookup_1 (uint32_t wo[...]
[diff truncated at 100000 bytes]