[binutils-gdb] Enable Intel GFNI instructions.
Igor Tsimbalist
itsimbal@sourceware.org
Mon Oct 23 13:18:00 GMT 2017
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=48521003d5300e1390d78dbbcae83febe5808aaf
commit 48521003d5300e1390d78dbbcae83febe5808aaf
Author: Igor Tsimbalist <igor.v.tsimbalist@intel.com>
Date: Fri Oct 20 23:26:11 2017 +0300
Enable Intel GFNI instructions.
Intel has disclosed a set of new instructions. The spec is
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
gas/
* config/tc-i386.c (cpu_arch): Add .gfni.
* doc/c-i386.texi: Document .gfni.
* testsuite/gas/i386/i386.exp: Add GFNI tests.
* testsuite/gas/i386/avx.s: New GFNI test.
* testsuite/gas/i386/x86-64-avx.s: Likewise.
* testsuite/gas/i386/avx.d: Adjust.
* testsuite/gas/i386/avx-intel.d: Likewise
* testsuite/gas/i386/ilp32/x86-64-avx-intel.d: Likewise.
* testsuite/gas/i386/ilp32/x86-64-avx.d: Likewise.
* testsuite/gas/i386/avx512f_gfni-intel.d: New test.
* testsuite/gas/i386/avx512f_gfni.d: Likewise.
* testsuite/gas/i386/avx512f_gfni.s: Likewise.
* testsuite/gas/i386/avx512vl_gfni-intel.d: Likewise.
* testsuite/gas/i386/avx512vl_gfni.d: Likewise.
* testsuite/gas/i386/avx512vl_gfni.s: Likewise.
* testsuite/gas/i386/gfni-intel.d: Likewise.
* testsuite/gas/i386/gfni.d: Likewise.
* testsuite/gas/i386/gfni.s: Likewise.
* testsuite/gas/i386/x86-64-avx512f_gfni-intel.d: Likewise.
* testsuite/gas/i386/x86-64-avx512f_gfni.d: Likewise.
* testsuite/gas/i386/x86-64-avx512f_gfni.s: Likewise.
* testsuite/gas/i386/x86-64-avx512vl_gfni-intel.d: Likewise.
* testsuite/gas/i386/x86-64-avx512vl_gfni.d: Likewise.
* testsuite/gas/i386/x86-64-avx512vl_gfni.s: Likewise.
* testsuite/gas/i386/x86-64-avx_gfni-intel.d: Likewise.
* testsuite/gas/i386/x86-64-avx_gfni.d: Likewise.
* testsuite/gas/i386/x86-64-avx_gfni.s: Likewise.
* testsuite/gas/i386/x86-64-gfni-intel.d: Likewise.
* testsuite/gas/i386/x86-64-gfni.d: Likewise.
* testsuite/gas/i386/x86-64-gfni.s: Likewise.
opcodes/
* i386-dis.c (enum): Add PREFIX_0F38CF, PREFIX_0F3ACE, PREFIX_0F3ACF,
PREFIX_VEX_0F38CF, PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF,
PREFIX_EVEX_0F38CF, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF.
(enum): Add VEX_W_0F38CF_P_2, VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2,
EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2.
(prefix_table): Updated (see prefixes above).
(three_byte_table): Likewise.
(vex_w_table): Likewise.
* i386-dis-evex.h: Likewise.
* i386-gen.c (cpu_flag_init): Add CPU_GFNI_FLAGS, CpuGFNI.
(cpu_flags): Add CpuGFNI.
* i386-opc.h (enum): Add CpuGFNI.
(i386_cpu_flags): Add cpugfni.
* i386-opc.tbl: Add Intel GFNI instructions.
* i386-init.h: Regenerate.
* i386-tbl.h: Likewise.
Diff:
---
gas/config/tc-i386.c | 2 +
gas/doc/c-i386.texi | 3 +-
gas/testsuite/gas/i386/avx-intel.d | 98 +
gas/testsuite/gas/i386/avx.d | 98 +
gas/testsuite/gas/i386/avx.s | 98 +
gas/testsuite/gas/i386/avx512f_gfni-intel.d | 46 +
gas/testsuite/gas/i386/avx512f_gfni.d | 46 +
gas/testsuite/gas/i386/avx512f_gfni.s | 45 +
gas/testsuite/gas/i386/avx512vl_gfni-intel.d | 73 +
gas/testsuite/gas/i386/avx512vl_gfni.d | 73 +
gas/testsuite/gas/i386/avx512vl_gfni.s | 72 +
gas/testsuite/gas/i386/gfni-intel.d | 30 +
gas/testsuite/gas/i386/gfni.d | 30 +
gas/testsuite/gas/i386/gfni.s | 30 +
gas/testsuite/gas/i386/i386.exp | 14 +
gas/testsuite/gas/i386/ilp32/x86-64-avx-intel.d | 98 +
gas/testsuite/gas/i386/ilp32/x86-64-avx.d | 98 +
gas/testsuite/gas/i386/x86-64-avx-intel.d | 98 +
gas/testsuite/gas/i386/x86-64-avx.d | 98 +
gas/testsuite/gas/i386/x86-64-avx.s | 100 +
gas/testsuite/gas/i386/x86-64-avx512f_gfni-intel.d | 46 +
gas/testsuite/gas/i386/x86-64-avx512f_gfni.d | 46 +
gas/testsuite/gas/i386/x86-64-avx512f_gfni.s | 45 +
.../gas/i386/x86-64-avx512vl_gfni-intel.d | 80 +
gas/testsuite/gas/i386/x86-64-avx512vl_gfni.d | 80 +
gas/testsuite/gas/i386/x86-64-avx512vl_gfni.s | 79 +
gas/testsuite/gas/i386/x86-64-avx_gfni-intel.d | 48 +
gas/testsuite/gas/i386/x86-64-avx_gfni.d | 48 +
gas/testsuite/gas/i386/x86-64-avx_gfni.s | 54 +
gas/testsuite/gas/i386/x86-64-gfni-intel.d | 30 +
gas/testsuite/gas/i386/x86-64-gfni.d | 30 +
gas/testsuite/gas/i386/x86-64-gfni.s | 30 +
opcodes/i386-dis-evex.h | 34 +-
opcodes/i386-dis.c | 86 +-
opcodes/i386-gen.c | 3 +
opcodes/i386-init.h | 281 +-
opcodes/i386-opc.h | 5 +-
opcodes/i386-opc.tbl | 36 +
opcodes/i386-tbl.h | 11009 ++++++++++---------
39 files changed, 7876 insertions(+), 5444 deletions(-)
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index fdfaa51..aff7f9b 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -996,6 +996,8 @@ static const arch_entry cpu_arch[] =
CPU_PTWRITE_FLAGS, 0 },
{ STRING_COMMA_LEN (".cet"), PROCESSOR_UNKNOWN,
CPU_CET_FLAGS, 0 },
+ { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN,
+ CPU_GFNI_FLAGS, 0 },
};
static const noarch_entry cpu_noarch[] =
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index 94d1f9c..5740d33 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -168,6 +168,7 @@ accept various extension mnemonics. For example,
@code{rdpid},
@code{ptwrite},
@code{cet},
+@code{gfni},
@code{prefetchwt1},
@code{clflushopt},
@code{se1},
@@ -1225,7 +1226,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
@item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
@item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
@item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
-@item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx}
+@item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx} @tab @samp{.gfni}
@end multitable
Apart from the warning, there are only two other effects on
diff --git a/gas/testsuite/gas/i386/avx-intel.d b/gas/testsuite/gas/i386/avx-intel.d
index 2295df9..bc5485e 100644
--- a/gas/testsuite/gas/i386/avx-intel.d
+++ b/gas/testsuite/gas/i386/avx-intel.d
@@ -215,6 +215,13 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c5 cc c2 11 1e vcmpgt_oqps ymm2,ymm6,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 cc c2 d4 1f vcmptrue_usps ymm2,ymm6,ymm4
[ ]*[a-f0-9]+: c5 cc c2 11 1f vcmptrue_usps ymm2,ymm6,YMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c4 e2 55 cf f4 vgf2p8mulb ymm6,ymm5,ymm4
+[ ]*[a-f0-9]+: c4 e2 55 cf 31 vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c4 e2 55 cf b4 f4 c0 1d fe ff vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ ]*[a-f0-9]+: c4 e2 55 cf b2 e0 0f 00 00 vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\]
+[ ]*[a-f0-9]+: c4 e2 55 cf b2 00 10 00 00 vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[edx\+0x1000\]
+[ ]*[a-f0-9]+: c4 e2 55 cf b2 00 f0 ff ff vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[edx-0x1000\]
+[ ]*[a-f0-9]+: c4 e2 55 cf b2 e0 ef ff ff vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[edx-0x1020\]
[ ]*[a-f0-9]+: c5 ff e6 e4 vcvtpd2dq xmm4,ymm4
[ ]*[a-f0-9]+: c5 ff e6 21 vcvtpd2dq xmm4,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 fd 5a e4 vcvtpd2ps xmm4,ymm4
@@ -291,6 +298,22 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c5 cd c6 11 07 vshufpd ymm2,ymm6,YMMWORD PTR \[ecx\],0x7
[ ]*[a-f0-9]+: c5 cc c6 d4 07 vshufps ymm2,ymm6,ymm4,0x7
[ ]*[a-f0-9]+: c5 cc c6 11 07 vshufps ymm2,ymm6,YMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 d5 ce f4 ab vgf2p8affineqb ymm6,ymm5,ymm4,0xab
+[ ]*[a-f0-9]+: c4 e3 d5 ce f4 7b vgf2p8affineqb ymm6,ymm5,ymm4,0x7b
+[ ]*[a-f0-9]+: c4 e3 d5 ce 31 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[ecx\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d5 ce b4 f4 c0 1d fe ff 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d5 ce b2 e0 0f 00 00 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d5 ce b2 00 10 00 00 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[edx\+0x1000\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d5 ce b2 00 f0 ff ff 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[edx-0x1000\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d5 ce b2 e0 ef ff ff 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[edx-0x1020\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d5 cf f4 ab vgf2p8affineinvqb ymm6,ymm5,ymm4,0xab
+[ ]*[a-f0-9]+: c4 e3 d5 cf f4 7b vgf2p8affineinvqb ymm6,ymm5,ymm4,0x7b
+[ ]*[a-f0-9]+: c4 e3 d5 cf 31 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[ecx\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d5 cf b4 f4 c0 1d fe ff 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d5 cf b2 e0 0f 00 00 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d5 cf b2 00 10 00 00 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[edx\+0x1000\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d5 cf b2 00 f0 ff ff 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[edx-0x1000\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d5 cf b2 e0 ef ff ff 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[edx-0x1020\],0x7b
[ ]*[a-f0-9]+: c4 e3 6d 4b fe 40 vblendvpd ymm7,ymm2,ymm6,ymm4
[ ]*[a-f0-9]+: c4 e3 6d 4b 39 40 vblendvpd ymm7,ymm2,YMMWORD PTR \[ecx\],ymm4
[ ]*[a-f0-9]+: c4 e3 6d 4a fe 40 vblendvps ymm7,ymm2,ymm6,ymm4
@@ -745,6 +768,13 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c5 c8 c2 39 1e vcmpgt_oqps xmm7,xmm6,XMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 c8 c2 d4 1f vcmptrue_usps xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c5 c8 c2 39 1f vcmptrue_usps xmm7,xmm6,XMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c4 e2 51 cf f4 vgf2p8mulb xmm6,xmm5,xmm4
+[ ]*[a-f0-9]+: c4 e2 51 cf 31 vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c4 e2 51 cf b4 f4 c0 1d fe ff vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ ]*[a-f0-9]+: c4 e2 51 cf b2 f0 07 00 00 vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[edx\+0x7f0\]
+[ ]*[a-f0-9]+: c4 e2 51 cf b2 00 08 00 00 vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[edx\+0x800\]
+[ ]*[a-f0-9]+: c4 e2 51 cf b2 00 f8 ff ff vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[edx-0x800\]
+[ ]*[a-f0-9]+: c4 e2 51 cf b2 f0 f7 ff ff vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[edx-0x810\]
[ ]*[a-f0-9]+: c4 e2 59 2c 31 vmaskmovps xmm6,xmm4,XMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c4 e2 59 2d 31 vmaskmovpd xmm6,xmm4,XMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c4 e3 79 df f4 07 vaeskeygenassist xmm6,xmm4,0x7
@@ -797,6 +827,22 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c5 c9 c6 11 07 vshufpd xmm2,xmm6,XMMWORD PTR \[ecx\],0x7
[ ]*[a-f0-9]+: c5 c8 c6 d4 07 vshufps xmm2,xmm6,xmm4,0x7
[ ]*[a-f0-9]+: c5 c8 c6 11 07 vshufps xmm2,xmm6,XMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 d1 ce f4 ab vgf2p8affineqb xmm6,xmm5,xmm4,0xab
+[ ]*[a-f0-9]+: c4 e3 d1 ce f4 7b vgf2p8affineqb xmm6,xmm5,xmm4,0x7b
+[ ]*[a-f0-9]+: c4 e3 d1 ce 31 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[ecx\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d1 ce b4 f4 c0 1d fe ff 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d1 ce b2 f0 07 00 00 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[edx\+0x7f0\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d1 ce b2 00 08 00 00 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[edx\+0x800\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d1 ce b2 00 f8 ff ff 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[edx-0x800\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d1 ce b2 f0 f7 ff ff 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[edx-0x810\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d1 cf f4 ab vgf2p8affineinvqb xmm6,xmm5,xmm4,0xab
+[ ]*[a-f0-9]+: c4 e3 d1 cf f4 7b vgf2p8affineinvqb xmm6,xmm5,xmm4,0x7b
+[ ]*[a-f0-9]+: c4 e3 d1 cf 31 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[ecx\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d1 cf b4 f4 c0 1d fe ff 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d1 cf b2 f0 07 00 00 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[edx\+0x7f0\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d1 cf b2 00 08 00 00 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[edx\+0x800\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d1 cf b2 00 f8 ff ff 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[edx-0x800\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d1 cf b2 f0 f7 ff ff 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[edx-0x810\],0x7b
[ ]*[a-f0-9]+: c4 e3 69 4b fe 40 vblendvpd xmm7,xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c4 e3 69 4b 39 40 vblendvpd xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
[ ]*[a-f0-9]+: c4 e3 69 4a fe 40 vblendvps xmm7,xmm2,xmm6,xmm4
@@ -1641,6 +1687,14 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c5 cc c2 d4 1f vcmptrue_usps ymm2,ymm6,ymm4
[ ]*[a-f0-9]+: c5 cc c2 11 1f vcmptrue_usps ymm2,ymm6,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 cc c2 11 1f vcmptrue_usps ymm2,ymm6,YMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c4 e2 55 cf f4 vgf2p8mulb ymm6,ymm5,ymm4
+[ ]*[a-f0-9]+: c4 e2 55 cf 31 vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c4 e2 55 cf 31 vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c4 e2 55 cf b4 f4 c0 1d fe ff vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ ]*[a-f0-9]+: c4 e2 55 cf b2 e0 0f 00 00 vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\]
+[ ]*[a-f0-9]+: c4 e2 55 cf b2 00 10 00 00 vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[edx\+0x1000\]
+[ ]*[a-f0-9]+: c4 e2 55 cf b2 00 f0 ff ff vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[edx-0x1000\]
+[ ]*[a-f0-9]+: c4 e2 55 cf b2 e0 ef ff ff vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[edx-0x1020\]
[ ]*[a-f0-9]+: c5 ff e6 e4 vcvtpd2dq xmm4,ymm4
[ ]*[a-f0-9]+: c5 ff e6 21 vcvtpd2dq xmm4,YMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 fd 5a e4 vcvtpd2ps xmm4,ymm4
@@ -1754,6 +1808,24 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c5 cc c6 d4 07 vshufps ymm2,ymm6,ymm4,0x7
[ ]*[a-f0-9]+: c5 cc c6 11 07 vshufps ymm2,ymm6,YMMWORD PTR \[ecx\],0x7
[ ]*[a-f0-9]+: c5 cc c6 11 07 vshufps ymm2,ymm6,YMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 d5 ce f4 ab vgf2p8affineqb ymm6,ymm5,ymm4,0xab
+[ ]*[a-f0-9]+: c4 e3 d5 ce f4 7b vgf2p8affineqb ymm6,ymm5,ymm4,0x7b
+[ ]*[a-f0-9]+: c4 e3 d5 ce 31 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[ecx\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d5 ce 31 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[ecx\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d5 ce b4 f4 c0 1d fe ff 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d5 ce b2 e0 0f 00 00 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d5 ce b2 00 10 00 00 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[edx\+0x1000\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d5 ce b2 00 f0 ff ff 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[edx-0x1000\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d5 ce b2 e0 ef ff ff 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[edx-0x1020\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d5 cf f4 ab vgf2p8affineinvqb ymm6,ymm5,ymm4,0xab
+[ ]*[a-f0-9]+: c4 e3 d5 cf f4 7b vgf2p8affineinvqb ymm6,ymm5,ymm4,0x7b
+[ ]*[a-f0-9]+: c4 e3 d5 cf 31 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[ecx\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d5 cf 31 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[ecx\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d5 cf b4 f4 c0 1d fe ff 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d5 cf b2 e0 0f 00 00 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[edx\+0xfe0\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d5 cf b2 00 10 00 00 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[edx\+0x1000\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d5 cf b2 00 f0 ff ff 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[edx-0x1000\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d5 cf b2 e0 ef ff ff 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[edx-0x1020\],0x7b
[ ]*[a-f0-9]+: c4 e3 6d 4b fe 40 vblendvpd ymm7,ymm2,ymm6,ymm4
[ ]*[a-f0-9]+: c4 e3 6d 4b 39 40 vblendvpd ymm7,ymm2,YMMWORD PTR \[ecx\],ymm4
[ ]*[a-f0-9]+: c4 e3 6d 4b 39 40 vblendvpd ymm7,ymm2,YMMWORD PTR \[ecx\],ymm4
@@ -2435,6 +2507,14 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c5 c8 c2 d4 1f vcmptrue_usps xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c5 c8 c2 39 1f vcmptrue_usps xmm7,xmm6,XMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c5 c8 c2 39 1f vcmptrue_usps xmm7,xmm6,XMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c4 e2 51 cf f4 vgf2p8mulb xmm6,xmm5,xmm4
+[ ]*[a-f0-9]+: c4 e2 51 cf 31 vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c4 e2 51 cf 31 vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[ecx\]
+[ ]*[a-f0-9]+: c4 e2 51 cf b4 f4 c0 1d fe ff vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ ]*[a-f0-9]+: c4 e2 51 cf b2 f0 07 00 00 vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[edx\+0x7f0\]
+[ ]*[a-f0-9]+: c4 e2 51 cf b2 00 08 00 00 vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[edx\+0x800\]
+[ ]*[a-f0-9]+: c4 e2 51 cf b2 00 f8 ff ff vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[edx-0x800\]
+[ ]*[a-f0-9]+: c4 e2 51 cf b2 f0 f7 ff ff vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[edx-0x810\]
[ ]*[a-f0-9]+: c4 e2 59 2c 31 vmaskmovps xmm6,xmm4,XMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c4 e2 59 2c 31 vmaskmovps xmm6,xmm4,XMMWORD PTR \[ecx\]
[ ]*[a-f0-9]+: c4 e2 59 2d 31 vmaskmovpd xmm6,xmm4,XMMWORD PTR \[ecx\]
@@ -2515,6 +2595,24 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c5 c8 c6 d4 07 vshufps xmm2,xmm6,xmm4,0x7
[ ]*[a-f0-9]+: c5 c8 c6 11 07 vshufps xmm2,xmm6,XMMWORD PTR \[ecx\],0x7
[ ]*[a-f0-9]+: c5 c8 c6 11 07 vshufps xmm2,xmm6,XMMWORD PTR \[ecx\],0x7
+[ ]*[a-f0-9]+: c4 e3 d1 ce f4 ab vgf2p8affineqb xmm6,xmm5,xmm4,0xab
+[ ]*[a-f0-9]+: c4 e3 d1 ce f4 7b vgf2p8affineqb xmm6,xmm5,xmm4,0x7b
+[ ]*[a-f0-9]+: c4 e3 d1 ce 31 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[ecx\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d1 ce 31 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[ecx\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d1 ce b4 f4 c0 1d fe ff 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d1 ce b2 f0 07 00 00 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[edx\+0x7f0\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d1 ce b2 00 08 00 00 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[edx\+0x800\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d1 ce b2 00 f8 ff ff 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[edx-0x800\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d1 ce b2 f0 f7 ff ff 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[edx-0x810\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d1 cf f4 ab vgf2p8affineinvqb xmm6,xmm5,xmm4,0xab
+[ ]*[a-f0-9]+: c4 e3 d1 cf f4 7b vgf2p8affineinvqb xmm6,xmm5,xmm4,0x7b
+[ ]*[a-f0-9]+: c4 e3 d1 cf 31 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[ecx\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d1 cf 31 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[ecx\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d1 cf b4 f4 c0 1d fe ff 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d1 cf b2 f0 07 00 00 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[edx\+0x7f0\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d1 cf b2 00 08 00 00 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[edx\+0x800\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d1 cf b2 00 f8 ff ff 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[edx-0x800\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d1 cf b2 f0 f7 ff ff 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[edx-0x810\],0x7b
[ ]*[a-f0-9]+: c4 e3 69 4b fe 40 vblendvpd xmm7,xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c4 e3 69 4b 39 40 vblendvpd xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
[ ]*[a-f0-9]+: c4 e3 69 4b 39 40 vblendvpd xmm7,xmm2,XMMWORD PTR \[ecx\],xmm4
diff --git a/gas/testsuite/gas/i386/avx.d b/gas/testsuite/gas/i386/avx.d
index 5f24dce..6435608 100644
--- a/gas/testsuite/gas/i386/avx.d
+++ b/gas/testsuite/gas/i386/avx.d
@@ -214,6 +214,13 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c5 cc c2 11 1e vcmpgt_oqps \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c2 d4 1f vcmptrue_usps %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c2 11 1f vcmptrue_usps \(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c4 e2 55 cf f4 vgf2p8mulb %ymm4,%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e2 55 cf 31 vgf2p8mulb \(%ecx\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e2 55 cf b4 f4 c0 1d fe ff vgf2p8mulb -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e2 55 cf b2 e0 0f 00 00 vgf2p8mulb 0xfe0\(%edx\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e2 55 cf b2 00 10 00 00 vgf2p8mulb 0x1000\(%edx\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e2 55 cf b2 00 f0 ff ff vgf2p8mulb -0x1000\(%edx\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e2 55 cf b2 e0 ef ff ff vgf2p8mulb -0x1020\(%edx\),%ymm5,%ymm6
[ ]*[a-f0-9]+: c5 ff e6 e4 vcvtpd2dq %ymm4,%xmm4
[ ]*[a-f0-9]+: c5 ff e6 21 vcvtpd2dqy \(%ecx\),%xmm4
[ ]*[a-f0-9]+: c5 fd 5a e4 vcvtpd2ps %ymm4,%xmm4
@@ -290,6 +297,22 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c5 cd c6 11 07 vshufpd \$0x7,\(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c6 d4 07 vshufps \$0x7,%ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c6 11 07 vshufps \$0x7,\(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c4 e3 d5 ce f4 ab vgf2p8affineqb \$0xab,%ymm4,%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e3 d5 ce f4 7b vgf2p8affineqb \$0x7b,%ymm4,%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e3 d5 ce 31 7b vgf2p8affineqb \$0x7b,\(%ecx\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e3 d5 ce b4 f4 c0 1d fe ff 7b vgf2p8affineqb \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e3 d5 ce b2 e0 0f 00 00 7b vgf2p8affineqb \$0x7b,0xfe0\(%edx\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e3 d5 ce b2 00 10 00 00 7b vgf2p8affineqb \$0x7b,0x1000\(%edx\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e3 d5 ce b2 00 f0 ff ff 7b vgf2p8affineqb \$0x7b,-0x1000\(%edx\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e3 d5 ce b2 e0 ef ff ff 7b vgf2p8affineqb \$0x7b,-0x1020\(%edx\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e3 d5 cf f4 ab vgf2p8affineinvqb \$0xab,%ymm4,%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e3 d5 cf f4 7b vgf2p8affineinvqb \$0x7b,%ymm4,%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e3 d5 cf 31 7b vgf2p8affineinvqb \$0x7b,\(%ecx\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e3 d5 cf b4 f4 c0 1d fe ff 7b vgf2p8affineinvqb \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e3 d5 cf b2 e0 0f 00 00 7b vgf2p8affineinvqb \$0x7b,0xfe0\(%edx\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e3 d5 cf b2 00 10 00 00 7b vgf2p8affineinvqb \$0x7b,0x1000\(%edx\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e3 d5 cf b2 00 f0 ff ff 7b vgf2p8affineinvqb \$0x7b,-0x1000\(%edx\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e3 d5 cf b2 e0 ef ff ff 7b vgf2p8affineinvqb \$0x7b,-0x1020\(%edx\),%ymm5,%ymm6
[ ]*[a-f0-9]+: c4 e3 6d 4b fe 40 vblendvpd %ymm4,%ymm6,%ymm2,%ymm7
[ ]*[a-f0-9]+: c4 e3 6d 4b 39 40 vblendvpd %ymm4,\(%ecx\),%ymm2,%ymm7
[ ]*[a-f0-9]+: c4 e3 6d 4a fe 40 vblendvps %ymm4,%ymm6,%ymm2,%ymm7
@@ -744,6 +767,13 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c5 c8 c2 39 1e vcmpgt_oqps \(%ecx\),%xmm6,%xmm7
[ ]*[a-f0-9]+: c5 c8 c2 d4 1f vcmptrue_usps %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 c8 c2 39 1f vcmptrue_usps \(%ecx\),%xmm6,%xmm7
+[ ]*[a-f0-9]+: c4 e2 51 cf f4 vgf2p8mulb %xmm4,%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e2 51 cf 31 vgf2p8mulb \(%ecx\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e2 51 cf b4 f4 c0 1d fe ff vgf2p8mulb -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e2 51 cf b2 f0 07 00 00 vgf2p8mulb 0x7f0\(%edx\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e2 51 cf b2 00 08 00 00 vgf2p8mulb 0x800\(%edx\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e2 51 cf b2 00 f8 ff ff vgf2p8mulb -0x800\(%edx\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e2 51 cf b2 f0 f7 ff ff vgf2p8mulb -0x810\(%edx\),%xmm5,%xmm6
[ ]*[a-f0-9]+: c4 e2 59 2c 31 vmaskmovps \(%ecx\),%xmm4,%xmm6
[ ]*[a-f0-9]+: c4 e2 59 2d 31 vmaskmovpd \(%ecx\),%xmm4,%xmm6
[ ]*[a-f0-9]+: c4 e3 79 df f4 07 vaeskeygenassist \$0x7,%xmm4,%xmm6
@@ -796,6 +826,22 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c5 c9 c6 11 07 vshufpd \$0x7,\(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 c8 c6 d4 07 vshufps \$0x7,%xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 c8 c6 11 07 vshufps \$0x7,\(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 d1 ce f4 ab vgf2p8affineqb \$0xab,%xmm4,%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e3 d1 ce f4 7b vgf2p8affineqb \$0x7b,%xmm4,%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e3 d1 ce 31 7b vgf2p8affineqb \$0x7b,\(%ecx\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e3 d1 ce b4 f4 c0 1d fe ff 7b vgf2p8affineqb \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e3 d1 ce b2 f0 07 00 00 7b vgf2p8affineqb \$0x7b,0x7f0\(%edx\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e3 d1 ce b2 00 08 00 00 7b vgf2p8affineqb \$0x7b,0x800\(%edx\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e3 d1 ce b2 00 f8 ff ff 7b vgf2p8affineqb \$0x7b,-0x800\(%edx\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e3 d1 ce b2 f0 f7 ff ff 7b vgf2p8affineqb \$0x7b,-0x810\(%edx\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e3 d1 cf f4 ab vgf2p8affineinvqb \$0xab,%xmm4,%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e3 d1 cf f4 7b vgf2p8affineinvqb \$0x7b,%xmm4,%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e3 d1 cf 31 7b vgf2p8affineinvqb \$0x7b,\(%ecx\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e3 d1 cf b4 f4 c0 1d fe ff 7b vgf2p8affineinvqb \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e3 d1 cf b2 f0 07 00 00 7b vgf2p8affineinvqb \$0x7b,0x7f0\(%edx\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e3 d1 cf b2 00 08 00 00 7b vgf2p8affineinvqb \$0x7b,0x800\(%edx\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e3 d1 cf b2 00 f8 ff ff 7b vgf2p8affineinvqb \$0x7b,-0x800\(%edx\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e3 d1 cf b2 f0 f7 ff ff 7b vgf2p8affineinvqb \$0x7b,-0x810\(%edx\),%xmm5,%xmm6
[ ]*[a-f0-9]+: c4 e3 69 4b fe 40 vblendvpd %xmm4,%xmm6,%xmm2,%xmm7
[ ]*[a-f0-9]+: c4 e3 69 4b 39 40 vblendvpd %xmm4,\(%ecx\),%xmm2,%xmm7
[ ]*[a-f0-9]+: c4 e3 69 4a fe 40 vblendvps %xmm4,%xmm6,%xmm2,%xmm7
@@ -1640,6 +1686,14 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c5 cc c2 d4 1f vcmptrue_usps %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c2 11 1f vcmptrue_usps \(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c2 11 1f vcmptrue_usps \(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c4 e2 55 cf f4 vgf2p8mulb %ymm4,%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e2 55 cf 31 vgf2p8mulb \(%ecx\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e2 55 cf 31 vgf2p8mulb \(%ecx\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e2 55 cf b4 f4 c0 1d fe ff vgf2p8mulb -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e2 55 cf b2 e0 0f 00 00 vgf2p8mulb 0xfe0\(%edx\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e2 55 cf b2 00 10 00 00 vgf2p8mulb 0x1000\(%edx\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e2 55 cf b2 00 f0 ff ff vgf2p8mulb -0x1000\(%edx\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e2 55 cf b2 e0 ef ff ff vgf2p8mulb -0x1020\(%edx\),%ymm5,%ymm6
[ ]*[a-f0-9]+: c5 ff e6 e4 vcvtpd2dq %ymm4,%xmm4
[ ]*[a-f0-9]+: c5 ff e6 21 vcvtpd2dqy \(%ecx\),%xmm4
[ ]*[a-f0-9]+: c5 fd 5a e4 vcvtpd2ps %ymm4,%xmm4
@@ -1753,6 +1807,24 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c5 cc c6 d4 07 vshufps \$0x7,%ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c6 11 07 vshufps \$0x7,\(%ecx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c6 11 07 vshufps \$0x7,\(%ecx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c4 e3 d5 ce f4 ab vgf2p8affineqb \$0xab,%ymm4,%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e3 d5 ce f4 7b vgf2p8affineqb \$0x7b,%ymm4,%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e3 d5 ce 31 7b vgf2p8affineqb \$0x7b,\(%ecx\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e3 d5 ce 31 7b vgf2p8affineqb \$0x7b,\(%ecx\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e3 d5 ce b4 f4 c0 1d fe ff 7b vgf2p8affineqb \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e3 d5 ce b2 e0 0f 00 00 7b vgf2p8affineqb \$0x7b,0xfe0\(%edx\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e3 d5 ce b2 00 10 00 00 7b vgf2p8affineqb \$0x7b,0x1000\(%edx\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e3 d5 ce b2 00 f0 ff ff 7b vgf2p8affineqb \$0x7b,-0x1000\(%edx\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e3 d5 ce b2 e0 ef ff ff 7b vgf2p8affineqb \$0x7b,-0x1020\(%edx\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e3 d5 cf f4 ab vgf2p8affineinvqb \$0xab,%ymm4,%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e3 d5 cf f4 7b vgf2p8affineinvqb \$0x7b,%ymm4,%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e3 d5 cf 31 7b vgf2p8affineinvqb \$0x7b,\(%ecx\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e3 d5 cf 31 7b vgf2p8affineinvqb \$0x7b,\(%ecx\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e3 d5 cf b4 f4 c0 1d fe ff 7b vgf2p8affineinvqb \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e3 d5 cf b2 e0 0f 00 00 7b vgf2p8affineinvqb \$0x7b,0xfe0\(%edx\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e3 d5 cf b2 00 10 00 00 7b vgf2p8affineinvqb \$0x7b,0x1000\(%edx\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e3 d5 cf b2 00 f0 ff ff 7b vgf2p8affineinvqb \$0x7b,-0x1000\(%edx\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e3 d5 cf b2 e0 ef ff ff 7b vgf2p8affineinvqb \$0x7b,-0x1020\(%edx\),%ymm5,%ymm6
[ ]*[a-f0-9]+: c4 e3 6d 4b fe 40 vblendvpd %ymm4,%ymm6,%ymm2,%ymm7
[ ]*[a-f0-9]+: c4 e3 6d 4b 39 40 vblendvpd %ymm4,\(%ecx\),%ymm2,%ymm7
[ ]*[a-f0-9]+: c4 e3 6d 4b 39 40 vblendvpd %ymm4,\(%ecx\),%ymm2,%ymm7
@@ -2434,6 +2506,14 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c5 c8 c2 d4 1f vcmptrue_usps %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 c8 c2 39 1f vcmptrue_usps \(%ecx\),%xmm6,%xmm7
[ ]*[a-f0-9]+: c5 c8 c2 39 1f vcmptrue_usps \(%ecx\),%xmm6,%xmm7
+[ ]*[a-f0-9]+: c4 e2 51 cf f4 vgf2p8mulb %xmm4,%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e2 51 cf 31 vgf2p8mulb \(%ecx\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e2 51 cf 31 vgf2p8mulb \(%ecx\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e2 51 cf b4 f4 c0 1d fe ff vgf2p8mulb -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e2 51 cf b2 f0 07 00 00 vgf2p8mulb 0x7f0\(%edx\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e2 51 cf b2 00 08 00 00 vgf2p8mulb 0x800\(%edx\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e2 51 cf b2 00 f8 ff ff vgf2p8mulb -0x800\(%edx\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e2 51 cf b2 f0 f7 ff ff vgf2p8mulb -0x810\(%edx\),%xmm5,%xmm6
[ ]*[a-f0-9]+: c4 e2 59 2c 31 vmaskmovps \(%ecx\),%xmm4,%xmm6
[ ]*[a-f0-9]+: c4 e2 59 2c 31 vmaskmovps \(%ecx\),%xmm4,%xmm6
[ ]*[a-f0-9]+: c4 e2 59 2d 31 vmaskmovpd \(%ecx\),%xmm4,%xmm6
@@ -2514,6 +2594,24 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c5 c8 c6 d4 07 vshufps \$0x7,%xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 c8 c6 11 07 vshufps \$0x7,\(%ecx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 c8 c6 11 07 vshufps \$0x7,\(%ecx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 d1 ce f4 ab vgf2p8affineqb \$0xab,%xmm4,%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e3 d1 ce f4 7b vgf2p8affineqb \$0x7b,%xmm4,%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e3 d1 ce 31 7b vgf2p8affineqb \$0x7b,\(%ecx\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e3 d1 ce 31 7b vgf2p8affineqb \$0x7b,\(%ecx\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e3 d1 ce b4 f4 c0 1d fe ff 7b vgf2p8affineqb \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e3 d1 ce b2 f0 07 00 00 7b vgf2p8affineqb \$0x7b,0x7f0\(%edx\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e3 d1 ce b2 00 08 00 00 7b vgf2p8affineqb \$0x7b,0x800\(%edx\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e3 d1 ce b2 00 f8 ff ff 7b vgf2p8affineqb \$0x7b,-0x800\(%edx\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e3 d1 ce b2 f0 f7 ff ff 7b vgf2p8affineqb \$0x7b,-0x810\(%edx\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e3 d1 cf f4 ab vgf2p8affineinvqb \$0xab,%xmm4,%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e3 d1 cf f4 7b vgf2p8affineinvqb \$0x7b,%xmm4,%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e3 d1 cf 31 7b vgf2p8affineinvqb \$0x7b,\(%ecx\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e3 d1 cf 31 7b vgf2p8affineinvqb \$0x7b,\(%ecx\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e3 d1 cf b4 f4 c0 1d fe ff 7b vgf2p8affineinvqb \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e3 d1 cf b2 f0 07 00 00 7b vgf2p8affineinvqb \$0x7b,0x7f0\(%edx\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e3 d1 cf b2 00 08 00 00 7b vgf2p8affineinvqb \$0x7b,0x800\(%edx\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e3 d1 cf b2 00 f8 ff ff 7b vgf2p8affineinvqb \$0x7b,-0x800\(%edx\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e3 d1 cf b2 f0 f7 ff ff 7b vgf2p8affineinvqb \$0x7b,-0x810\(%edx\),%xmm5,%xmm6
[ ]*[a-f0-9]+: c4 e3 69 4b fe 40 vblendvpd %xmm4,%xmm6,%xmm2,%xmm7
[ ]*[a-f0-9]+: c4 e3 69 4b 39 40 vblendvpd %xmm4,\(%ecx\),%xmm2,%xmm7
[ ]*[a-f0-9]+: c4 e3 69 4b 39 40 vblendvpd %xmm4,\(%ecx\),%xmm2,%xmm7
diff --git a/gas/testsuite/gas/i386/avx.s b/gas/testsuite/gas/i386/avx.s
index 0393d86..0867dd2 100644
--- a/gas/testsuite/gas/i386/avx.s
+++ b/gas/testsuite/gas/i386/avx.s
@@ -221,6 +221,13 @@ _start:
vcmpgt_oqps (%ecx),%ymm6,%ymm2
vcmptrue_usps %ymm4,%ymm6,%ymm2
vcmptrue_usps (%ecx),%ymm6,%ymm2
+ vgf2p8mulb %ymm4, %ymm5, %ymm6
+ vgf2p8mulb (%ecx), %ymm5, %ymm6
+ vgf2p8mulb -123456(%esp,%esi,8), %ymm5, %ymm6
+ vgf2p8mulb 4064(%edx), %ymm5, %ymm6
+ vgf2p8mulb 4096(%edx), %ymm5, %ymm6
+ vgf2p8mulb -4096(%edx), %ymm5, %ymm6
+ vgf2p8mulb -4128(%edx), %ymm5, %ymm6
# Tests for op ymm/mem256, xmm
vcvtpd2dqy %ymm4,%xmm4
@@ -309,6 +316,22 @@ _start:
vshufpd $7,(%ecx),%ymm6,%ymm2
vshufps $7,%ymm4,%ymm6,%ymm2
vshufps $7,(%ecx),%ymm6,%ymm2
+ vgf2p8affineqb $0xab, %ymm4, %ymm5, %ymm6
+ vgf2p8affineqb $123, %ymm4, %ymm5, %ymm6
+ vgf2p8affineqb $123, (%ecx), %ymm5, %ymm6
+ vgf2p8affineqb $123, -123456(%esp,%esi,8), %ymm5, %ymm6
+ vgf2p8affineqb $123, 4064(%edx), %ymm5, %ymm6
+ vgf2p8affineqb $123, 4096(%edx), %ymm5, %ymm6
+ vgf2p8affineqb $123, -4096(%edx), %ymm5, %ymm6
+ vgf2p8affineqb $123, -4128(%edx), %ymm5, %ymm6
+ vgf2p8affineinvqb $0xab, %ymm4, %ymm5, %ymm6
+ vgf2p8affineinvqb $123, %ymm4, %ymm5, %ymm6
+ vgf2p8affineinvqb $123, (%ecx), %ymm5, %ymm6
+ vgf2p8affineinvqb $123, -123456(%esp,%esi,8), %ymm5, %ymm6
+ vgf2p8affineinvqb $123, 4064(%edx), %ymm5, %ymm6
+ vgf2p8affineinvqb $123, 4096(%edx), %ymm5, %ymm6
+ vgf2p8affineinvqb $123, -4096(%edx), %ymm5, %ymm6
+ vgf2p8affineinvqb $123, -4128(%edx), %ymm5, %ymm6
# Tests for op ymm, ymm/mem256, ymm, ymm
vblendvpd %ymm4,%ymm6,%ymm2,%ymm7
@@ -783,6 +806,13 @@ _start:
vcmpgt_oqps (%ecx),%xmm6,%xmm7
vcmptrue_usps %xmm4,%xmm6,%xmm2
vcmptrue_usps (%ecx),%xmm6,%xmm7
+ vgf2p8mulb %xmm4, %xmm5, %xmm6
+ vgf2p8mulb (%ecx), %xmm5, %xmm6
+ vgf2p8mulb -123456(%esp,%esi,8), %xmm5, %xmm6
+ vgf2p8mulb 2032(%edx), %xmm5, %xmm6
+ vgf2p8mulb 2048(%edx), %xmm5, %xmm6
+ vgf2p8mulb -2048(%edx), %xmm5, %xmm6
+ vgf2p8mulb -2064(%edx), %xmm5, %xmm6
# Tests for op mem128, xmm, xmm
vmaskmovps (%ecx),%xmm4,%xmm6
@@ -843,6 +873,22 @@ _start:
vshufpd $7,(%ecx),%xmm6,%xmm2
vshufps $7,%xmm4,%xmm6,%xmm2
vshufps $7,(%ecx),%xmm6,%xmm2
+ vgf2p8affineqb $0xab, %xmm4, %xmm5, %xmm6
+ vgf2p8affineqb $123, %xmm4, %xmm5, %xmm6
+ vgf2p8affineqb $123, (%ecx), %xmm5, %xmm6
+ vgf2p8affineqb $123, -123456(%esp,%esi,8), %xmm5, %xmm6
+ vgf2p8affineqb $123, 2032(%edx), %xmm5, %xmm6
+ vgf2p8affineqb $123, 2048(%edx), %xmm5, %xmm6
+ vgf2p8affineqb $123, -2048(%edx), %xmm5, %xmm6
+ vgf2p8affineqb $123, -2064(%edx), %xmm5, %xmm6
+ vgf2p8affineinvqb $0xab, %xmm4, %xmm5, %xmm6
+ vgf2p8affineinvqb $123, %xmm4, %xmm5, %xmm6
+ vgf2p8affineinvqb $123, (%ecx), %xmm5, %xmm6
+ vgf2p8affineinvqb $123, -123456(%esp,%esi,8), %xmm5, %xmm6
+ vgf2p8affineinvqb $123, 2032(%edx), %xmm5, %xmm6
+ vgf2p8affineinvqb $123, 2048(%edx), %xmm5, %xmm6
+ vgf2p8affineinvqb $123, -2048(%edx), %xmm5, %xmm6
+ vgf2p8affineinvqb $123, -2064(%edx), %xmm5, %xmm6
# Tests for op xmm, xmm/mem128, xmm, xmm
vblendvpd %xmm4,%xmm6,%xmm2,%xmm7
@@ -1777,6 +1823,14 @@ _start:
vcmptrue_usps ymm2,ymm6,ymm4
vcmptrue_usps ymm2,ymm6,YMMWORD PTR [ecx]
vcmptrue_usps ymm2,ymm6,[ecx]
+ vgf2p8mulb ymm6, ymm5, ymm4
+ vgf2p8mulb ymm6, ymm5, YMMWORD PTR [ecx]
+ vgf2p8mulb ymm6, ymm5, [ecx]
+ vgf2p8mulb ymm6, ymm5, YMMWORD PTR [esp+esi*8-123456]
+ vgf2p8mulb ymm6, ymm5, YMMWORD PTR [edx+4064]
+ vgf2p8mulb ymm6, ymm5, YMMWORD PTR [edx+4096]
+ vgf2p8mulb ymm6, ymm5, YMMWORD PTR [edx-4096]
+ vgf2p8mulb ymm6, ymm5, YMMWORD PTR [edx-4128]
# Tests for op ymm/mem256, xmm
vcvtpd2dq xmm4,ymm4
@@ -1902,6 +1956,24 @@ _start:
vshufps ymm2,ymm6,ymm4,7
vshufps ymm2,ymm6,YMMWORD PTR [ecx],7
vshufps ymm2,ymm6,[ecx],7
+ vgf2p8affineqb ymm6, ymm5, ymm4, 0xab
+ vgf2p8affineqb ymm6, ymm5, ymm4, 123
+ vgf2p8affineqb ymm6, ymm5, YMMWORD PTR [ecx], 123
+ vgf2p8affineqb ymm6, ymm5, [ecx], 123
+ vgf2p8affineqb ymm6, ymm5, YMMWORD PTR [esp+esi*8-123456], 123
+ vgf2p8affineqb ymm6, ymm5, YMMWORD PTR [edx+4064], 123
+ vgf2p8affineqb ymm6, ymm5, YMMWORD PTR [edx+4096], 123
+ vgf2p8affineqb ymm6, ymm5, YMMWORD PTR [edx-4096], 123
+ vgf2p8affineqb ymm6, ymm5, YMMWORD PTR [edx-4128], 123
+ vgf2p8affineinvqb ymm6, ymm5, ymm4, 0xab
+ vgf2p8affineinvqb ymm6, ymm5, ymm4, 123
+ vgf2p8affineinvqb ymm6, ymm5, YMMWORD PTR [ecx], 123
+ vgf2p8affineinvqb ymm6, ymm5, [ecx], 123
+ vgf2p8affineinvqb ymm6, ymm5, YMMWORD PTR [esp+esi*8-123456], 123
+ vgf2p8affineinvqb ymm6, ymm5, YMMWORD PTR [edx+4064], 123
+ vgf2p8affineinvqb ymm6, ymm5, YMMWORD PTR [edx+4096], 123
+ vgf2p8affineinvqb ymm6, ymm5, YMMWORD PTR [edx-4096], 123
+ vgf2p8affineinvqb ymm6, ymm5, YMMWORD PTR [edx-4128], 123
# Tests for op ymm, ymm/mem256, ymm, ymm
vblendvpd ymm7,ymm2,ymm6,ymm4
@@ -2603,6 +2675,14 @@ _start:
vcmptrue_usps xmm2,xmm6,xmm4
vcmptrue_usps xmm7,xmm6,XMMWORD PTR [ecx]
vcmptrue_usps xmm7,xmm6,[ecx]
+ vgf2p8mulb xmm6, xmm5, xmm4
+ vgf2p8mulb xmm6, xmm5, XMMWORD PTR [ecx]
+ vgf2p8mulb xmm6, xmm5, [ecx]
+ vgf2p8mulb xmm6, xmm5, XMMWORD PTR [esp+esi*8-123456]
+ vgf2p8mulb xmm6, xmm5, XMMWORD PTR [edx+2032]
+ vgf2p8mulb xmm6, xmm5, XMMWORD PTR [edx+2048]
+ vgf2p8mulb xmm6, xmm5, XMMWORD PTR [edx-2048]
+ vgf2p8mulb xmm6, xmm5, XMMWORD PTR [edx-2064]
# Tests for op mem128, xmm, xmm
vmaskmovps xmm6,xmm4,XMMWORD PTR [ecx]
@@ -2691,6 +2771,24 @@ _start:
vshufps xmm2,xmm6,xmm4,7
vshufps xmm2,xmm6,XMMWORD PTR [ecx],7
vshufps xmm2,xmm6,[ecx],7
+ vgf2p8affineqb xmm6, xmm5, xmm4, 0xab
+ vgf2p8affineqb xmm6, xmm5, xmm4, 123
+ vgf2p8affineqb xmm6, xmm5, XMMWORD PTR [ecx], 123
+ vgf2p8affineqb xmm6, xmm5, [ecx], 123
+ vgf2p8affineqb xmm6, xmm5, XMMWORD PTR [esp+esi*8-123456], 123
+ vgf2p8affineqb xmm6, xmm5, XMMWORD PTR [edx+2032], 123
+ vgf2p8affineqb xmm6, xmm5, XMMWORD PTR [edx+2048], 123
+ vgf2p8affineqb xmm6, xmm5, XMMWORD PTR [edx-2048], 123
+ vgf2p8affineqb xmm6, xmm5, XMMWORD PTR [edx-2064], 123
+ vgf2p8affineinvqb xmm6, xmm5, xmm4, 0xab
+ vgf2p8affineinvqb xmm6, xmm5, xmm4, 123
+ vgf2p8affineinvqb xmm6, xmm5, XMMWORD PTR [ecx], 123
+ vgf2p8affineinvqb xmm6, xmm5, [ecx], 123
+ vgf2p8affineinvqb xmm6, xmm5, XMMWORD PTR [esp+esi*8-123456], 123
+ vgf2p8affineinvqb xmm6, xmm5, XMMWORD PTR [edx+2032], 123
+ vgf2p8affineinvqb xmm6, xmm5, XMMWORD PTR [edx+2048], 123
+ vgf2p8affineinvqb xmm6, xmm5, XMMWORD PTR [edx-2048], 123
+ vgf2p8affineinvqb xmm6, xmm5, XMMWORD PTR [edx-2064], 123
# Tests for op xmm, xmm/mem128, xmm, xmm
vblendvpd xmm7,xmm2,xmm6,xmm4
diff --git a/gas/testsuite/gas/i386/avx512f_gfni-intel.d b/gas/testsuite/gas/i386/avx512f_gfni-intel.d
new file mode 100644
index 0000000..4cb626c
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx512f_gfni-intel.d
@@ -0,0 +1,46 @@
+#as:
+#objdump: -dw -Mintel
+#name: i386 AVX512F/GFNI insns (Intel disassembly)
+#source: avx512f_gfni.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+00000000 <_start>:
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 ce f4 ab[ ]*vgf2p8affineqb zmm6,zmm5,zmm4,0xab
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 4f ce f4 ab[ ]*vgf2p8affineqb zmm6\{k7\},zmm5,zmm4,0xab
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 cf ce f4 ab[ ]*vgf2p8affineqb zmm6\{k7\}\{z\},zmm5,zmm4,0xab
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 ce b4 f4 c0 1d fe ff 7b[ ]*vgf2p8affineqb zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 ce 72 7f 7b[ ]*vgf2p8affineqb zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 58 ce 72 7f 7b[ ]*vgf2p8affineqb zmm6,zmm5,QWORD PTR \[edx\+0x3f8\]\{1to8\},0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 cf f4 ab[ ]*vgf2p8affineinvqb zmm6,zmm5,zmm4,0xab
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 4f cf f4 ab[ ]*vgf2p8affineinvqb zmm6\{k7\},zmm5,zmm4,0xab
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 cf cf f4 ab[ ]*vgf2p8affineinvqb zmm6\{k7\}\{z\},zmm5,zmm4,0xab
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 cf b4 f4 c0 1d fe ff 7b[ ]*vgf2p8affineinvqb zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 cf 72 7f 7b[ ]*vgf2p8affineinvqb zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 58 cf 72 7f 7b[ ]*vgf2p8affineinvqb zmm6,zmm5,QWORD PTR \[edx\+0x3f8\]\{1to8\},0x7b
+[ ]*[a-f0-9]+:[ ]*62 f2 55 48 cf f4[ ]*vgf2p8mulb zmm6,zmm5,zmm4
+[ ]*[a-f0-9]+:[ ]*62 f2 55 4f cf f4[ ]*vgf2p8mulb zmm6\{k7\},zmm5,zmm4
+[ ]*[a-f0-9]+:[ ]*62 f2 55 cf cf f4[ ]*vgf2p8mulb zmm6\{k7\}\{z\},zmm5,zmm4
+[ ]*[a-f0-9]+:[ ]*62 f2 55 48 cf b4 f4 c0 1d fe ff[ ]*vgf2p8mulb zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ ]*[a-f0-9]+:[ ]*62 f2 55 48 cf 72 7f[ ]*vgf2p8mulb zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 ce f4 ab[ ]*vgf2p8affineqb zmm6,zmm5,zmm4,0xab
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 4f ce f4 ab[ ]*vgf2p8affineqb zmm6\{k7\},zmm5,zmm4,0xab
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 cf ce f4 ab[ ]*vgf2p8affineqb zmm6\{k7\}\{z\},zmm5,zmm4,0xab
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 ce b4 f4 c0 1d fe ff 7b[ ]*vgf2p8affineqb zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 ce 72 7f 7b[ ]*vgf2p8affineqb zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 58 ce 72 7f 7b[ ]*vgf2p8affineqb zmm6,zmm5,QWORD PTR \[edx\+0x3f8\]\{1to8\},0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 cf f4 ab[ ]*vgf2p8affineinvqb zmm6,zmm5,zmm4,0xab
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 4f cf f4 ab[ ]*vgf2p8affineinvqb zmm6\{k7\},zmm5,zmm4,0xab
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 cf cf f4 ab[ ]*vgf2p8affineinvqb zmm6\{k7\}\{z\},zmm5,zmm4,0xab
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 cf b4 f4 c0 1d fe ff 7b[ ]*vgf2p8affineinvqb zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 cf 72 7f 7b[ ]*vgf2p8affineinvqb zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 58 cf 72 7f 7b[ ]*vgf2p8affineinvqb zmm6,zmm5,QWORD PTR \[edx\+0x3f8\]\{1to8\},0x7b
+[ ]*[a-f0-9]+:[ ]*62 f2 55 48 cf f4[ ]*vgf2p8mulb zmm6,zmm5,zmm4
+[ ]*[a-f0-9]+:[ ]*62 f2 55 4f cf f4[ ]*vgf2p8mulb zmm6\{k7\},zmm5,zmm4
+[ ]*[a-f0-9]+:[ ]*62 f2 55 cf cf f4[ ]*vgf2p8mulb zmm6\{k7\}\{z\},zmm5,zmm4
+[ ]*[a-f0-9]+:[ ]*62 f2 55 48 cf b4 f4 c0 1d fe ff[ ]*vgf2p8mulb zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ ]*[a-f0-9]+:[ ]*62 f2 55 48 cf 72 7f[ ]*vgf2p8mulb zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
+#pass
diff --git a/gas/testsuite/gas/i386/avx512f_gfni.d b/gas/testsuite/gas/i386/avx512f_gfni.d
new file mode 100644
index 0000000..1f8d56c
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx512f_gfni.d
@@ -0,0 +1,46 @@
+#as:
+#objdump: -dw
+#name: i386 AVX512F/GFNI insns
+#source: avx512f_gfni.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+00000000 <_start>:
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 ce f4 ab[ ]*vgf2p8affineqb \$0xab,%zmm4,%zmm5,%zmm6
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 4f ce f4 ab[ ]*vgf2p8affineqb \$0xab,%zmm4,%zmm5,%zmm6\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 cf ce f4 ab[ ]*vgf2p8affineqb \$0xab,%zmm4,%zmm5,%zmm6\{%k7\}\{z\}
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 ce b4 f4 c0 1d fe ff 7b[ ]*vgf2p8affineqb \$0x7b,-0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 ce 72 7f 7b[ ]*vgf2p8affineqb \$0x7b,0x1fc0\(%edx\),%zmm5,%zmm6
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 58 ce 72 7f 7b[ ]*vgf2p8affineqb \$0x7b,0x3f8\(%edx\)\{1to8\},%zmm5,%zmm6
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 cf f4 ab[ ]*vgf2p8affineinvqb \$0xab,%zmm4,%zmm5,%zmm6
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 4f cf f4 ab[ ]*vgf2p8affineinvqb \$0xab,%zmm4,%zmm5,%zmm6\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 cf cf f4 ab[ ]*vgf2p8affineinvqb \$0xab,%zmm4,%zmm5,%zmm6\{%k7\}\{z\}
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 cf b4 f4 c0 1d fe ff 7b[ ]*vgf2p8affineinvqb \$0x7b,-0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 cf 72 7f 7b[ ]*vgf2p8affineinvqb \$0x7b,0x1fc0\(%edx\),%zmm5,%zmm6
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 58 cf 72 7f 7b[ ]*vgf2p8affineinvqb \$0x7b,0x3f8\(%edx\)\{1to8\},%zmm5,%zmm6
+[ ]*[a-f0-9]+:[ ]*62 f2 55 48 cf f4[ ]*vgf2p8mulb %zmm4,%zmm5,%zmm6
+[ ]*[a-f0-9]+:[ ]*62 f2 55 4f cf f4[ ]*vgf2p8mulb %zmm4,%zmm5,%zmm6\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f2 55 cf cf f4[ ]*vgf2p8mulb %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
+[ ]*[a-f0-9]+:[ ]*62 f2 55 48 cf b4 f4 c0 1d fe ff[ ]*vgf2p8mulb -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
+[ ]*[a-f0-9]+:[ ]*62 f2 55 48 cf 72 7f[ ]*vgf2p8mulb 0x1fc0\(%edx\),%zmm5,%zmm6
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 ce f4 ab[ ]*vgf2p8affineqb \$0xab,%zmm4,%zmm5,%zmm6
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 4f ce f4 ab[ ]*vgf2p8affineqb \$0xab,%zmm4,%zmm5,%zmm6\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 cf ce f4 ab[ ]*vgf2p8affineqb \$0xab,%zmm4,%zmm5,%zmm6\{%k7\}\{z\}
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 ce b4 f4 c0 1d fe ff 7b[ ]*vgf2p8affineqb \$0x7b,-0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 ce 72 7f 7b[ ]*vgf2p8affineqb \$0x7b,0x1fc0\(%edx\),%zmm5,%zmm6
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 58 ce 72 7f 7b[ ]*vgf2p8affineqb \$0x7b,0x3f8\(%edx\)\{1to8\},%zmm5,%zmm6
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 cf f4 ab[ ]*vgf2p8affineinvqb \$0xab,%zmm4,%zmm5,%zmm6
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 4f cf f4 ab[ ]*vgf2p8affineinvqb \$0xab,%zmm4,%zmm5,%zmm6\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 cf cf f4 ab[ ]*vgf2p8affineinvqb \$0xab,%zmm4,%zmm5,%zmm6\{%k7\}\{z\}
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 cf b4 f4 c0 1d fe ff 7b[ ]*vgf2p8affineinvqb \$0x7b,-0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 cf 72 7f 7b[ ]*vgf2p8affineinvqb \$0x7b,0x1fc0\(%edx\),%zmm5,%zmm6
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 58 cf 72 7f 7b[ ]*vgf2p8affineinvqb \$0x7b,0x3f8\(%edx\)\{1to8\},%zmm5,%zmm6
+[ ]*[a-f0-9]+:[ ]*62 f2 55 48 cf f4[ ]*vgf2p8mulb %zmm4,%zmm5,%zmm6
+[ ]*[a-f0-9]+:[ ]*62 f2 55 4f cf f4[ ]*vgf2p8mulb %zmm4,%zmm5,%zmm6\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f2 55 cf cf f4[ ]*vgf2p8mulb %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
+[ ]*[a-f0-9]+:[ ]*62 f2 55 48 cf b4 f4 c0 1d fe ff[ ]*vgf2p8mulb -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
+[ ]*[a-f0-9]+:[ ]*62 f2 55 48 cf 72 7f[ ]*vgf2p8mulb 0x1fc0\(%edx\),%zmm5,%zmm6
+#pass
diff --git a/gas/testsuite/gas/i386/avx512f_gfni.s b/gas/testsuite/gas/i386/avx512f_gfni.s
new file mode 100644
index 0000000..87cda8b
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx512f_gfni.s
@@ -0,0 +1,45 @@
+# Check 32bit AVX512F,GFNI instructions
+
+ .allow_index_reg
+ .text
+_start:
+ vgf2p8affineqb $0xab, %zmm4, %zmm5, %zmm6 # AVX512F,GFNI
+ vgf2p8affineqb $0xab, %zmm4, %zmm5, %zmm6{%k7} # AVX512F,GFNI
+ vgf2p8affineqb $0xab, %zmm4, %zmm5, %zmm6{%k7}{z} # AVX512F,GFNI
+ vgf2p8affineqb $123, -123456(%esp,%esi,8), %zmm5, %zmm6 # AVX512F,GFNI
+ vgf2p8affineqb $123, 8128(%edx), %zmm5, %zmm6 # AVX512F,GFNI Disp8
+ vgf2p8affineqb $123, 1016(%edx){1to8}, %zmm5, %zmm6 # AVX512F,GFNI Disp8
+
+ vgf2p8affineinvqb $0xab, %zmm4, %zmm5, %zmm6 # AVX512F,GFNI
+ vgf2p8affineinvqb $0xab, %zmm4, %zmm5, %zmm6{%k7} # AVX512F,GFNI
+ vgf2p8affineinvqb $0xab, %zmm4, %zmm5, %zmm6{%k7}{z} # AVX512F,GFNI
+ vgf2p8affineinvqb $123, -123456(%esp,%esi,8), %zmm5, %zmm6 # AVX512F,GFNI
+ vgf2p8affineinvqb $123, 8128(%edx), %zmm5, %zmm6 # AVX512F,GFNI Disp8
+ vgf2p8affineinvqb $123, 1016(%edx){1to8}, %zmm5, %zmm6 # AVX512F,GFNI Disp8
+
+ vgf2p8mulb %zmm4, %zmm5, %zmm6 # AVX512F,GFNI
+ vgf2p8mulb %zmm4, %zmm5, %zmm6{%k7} # AVX512F,GFNI
+ vgf2p8mulb %zmm4, %zmm5, %zmm6{%k7}{z} # AVX512F,GFNI
+ vgf2p8mulb -123456(%esp,%esi,8), %zmm5, %zmm6 # AVX512F,GFNI
+ vgf2p8mulb 8128(%edx), %zmm5, %zmm6 # AVX512F,GFNI Disp8
+
+ .intel_syntax noprefix
+ vgf2p8affineqb zmm6, zmm5, zmm4, 0xab # AVX512F,GFNI
+ vgf2p8affineqb zmm6{k7}, zmm5, zmm4, 0xab # AVX512F,GFNI
+ vgf2p8affineqb zmm6{k7}{z}, zmm5, zmm4, 0xab # AVX512F,GFNI
+ vgf2p8affineqb zmm6, zmm5, ZMMWORD PTR [esp+esi*8-123456], 123 # AVX512F,GFNI
+ vgf2p8affineqb zmm6, zmm5, ZMMWORD PTR [edx+8128], 123 # AVX512F,GFNI Disp8
+ vgf2p8affineqb zmm6, zmm5, [edx+1016]{1to8}, 123 # AVX512F,GFNI Disp8
+
+ vgf2p8affineinvqb zmm6, zmm5, zmm4, 0xab # AVX512F,GFNI
+ vgf2p8affineinvqb zmm6{k7}, zmm5, zmm4, 0xab # AVX512F,GFNI
+ vgf2p8affineinvqb zmm6{k7}{z}, zmm5, zmm4, 0xab # AVX512F,GFNI
+ vgf2p8affineinvqb zmm6, zmm5, ZMMWORD PTR [esp+esi*8-123456], 123 # AVX512F,GFNI
+ vgf2p8affineinvqb zmm6, zmm5, ZMMWORD PTR [edx+8128], 123 # AVX512F,GFNI Disp8
+ vgf2p8affineinvqb zmm6, zmm5, [edx+1016]{1to8}, 123 # AVX512F,GFNI Disp8
+
+ vgf2p8mulb zmm6, zmm5, zmm4 # AVX512F,GFNI
+ vgf2p8mulb zmm6{k7}, zmm5, zmm4 # AVX512F,GFNI
+ vgf2p8mulb zmm6{k7}{z}, zmm5, zmm4 # AVX512F,GFNI
+ vgf2p8mulb zmm6, zmm5, ZMMWORD PTR [esp+esi*8-123456] # AVX512F,GFNI
+ vgf2p8mulb zmm6, zmm5, ZMMWORD PTR [edx+8128] # AVX512F,GFNI Disp8
diff --git a/gas/testsuite/gas/i386/avx512vl_gfni-intel.d b/gas/testsuite/gas/i386/avx512vl_gfni-intel.d
new file mode 100644
index 0000000..cce7bde
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx512vl_gfni-intel.d
@@ -0,0 +1,73 @@
+#as:
+#objdump: -dw -Mintel
+#name: i386 AVX512VL/GFNI insns (Intel disassembly)
+#source: avx512vl_gfni.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+00000000 <_start>:
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 0f ce f4 ab[ ]*vgf2p8affineqb xmm6\{k7\},xmm5,xmm4,0xab
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 8f ce f4 ab[ ]*vgf2p8affineqb xmm6\{k7\}\{z\},xmm5,xmm4,0xab
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 0f ce f4 7b[ ]*vgf2p8affineqb xmm6\{k7\},xmm5,xmm4,0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 0f ce b4 f4 c0 1d fe ff 7b[ ]*vgf2p8affineqb xmm6\{k7\},xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 0f ce 72 7f 7b[ ]*vgf2p8affineqb xmm6\{k7\},xmm5,XMMWORD PTR \[edx\+0x7f0\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 1f ce 72 7f 7b[ ]*vgf2p8affineqb xmm6\{k7\},xmm5,QWORD PTR \[edx\+0x3f8\]\{1to2\},0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 2f ce f4 ab[ ]*vgf2p8affineqb ymm6\{k7\},ymm5,ymm4,0xab
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 af ce f4 ab[ ]*vgf2p8affineqb ymm6\{k7\}\{z\},ymm5,ymm4,0xab
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 2f ce f4 7b[ ]*vgf2p8affineqb ymm6\{k7\},ymm5,ymm4,0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 2f ce b4 f4 c0 1d fe ff 7b[ ]*vgf2p8affineqb ymm6\{k7\},ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 2f ce 72 7f 7b[ ]*vgf2p8affineqb ymm6\{k7\},ymm5,YMMWORD PTR \[edx\+0xfe0\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 3f ce 72 7f 7b[ ]*vgf2p8affineqb ymm6\{k7\},ymm5,QWORD PTR \[edx\+0x3f8\]\{1to4\},0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 0f cf f4 ab[ ]*vgf2p8affineinvqb xmm6\{k7\},xmm5,xmm4,0xab
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 8f cf f4 ab[ ]*vgf2p8affineinvqb xmm6\{k7\}\{z\},xmm5,xmm4,0xab
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 0f cf f4 7b[ ]*vgf2p8affineinvqb xmm6\{k7\},xmm5,xmm4,0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 0f cf b4 f4 c0 1d fe ff 7b[ ]*vgf2p8affineinvqb xmm6\{k7\},xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 0f cf 72 7f 7b[ ]*vgf2p8affineinvqb xmm6\{k7\},xmm5,XMMWORD PTR \[edx\+0x7f0\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 1f cf 72 7f 7b[ ]*vgf2p8affineinvqb xmm6\{k7\},xmm5,QWORD PTR \[edx\+0x3f8\]\{1to2\},0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 2f cf f4 ab[ ]*vgf2p8affineinvqb ymm6\{k7\},ymm5,ymm4,0xab
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 af cf f4 ab[ ]*vgf2p8affineinvqb ymm6\{k7\}\{z\},ymm5,ymm4,0xab
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 2f cf f4 7b[ ]*vgf2p8affineinvqb ymm6\{k7\},ymm5,ymm4,0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 2f cf b4 f4 c0 1d fe ff 7b[ ]*vgf2p8affineinvqb ymm6\{k7\},ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 2f cf 72 7f 7b[ ]*vgf2p8affineinvqb ymm6\{k7\},ymm5,YMMWORD PTR \[edx\+0xfe0\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 3f cf 72 7f 7b[ ]*vgf2p8affineinvqb ymm6\{k7\},ymm5,QWORD PTR \[edx\+0x3f8\]\{1to4\},0x7b
+[ ]*[a-f0-9]+:[ ]*62 f2 55 0f cf f4[ ]*vgf2p8mulb xmm6\{k7\},xmm5,xmm4
+[ ]*[a-f0-9]+:[ ]*62 f2 55 8f cf f4[ ]*vgf2p8mulb xmm6\{k7\}\{z\},xmm5,xmm4
+[ ]*[a-f0-9]+:[ ]*62 f2 55 0f cf b4 f4 c0 1d fe ff[ ]*vgf2p8mulb xmm6\{k7\},xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ ]*[a-f0-9]+:[ ]*62 f2 55 0f cf 72 7f[ ]*vgf2p8mulb xmm6\{k7\},xmm5,XMMWORD PTR \[edx\+0x7f0\]
+[ ]*[a-f0-9]+:[ ]*62 f2 55 2f cf f4[ ]*vgf2p8mulb ymm6\{k7\},ymm5,ymm4
+[ ]*[a-f0-9]+:[ ]*62 f2 55 af cf f4[ ]*vgf2p8mulb ymm6\{k7\}\{z\},ymm5,ymm4
+[ ]*[a-f0-9]+:[ ]*62 f2 55 2f cf b4 f4 c0 1d fe ff[ ]*vgf2p8mulb ymm6\{k7\},ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ ]*[a-f0-9]+:[ ]*62 f2 55 2f cf 72 7f[ ]*vgf2p8mulb ymm6\{k7\},ymm5,YMMWORD PTR \[edx\+0xfe0\]
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 0f ce f4 ab[ ]*vgf2p8affineqb xmm6\{k7\},xmm5,xmm4,0xab
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 8f ce f4 ab[ ]*vgf2p8affineqb xmm6\{k7\}\{z\},xmm5,xmm4,0xab
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 0f ce b4 f4 c0 1d fe ff 7b[ ]*vgf2p8affineqb xmm6\{k7\},xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 0f ce 72 7f 7b[ ]*vgf2p8affineqb xmm6\{k7\},xmm5,XMMWORD PTR \[edx\+0x7f0\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 1f ce 72 7f 7b[ ]*vgf2p8affineqb xmm6\{k7\},xmm5,QWORD PTR \[edx\+0x3f8\]\{1to2\},0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 2f ce f4 ab[ ]*vgf2p8affineqb ymm6\{k7\},ymm5,ymm4,0xab
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 af ce f4 ab[ ]*vgf2p8affineqb ymm6\{k7\}\{z\},ymm5,ymm4,0xab
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 2f ce b4 f4 c0 1d fe ff 7b[ ]*vgf2p8affineqb ymm6\{k7\},ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 2f ce 72 7f 7b[ ]*vgf2p8affineqb ymm6\{k7\},ymm5,YMMWORD PTR \[edx\+0xfe0\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 3f ce 72 7f 7b[ ]*vgf2p8affineqb ymm6\{k7\},ymm5,QWORD PTR \[edx\+0x3f8\]\{1to4\},0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 0f cf f4 ab[ ]*vgf2p8affineinvqb xmm6\{k7\},xmm5,xmm4,0xab
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 8f cf f4 ab[ ]*vgf2p8affineinvqb xmm6\{k7\}\{z\},xmm5,xmm4,0xab
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 0f cf b4 f4 c0 1d fe ff 7b[ ]*vgf2p8affineinvqb xmm6\{k7\},xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 0f cf 72 7f 7b[ ]*vgf2p8affineinvqb xmm6\{k7\},xmm5,XMMWORD PTR \[edx\+0x7f0\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 1f cf 72 7f 7b[ ]*vgf2p8affineinvqb xmm6\{k7\},xmm5,QWORD PTR \[edx\+0x3f8\]\{1to2\},0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 2f cf f4 ab[ ]*vgf2p8affineinvqb ymm6\{k7\},ymm5,ymm4,0xab
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 af cf f4 ab[ ]*vgf2p8affineinvqb ymm6\{k7\}\{z\},ymm5,ymm4,0xab
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 2f cf b4 f4 c0 1d fe ff 7b[ ]*vgf2p8affineinvqb ymm6\{k7\},ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 3f cf 30 7b[ ]*vgf2p8affineinvqb ymm6\{k7\},ymm5,QWORD PTR \[eax\]\{1to4\},0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 2f cf 72 7f 7b[ ]*vgf2p8affineinvqb ymm6\{k7\},ymm5,YMMWORD PTR \[edx\+0xfe0\],0x7b
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 3f cf 72 7f 7b[ ]*vgf2p8affineinvqb ymm6\{k7\},ymm5,QWORD PTR \[edx\+0x3f8\]\{1to4\},0x7b
+[ ]*[a-f0-9]+:[ ]*62 f2 55 0f cf f4[ ]*vgf2p8mulb xmm6\{k7\},xmm5,xmm4
+[ ]*[a-f0-9]+:[ ]*62 f2 55 8f cf f4[ ]*vgf2p8mulb xmm6\{k7\}\{z\},xmm5,xmm4
+[ ]*[a-f0-9]+:[ ]*62 f2 55 0f cf b4 f4 c0 1d fe ff[ ]*vgf2p8mulb xmm6\{k7\},xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ ]*[a-f0-9]+:[ ]*62 f2 55 0f cf 72 7f[ ]*vgf2p8mulb xmm6\{k7\},xmm5,XMMWORD PTR \[edx\+0x7f0\]
+[ ]*[a-f0-9]+:[ ]*62 f2 55 2f cf f4[ ]*vgf2p8mulb ymm6\{k7\},ymm5,ymm4
+[ ]*[a-f0-9]+:[ ]*62 f2 55 af cf f4[ ]*vgf2p8mulb ymm6\{k7\}\{z\},ymm5,ymm4
+[ ]*[a-f0-9]+:[ ]*62 f2 55 2f cf b4 f4 c0 1d fe ff[ ]*vgf2p8mulb ymm6\{k7\},ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ ]*[a-f0-9]+:[ ]*62 f2 55 2f cf 72 7f[ ]*vgf2p8mulb ymm6\{k7\},ymm5,YMMWORD PTR \[edx\+0xfe0\]
+#pass
diff --git a/gas/testsuite/gas/i386/avx512vl_gfni.d b/gas/testsuite/gas/i386/avx512vl_gfni.d
new file mode 100644
index 0000000..8314d94
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx512vl_gfni.d
@@ -0,0 +1,73 @@
+#as:
+#objdump: -dw
+#name: i386 AVX512VL/GFNI insns
+#source: avx512vl_gfni.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+00000000 <_start>:
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 0f ce f4 ab[ ]*vgf2p8affineqb \$0xab,%xmm4,%xmm5,%xmm6\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 8f ce f4 ab[ ]*vgf2p8affineqb \$0xab,%xmm4,%xmm5,%xmm6\{%k7\}\{z\}
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 0f ce f4 7b[ ]*vgf2p8affineqb \$0x7b,%xmm4,%xmm5,%xmm6\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 0f ce b4 f4 c0 1d fe ff 7b[ ]*vgf2p8affineqb \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm5,%xmm6\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 0f ce 72 7f 7b[ ]*vgf2p8affineqb \$0x7b,0x7f0\(%edx\),%xmm5,%xmm6\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 1f ce 72 7f 7b[ ]*vgf2p8affineqb \$0x7b,0x3f8\(%edx\)\{1to2\},%xmm5,%xmm6\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 2f ce f4 ab[ ]*vgf2p8affineqb \$0xab,%ymm4,%ymm5,%ymm6\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 af ce f4 ab[ ]*vgf2p8affineqb \$0xab,%ymm4,%ymm5,%ymm6\{%k7\}\{z\}
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 2f ce f4 7b[ ]*vgf2p8affineqb \$0x7b,%ymm4,%ymm5,%ymm6\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 2f ce b4 f4 c0 1d fe ff 7b[ ]*vgf2p8affineqb \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm5,%ymm6\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 2f ce 72 7f 7b[ ]*vgf2p8affineqb \$0x7b,0xfe0\(%edx\),%ymm5,%ymm6\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 3f ce 72 7f 7b[ ]*vgf2p8affineqb \$0x7b,0x3f8\(%edx\)\{1to4\},%ymm5,%ymm6\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 0f cf f4 ab[ ]*vgf2p8affineinvqb \$0xab,%xmm4,%xmm5,%xmm6\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 8f cf f4 ab[ ]*vgf2p8affineinvqb \$0xab,%xmm4,%xmm5,%xmm6\{%k7\}\{z\}
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 0f cf f4 7b[ ]*vgf2p8affineinvqb \$0x7b,%xmm4,%xmm5,%xmm6\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 0f cf b4 f4 c0 1d fe ff 7b[ ]*vgf2p8affineinvqb \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm5,%xmm6\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 0f cf 72 7f 7b[ ]*vgf2p8affineinvqb \$0x7b,0x7f0\(%edx\),%xmm5,%xmm6\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 1f cf 72 7f 7b[ ]*vgf2p8affineinvqb \$0x7b,0x3f8\(%edx\)\{1to2\},%xmm5,%xmm6\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 2f cf f4 ab[ ]*vgf2p8affineinvqb \$0xab,%ymm4,%ymm5,%ymm6\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 af cf f4 ab[ ]*vgf2p8affineinvqb \$0xab,%ymm4,%ymm5,%ymm6\{%k7\}\{z\}
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 2f cf f4 7b[ ]*vgf2p8affineinvqb \$0x7b,%ymm4,%ymm5,%ymm6\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 2f cf b4 f4 c0 1d fe ff 7b[ ]*vgf2p8affineinvqb \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm5,%ymm6\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 2f cf 72 7f 7b[ ]*vgf2p8affineinvqb \$0x7b,0xfe0\(%edx\),%ymm5,%ymm6\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 3f cf 72 7f 7b[ ]*vgf2p8affineinvqb \$0x7b,0x3f8\(%edx\)\{1to4\},%ymm5,%ymm6\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f2 55 0f cf f4[ ]*vgf2p8mulb %xmm4,%xmm5,%xmm6\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f2 55 8f cf f4[ ]*vgf2p8mulb %xmm4,%xmm5,%xmm6\{%k7\}\{z\}
+[ ]*[a-f0-9]+:[ ]*62 f2 55 0f cf b4 f4 c0 1d fe ff[ ]*vgf2p8mulb -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f2 55 0f cf 72 7f[ ]*vgf2p8mulb 0x7f0\(%edx\),%xmm5,%xmm6\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f2 55 2f cf f4[ ]*vgf2p8mulb %ymm4,%ymm5,%ymm6\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f2 55 af cf f4[ ]*vgf2p8mulb %ymm4,%ymm5,%ymm6\{%k7\}\{z\}
+[ ]*[a-f0-9]+:[ ]*62 f2 55 2f cf b4 f4 c0 1d fe ff[ ]*vgf2p8mulb -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f2 55 2f cf 72 7f[ ]*vgf2p8mulb 0xfe0\(%edx\),%ymm5,%ymm6\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 0f ce f4 ab[ ]*vgf2p8affineqb \$0xab,%xmm4,%xmm5,%xmm6\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 8f ce f4 ab[ ]*vgf2p8affineqb \$0xab,%xmm4,%xmm5,%xmm6\{%k7\}\{z\}
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 0f ce b4 f4 c0 1d fe ff 7b[ ]*vgf2p8affineqb \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm5,%xmm6\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 0f ce 72 7f 7b[ ]*vgf2p8affineqb \$0x7b,0x7f0\(%edx\),%xmm5,%xmm6\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 1f ce 72 7f 7b[ ]*vgf2p8affineqb \$0x7b,0x3f8\(%edx\)\{1to2\},%xmm5,%xmm6\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 2f ce f4 ab[ ]*vgf2p8affineqb \$0xab,%ymm4,%ymm5,%ymm6\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 af ce f4 ab[ ]*vgf2p8affineqb \$0xab,%ymm4,%ymm5,%ymm6\{%k7\}\{z\}
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 2f ce b4 f4 c0 1d fe ff 7b[ ]*vgf2p8affineqb \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm5,%ymm6\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 2f ce 72 7f 7b[ ]*vgf2p8affineqb \$0x7b,0xfe0\(%edx\),%ymm5,%ymm6\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 3f ce 72 7f 7b[ ]*vgf2p8affineqb \$0x7b,0x3f8\(%edx\)\{1to4\},%ymm5,%ymm6\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 0f cf f4 ab[ ]*vgf2p8affineinvqb \$0xab,%xmm4,%xmm5,%xmm6\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 8f cf f4 ab[ ]*vgf2p8affineinvqb \$0xab,%xmm4,%xmm5,%xmm6\{%k7\}\{z\}
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 0f cf b4 f4 c0 1d fe ff 7b[ ]*vgf2p8affineinvqb \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm5,%xmm6\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 0f cf 72 7f 7b[ ]*vgf2p8affineinvqb \$0x7b,0x7f0\(%edx\),%xmm5,%xmm6\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 1f cf 72 7f 7b[ ]*vgf2p8affineinvqb \$0x7b,0x3f8\(%edx\)\{1to2\},%xmm5,%xmm6\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 2f cf f4 ab[ ]*vgf2p8affineinvqb \$0xab,%ymm4,%ymm5,%ymm6\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 af cf f4 ab[ ]*vgf2p8affineinvqb \$0xab,%ymm4,%ymm5,%ymm6\{%k7\}\{z\}
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 2f cf b4 f4 c0 1d fe ff 7b[ ]*vgf2p8affineinvqb \$0x7b,-0x1e240\(%esp,%esi,8\),%ymm5,%ymm6\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 3f cf 30 7b[ ]*vgf2p8affineinvqb \$0x7b,\(%eax\)\{1to4\},%ymm5,%ymm6\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 2f cf 72 7f 7b[ ]*vgf2p8affineinvqb \$0x7b,0xfe0\(%edx\),%ymm5,%ymm6\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f3 d5 3f cf 72 7f 7b[ ]*vgf2p8affineinvqb \$0x7b,0x3f8\(%edx\)\{1to4\},%ymm5,%ymm6\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f2 55 0f cf f4[ ]*vgf2p8mulb %xmm4,%xmm5,%xmm6\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f2 55 8f cf f4[ ]*vgf2p8mulb %xmm4,%xmm5,%xmm6\{%k7\}\{z\}
+[ ]*[a-f0-9]+:[ ]*62 f2 55 0f cf b4 f4 c0 1d fe ff[ ]*vgf2p8mulb -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f2 55 0f cf 72 7f[ ]*vgf2p8mulb 0x7f0\(%edx\),%xmm5,%xmm6\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f2 55 2f cf f4[ ]*vgf2p8mulb %ymm4,%ymm5,%ymm6\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f2 55 af cf f4[ ]*vgf2p8mulb %ymm4,%ymm5,%ymm6\{%k7\}\{z\}
+[ ]*[a-f0-9]+:[ ]*62 f2 55 2f cf b4 f4 c0 1d fe ff[ ]*vgf2p8mulb -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6\{%k7\}
+[ ]*[a-f0-9]+:[ ]*62 f2 55 2f cf 72 7f[ ]*vgf2p8mulb 0xfe0\(%edx\),%ymm5,%ymm6\{%k7\}
+#pass
diff --git a/gas/testsuite/gas/i386/avx512vl_gfni.s b/gas/testsuite/gas/i386/avx512vl_gfni.s
new file mode 100644
index 0000000..d288f22
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx512vl_gfni.s
@@ -0,0 +1,72 @@
+# Check 32bit AVX512VL,GFNI instructions
+
+ .allow_index_reg
+ .text
+_start:
+ vgf2p8affineqb $0xab, %xmm4, %xmm5, %xmm6{%k7} # AVX512VL,GFNI
+ vgf2p8affineqb $0xab, %xmm4, %xmm5, %xmm6{%k7}{z} # AVX512VL,GFNI
+ vgf2p8affineqb $123, %xmm4, %xmm5, %xmm6{%k7} # AVX512VL,GFNI
+ vgf2p8affineqb $123, -123456(%esp,%esi,8), %xmm5, %xmm6{%k7} # AVX512VL,GFNI
+ vgf2p8affineqb $123, 2032(%edx), %xmm5, %xmm6{%k7} # AVX512VL,GFNI Disp8
+ vgf2p8affineqb $123, 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512VL,GFNI Disp8
+ vgf2p8affineqb $0xab, %ymm4, %ymm5, %ymm6{%k7} # AVX512VL,GFNI
+ vgf2p8affineqb $0xab, %ymm4, %ymm5, %ymm6{%k7}{z} # AVX512VL,GFNI
+ vgf2p8affineqb $123, %ymm4, %ymm5, %ymm6{%k7} # AVX512VL,GFNI
+ vgf2p8affineqb $123, -123456(%esp,%esi,8), %ymm5, %ymm6{%k7} # AVX512VL,GFNI
+ vgf2p8affineqb $123, 4064(%edx), %ymm5, %ymm6{%k7} # AVX512VL,GFNI Disp8
+ vgf2p8affineqb $123, 1016(%edx){1to4}, %ymm5, %ymm6{%k7} # AVX512VL,GFNI Disp8
+
+ vgf2p8affineinvqb $0xab, %xmm4, %xmm5, %xmm6{%k7} # AVX512VL,GFNI
+ vgf2p8affineinvqb $0xab, %xmm4, %xmm5, %xmm6{%k7}{z} # AVX512VL,GFNI
+ vgf2p8affineinvqb $123, %xmm4, %xmm5, %xmm6{%k7} # AVX512VL,GFNI
+ vgf2p8affineinvqb $123, -123456(%esp,%esi,8), %xmm5, %xmm6{%k7} # AVX512VL,GFNI
+ vgf2p8affineinvqb $123, 2032(%edx), %xmm5, %xmm6{%k7} # AVX512VL,GFNI Disp8
+ vgf2p8affineinvqb $123, 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512VL,GFNI Disp8
+ vgf2p8affineinvqb $0xab, %ymm4, %ymm5, %ymm6{%k7} # AVX512VL,GFNI
+ vgf2p8affineinvqb $0xab, %ymm4, %ymm5, %ymm6{%k7}{z} # AVX512VL,GFNI
+ vgf2p8affineinvqb $123, %ymm4, %ymm5, %ymm6{%k7} # AVX512VL,GFNI
+ vgf2p8affineinvqb $123, -123456(%esp,%esi,8), %ymm5, %ymm6{%k7} # AVX512VL,GFNI
+ vgf2p8affineinvqb $123, 4064(%edx), %ymm5, %ymm6{%k7} # AVX512VL,GFNI Disp8
+ vgf2p8affineinvqb $123, 1016(%edx){1to4}, %ymm5, %ymm6{%k7} # AVX512VL,GFNI Disp8
+
+ vgf2p8mulb %xmm4, %xmm5, %xmm6{%k7} # AVX512VL,GFNI
+ vgf2p8mulb %xmm4, %xmm5, %xmm6{%k7}{z} # AVX512VL,GFNI
+ vgf2p8mulb -123456(%esp,%esi,8), %xmm5, %xmm6{%k7} # AVX512VL,GFNI
+ vgf2p8mulb 2032(%edx), %xmm5, %xmm6{%k7} # AVX512VL,GFNI Disp8
+ vgf2p8mulb %ymm4, %ymm5, %ymm6{%k7} # AVX512VL,GFNI
+ vgf2p8mulb %ymm4, %ymm5, %ymm6{%k7}{z} # AVX512VL,GFNI
+ vgf2p8mulb -123456(%esp,%esi,8), %ymm5, %ymm6{%k7} # AVX512VL,GFNI
+ vgf2p8mulb 4064(%edx), %ymm5, %ymm6{%k7} # AVX512VL,GFNI Disp8
+
+ .intel_syntax noprefix
+ vgf2p8affineqb xmm6{k7}, xmm5, xmm4, 0xab # AVX512VL,GFNI
+ vgf2p8affineqb xmm6{k7}{z}, xmm5, xmm4, 0xab # AVX512VL,GFNI
+ vgf2p8affineqb xmm6{k7}, xmm5, XMMWORD PTR [esp+esi*8-123456], 123 # AVX512VL,GFNI
+ vgf2p8affineqb xmm6{k7}, xmm5, XMMWORD PTR [edx+2032], 123 # AVX512VL,GFNI Disp8
+ vgf2p8affineqb xmm6{k7}, xmm5, [edx+1016]{1to2}, 123 # AVX512VL,GFNI Disp8
+ vgf2p8affineqb ymm6{k7}, ymm5, ymm4, 0xab # AVX512VL,GFNI
+ vgf2p8affineqb ymm6{k7}{z}, ymm5, ymm4, 0xab # AVX512VL,GFNI
+ vgf2p8affineqb ymm6{k7}, ymm5, YMMWORD PTR [esp+esi*8-123456], 123 # AVX512VL,GFNI
+ vgf2p8affineqb ymm6{k7}, ymm5, YMMWORD PTR [edx+4064], 123 # AVX512VL,GFNI Disp8
+ vgf2p8affineqb ymm6{k7}, ymm5, [edx+1016]{1to4}, 123 # AVX512VL,GFNI Disp8
+
+ vgf2p8affineinvqb xmm6{k7}, xmm5, xmm4, 0xab # AVX512VL,GFNI
+ vgf2p8affineinvqb xmm6{k7}{z}, xmm5, xmm4, 0xab # AVX512VL,GFNI
+ vgf2p8affineinvqb xmm6{k7}, xmm5, XMMWORD PTR [esp+esi*8-123456], 123 # AVX512VL,GFNI
+ vgf2p8affineinvqb xmm6{k7}, xmm5, XMMWORD PTR [edx+2032], 123 # AVX512VL,GFNI Disp8
+ vgf2p8affineinvqb xmm6{k7}, xmm5, [edx+1016]{1to2}, 123 # AVX512VL,GFNI Disp8
+ vgf2p8affineinvqb ymm6{k7}, ymm5, ymm4, 0xab # AVX512VL,GFNI
+ vgf2p8affineinvqb ymm6{k7}{z}, ymm5, ymm4, 0xab # AVX512VL,GFNI
+ vgf2p8affineinvqb ymm6{k7}, ymm5, YMMWORD PTR [esp+esi*8-123456], 123 # AVX512VL,GFNI
+ vgf2p8affineinvqb ymm6{k7}, ymm5, [eax]{1to4}, 123 # AVX512VL,GFNI
+ vgf2p8affineinvqb ymm6{k7}, ymm5, YMMWORD PTR [edx+4064], 123 # AVX512VL,GFNI Disp8
+ vgf2p8affineinvqb ymm6{k7}, ymm5, [edx+1016]{1to4}, 123 # AVX512VL,GFNI Disp8
+
+ vgf2p8mulb xmm6{k7}, xmm5, xmm4 # AVX512VL,GFNI
+ vgf2p8mulb xmm6{k7}{z}, xmm5, xmm4 # AVX512VL,GFNI
+ vgf2p8mulb xmm6{k7}, xmm5, XMMWORD PTR [esp+esi*8-123456] # AVX512VL,GFNI
+ vgf2p8mulb xmm6{k7}, xmm5, XMMWORD PTR [edx+2032] # AVX512VL,GFNI Disp8
+ vgf2p8mulb ymm6{k7}, ymm5, ymm4 # AVX512VL,GFNI
+ vgf2p8mulb ymm6{k7}{z}, ymm5, ymm4 # AVX512VL,GFNI
+ vgf2p8mulb ymm6{k7}, ymm5, YMMWORD PTR [esp+esi*8-123456] # AVX512VL,GFNI
+ vgf2p8mulb ymm6{k7}, ymm5, YMMWORD PTR [edx+4064] # AVX512VL,GFNI Disp8
diff --git a/gas/testsuite/gas/i386/gfni-intel.d b/gas/testsuite/gas/i386/gfni-intel.d
new file mode 100644
index 0000000..7ee4420
--- /dev/null
+++ b/gas/testsuite/gas/i386/gfni-intel.d
@@ -0,0 +1,30 @@
+#as:
+#objdump: -dw -Mintel
+#name: i386 GFNI insns (Intel disassembly)
+#source: gfni.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+00000000 <_start>:
+[ ]*[a-f0-9]+:[ ]*66 0f 38 cf ec[ ]*gf2p8mulb xmm5,xmm4
+[ ]*[a-f0-9]+:[ ]*66 0f 38 cf ac f4 c0 1d fe ff[ ]*gf2p8mulb xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ ]*[a-f0-9]+:[ ]*66 0f 38 cf aa f0 07 00 00[ ]*gf2p8mulb xmm5,XMMWORD PTR \[edx\+0x7f0\]
+[ ]*[a-f0-9]+:[ ]*66 0f 3a ce ec ab[ ]*gf2p8affineqb xmm5,xmm4,0xab
+[ ]*[a-f0-9]+:[ ]*66 0f 3a ce ac f4 c0 1d fe ff 7b[ ]*gf2p8affineqb xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ ]*[a-f0-9]+:[ ]*66 0f 3a ce aa f0 07 00 00 7b[ ]*gf2p8affineqb xmm5,XMMWORD PTR \[edx\+0x7f0\],0x7b
+[ ]*[a-f0-9]+:[ ]*66 0f 3a cf ec ab[ ]*gf2p8affineinvqb xmm5,xmm4,0xab
+[ ]*[a-f0-9]+:[ ]*66 0f 3a cf ac f4 c0 1d fe ff 7b[ ]*gf2p8affineinvqb xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ ]*[a-f0-9]+:[ ]*66 0f 3a cf aa f0 07 00 00 7b[ ]*gf2p8affineinvqb xmm5,XMMWORD PTR \[edx\+0x7f0\],0x7b
+[ ]*[a-f0-9]+:[ ]*66 0f 38 cf ec[ ]*gf2p8mulb xmm5,xmm4
+[ ]*[a-f0-9]+:[ ]*66 0f 38 cf ac f4 c0 1d fe ff[ ]*gf2p8mulb xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
+[ ]*[a-f0-9]+:[ ]*66 0f 38 cf aa f0 07 00 00[ ]*gf2p8mulb xmm5,XMMWORD PTR \[edx\+0x7f0\]
+[ ]*[a-f0-9]+:[ ]*66 0f 3a ce ec ab[ ]*gf2p8affineqb xmm5,xmm4,0xab
+[ ]*[a-f0-9]+:[ ]*66 0f 3a ce ac f4 c0 1d fe ff 7b[ ]*gf2p8affineqb xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ ]*[a-f0-9]+:[ ]*66 0f 3a ce aa f0 07 00 00 7b[ ]*gf2p8affineqb xmm5,XMMWORD PTR \[edx\+0x7f0\],0x7b
+[ ]*[a-f0-9]+:[ ]*66 0f 3a cf ec ab[ ]*gf2p8affineinvqb xmm5,xmm4,0xab
+[ ]*[a-f0-9]+:[ ]*66 0f 3a cf ac f4 c0 1d fe ff 7b[ ]*gf2p8affineinvqb xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
+[ ]*[a-f0-9]+:[ ]*66 0f 3a cf aa f0 07 00 00 7b[ ]*gf2p8affineinvqb xmm5,XMMWORD PTR \[edx\+0x7f0\],0x7b
+#pass
diff --git a/gas/testsuite/gas/i386/gfni.d b/gas/testsuite/gas/i386/gfni.d
new file mode 100644
index 0000000..9f4e443
--- /dev/null
+++ b/gas/testsuite/gas/i386/gfni.d
@@ -0,0 +1,30 @@
+#as:
+#objdump: -dw
+#name: i386 GFNI insns
+#source: gfni.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+00000000 <_start>:
+[ ]*[a-f0-9]+:[ ]*66 0f 38 cf ec[ ]*gf2p8mulb %xmm4,%xmm5
+[ ]*[a-f0-9]+:[ ]*66 0f 38 cf ac f4 c0 1d fe ff[ ]*gf2p8mulb -0x1e240\(%esp,%esi,8\),%xmm5
+[ ]*[a-f0-9]+:[ ]*66 0f 38 cf aa f0 07 00 00[ ]*gf2p8mulb 0x7f0\(%edx\),%xmm5
+[ ]*[a-f0-9]+:[ ]*66 0f 3a ce ec ab[ ]*gf2p8affineqb \$0xab,%xmm4,%xmm5
+[ ]*[a-f0-9]+:[ ]*66 0f 3a ce ac f4 c0 1d fe ff 7b[ ]*gf2p8affineqb \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm5
+[ ]*[a-f0-9]+:[ ]*66 0f 3a ce aa f0 07 00 00 7b[ ]*gf2p8affineqb \$0x7b,0x7f0\(%edx\),%xmm5
+[ ]*[a-f0-9]+:[ ]*66 0f 3a cf ec ab[ ]*gf2p8affineinvqb \$0xab,%xmm4,%xmm5
+[ ]*[a-f0-9]+:[ ]*66 0f 3a cf ac f4 c0 1d fe ff 7b[ ]*gf2p8affineinvqb \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm5
+[ ]*[a-f0-9]+:[ ]*66 0f 3a cf aa f0 07 00 00 7b[ ]*gf2p8affineinvqb \$0x7b,0x7f0\(%edx\),%xmm5
+[ ]*[a-f0-9]+:[ ]*66 0f 38 cf ec[ ]*gf2p8mulb %xmm4,%xmm5
+[ ]*[a-f0-9]+:[ ]*66 0f 38 cf ac f4 c0 1d fe ff[ ]*gf2p8mulb -0x1e240\(%esp,%esi,8\),%xmm5
+[ ]*[a-f0-9]+:[ ]*66 0f 38 cf aa f0 07 00 00[ ]*gf2p8mulb 0x7f0\(%edx\),%xmm5
+[ ]*[a-f0-9]+:[ ]*66 0f 3a ce ec ab[ ]*gf2p8affineqb \$0xab,%xmm4,%xmm5
+[ ]*[a-f0-9]+:[ ]*66 0f 3a ce ac f4 c0 1d fe ff 7b[ ]*gf2p8affineqb \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm5
+[ ]*[a-f0-9]+:[ ]*66 0f 3a ce aa f0 07 00 00 7b[ ]*gf2p8affineqb \$0x7b,0x7f0\(%edx\),%xmm5
+[ ]*[a-f0-9]+:[ ]*66 0f 3a cf ec ab[ ]*gf2p8affineinvqb \$0xab,%xmm4,%xmm5
+[ ]*[a-f0-9]+:[ ]*66 0f 3a cf ac f4 c0 1d fe ff 7b[ ]*gf2p8affineinvqb \$0x7b,-0x1e240\(%esp,%esi,8\),%xmm5
+[ ]*[a-f0-9]+:[ ]*66 0f 3a cf aa f0 07 00 00 7b[ ]*gf2p8affineinvqb \$0x7b,0x7f0\(%edx\),%xmm5
+#pass
diff --git a/gas/testsuite/gas/i386/gfni.s b/gas/testsuite/gas/i386/gfni.s
new file mode 100644
index 0000000..e4166ec
--- /dev/null
+++ b/gas/testsuite/gas/i386/gfni.s
@@ -0,0 +1,30 @@
+# Check GFNI instructions
+
+ .allow_index_reg
+ .text
+_start:
+ gf2p8mulb %xmm4, %xmm5
+ gf2p8mulb -123456(%esp,%esi,8), %xmm5
+ gf2p8mulb 2032(%edx), %xmm5
+
+ gf2p8affineqb $0xab, %xmm4, %xmm5
+ gf2p8affineqb $123, -123456(%esp,%esi,8), %xmm5
+ gf2p8affineqb $123, 2032(%edx), %xmm5
+
+ gf2p8affineinvqb $0xab, %xmm4, %xmm5
+ gf2p8affineinvqb $123, -123456(%esp,%esi,8), %xmm5
+ gf2p8affineinvqb $123, 2032(%edx), %xmm5
+
+ .intel_syntax noprefix
+
+ gf2p8mulb xmm5, xmm4
+ gf2p8mulb xmm5, XMMWORD PTR [esp+esi*8-123456]
+ gf2p8mulb xmm5, XMMWORD PTR [edx+2032]
+
+ gf2p8affineqb xmm5, xmm4, 0xab
+ gf2p8affineqb xmm5, XMMWORD PTR [esp+esi*8-123456], 123
+ gf2p8affineqb xmm5, XMMWORD PTR [edx+2032], 123
+
+ gf2p8affineinvqb xmm5, xmm4, 0xab
+ gf2p8affineinvqb xmm5, XMMWORD PTR [esp+esi*8-123456], 123
+ gf2p8affineinvqb xmm5, XMMWORD PTR [edx+2032], 123
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index 9967629..b764fb1 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -374,6 +374,10 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
run_dump_test "avx512vbmi2-intel"
run_dump_test "avx512vbmi2_vl"
run_dump_test "avx512vbmi2_vl-intel"
+ run_dump_test "avx512f_gfni"
+ run_dump_test "avx512f_gfni-intel"
+ run_dump_test "avx512vl_gfni"
+ run_dump_test "avx512vl_gfni-intel"
run_dump_test "clzero"
run_dump_test "disassem"
run_dump_test "mwaitx-bdver4"
@@ -383,6 +387,8 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
run_dump_test "rdpid-intel"
run_dump_test "ptwrite"
run_dump_test "ptwrite-intel"
+ run_dump_test "gfni"
+ run_dump_test "gfni-intel"
run_list_test "avx512vl-1" "-al"
run_list_test "avx512vl-2" "-al"
run_dump_test "fpu-bad"
@@ -626,6 +632,8 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
run_dump_test "x86-64-avx-scalar"
run_dump_test "x86-64-avx-scalar-intel"
run_dump_test "x86-64-avx256int"
+ run_dump_test "x86-64-avx_gfni"
+ run_dump_test "x86-64-avx_gfni-intel"
run_dump_test "x86-64-avx256int-intel"
run_dump_test "x86-64-avx2"
run_dump_test "x86-64-avx2-intel"
@@ -799,6 +807,10 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
run_dump_test "x86-64-avx512vbmi2-intel"
run_dump_test "x86-64-avx512vbmi2_vl"
run_dump_test "x86-64-avx512vbmi2_vl-intel"
+ run_dump_test "x86-64-avx512f_gfni"
+ run_dump_test "x86-64-avx512f_gfni-intel"
+ run_dump_test "x86-64-avx512vl_gfni"
+ run_dump_test "x86-64-avx512vl_gfni-intel"
run_dump_test "x86-64-clzero"
run_dump_test "x86-64-mwaitx-bdver4"
run_list_test "x86-64-mwaitx-reg"
@@ -807,6 +819,8 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
run_dump_test "x86-64-rdpid-intel"
run_dump_test "x86-64-ptwrite"
run_dump_test "x86-64-ptwrite-intel"
+ run_dump_test "x86-64-gfni"
+ run_dump_test "x86-64-gfni-intel"
run_dump_test "x86-64-fence-as-lock-add-yes"
run_dump_test "x86-64-fence-as-lock-add-no"
run_dump_test "x86-64-pr20141"
diff --git a/gas/testsuite/gas/i386/ilp32/x86-64-avx-intel.d b/gas/testsuite/gas/i386/ilp32/x86-64-avx-intel.d
index 0a8e09d..632a6ce 100644
--- a/gas/testsuite/gas/i386/ilp32/x86-64-avx-intel.d
+++ b/gas/testsuite/gas/i386/ilp32/x86-64-avx-intel.d
@@ -215,6 +215,13 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c5 cc c2 11 1e vcmpgt_oqps ymm2,ymm6,YMMWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c5 cc c2 d4 1f vcmptrue_usps ymm2,ymm6,ymm4
[ ]*[a-f0-9]+: c5 cc c2 11 1f vcmptrue_usps ymm2,ymm6,YMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 e2 55 cf f4 vgf2p8mulb ymm6,ymm5,ymm4
+[ ]*[a-f0-9]+: c4 e2 55 cf 31 vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 a2 55 cf b4 f0 c0 1d fe ff vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[rax\+r14\*8-0x1e240\]
+[ ]*[a-f0-9]+: c4 e2 55 cf b2 e0 0f 00 00 vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[rdx\+0xfe0\]
+[ ]*[a-f0-9]+: c4 e2 55 cf b2 00 10 00 00 vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[rdx\+0x1000\]
+[ ]*[a-f0-9]+: c4 e2 55 cf b2 00 f0 ff ff vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[rdx-0x1000\]
+[ ]*[a-f0-9]+: c4 e2 55 cf b2 e0 ef ff ff vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[rdx-0x1020\]
[ ]*[a-f0-9]+: c5 ff e6 e4 vcvtpd2dq xmm4,ymm4
[ ]*[a-f0-9]+: c5 ff e6 21 vcvtpd2dq xmm4,YMMWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c5 fd 5a e4 vcvtpd2ps xmm4,ymm4
@@ -291,6 +298,22 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c5 cd c6 11 07 vshufpd ymm2,ymm6,YMMWORD PTR \[rcx\],0x7
[ ]*[a-f0-9]+: c5 cc c6 d4 07 vshufps ymm2,ymm6,ymm4,0x7
[ ]*[a-f0-9]+: c5 cc c6 11 07 vshufps ymm2,ymm6,YMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 d5 ce f4 ab vgf2p8affineqb ymm6,ymm5,ymm4,0xab
+[ ]*[a-f0-9]+: c4 e3 d5 ce f4 7b vgf2p8affineqb ymm6,ymm5,ymm4,0x7b
+[ ]*[a-f0-9]+: c4 e3 d5 ce 31 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[rcx\],0x7b
+[ ]*[a-f0-9]+: c4 a3 d5 ce b4 f0 c0 1d fe ff 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[rax\+r14\*8-0x1e240\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d5 ce b2 e0 0f 00 00 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[rdx\+0xfe0\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d5 ce b2 00 10 00 00 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[rdx\+0x1000\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d5 ce b2 00 f0 ff ff 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[rdx-0x1000\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d5 ce b2 e0 ef ff ff 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[rdx-0x1020\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d5 cf f4 ab vgf2p8affineinvqb ymm6,ymm5,ymm4,0xab
+[ ]*[a-f0-9]+: c4 e3 d5 cf f4 7b vgf2p8affineinvqb ymm6,ymm5,ymm4,0x7b
+[ ]*[a-f0-9]+: c4 e3 d5 cf 31 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[rcx\],0x7b
+[ ]*[a-f0-9]+: c4 a3 d5 cf b4 f0 c0 1d fe ff 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[rax\+r14\*8-0x1e240\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d5 cf b2 e0 0f 00 00 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[rdx\+0xfe0\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d5 cf b2 00 10 00 00 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[rdx\+0x1000\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d5 cf b2 00 f0 ff ff 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[rdx-0x1000\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d5 cf b2 e0 ef ff ff 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[rdx-0x1020\],0x7b
[ ]*[a-f0-9]+: c4 e3 6d 4b fe 40 vblendvpd ymm7,ymm2,ymm6,ymm4
[ ]*[a-f0-9]+: c4 e3 6d 4b 39 40 vblendvpd ymm7,ymm2,YMMWORD PTR \[rcx\],ymm4
[ ]*[a-f0-9]+: c4 e3 6d 4a fe 40 vblendvps ymm7,ymm2,ymm6,ymm4
@@ -745,6 +768,13 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c5 c8 c2 39 1e vcmpgt_oqps xmm7,xmm6,XMMWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c5 c8 c2 d4 1f vcmptrue_usps xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c5 c8 c2 39 1f vcmptrue_usps xmm7,xmm6,XMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 e2 51 cf f4 vgf2p8mulb xmm6,xmm5,xmm4
+[ ]*[a-f0-9]+: c4 e2 51 cf 31 vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 a2 51 cf b4 f0 c0 1d fe ff vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[rax\+r14\*8-0x1e240\]
+[ ]*[a-f0-9]+: c4 e2 51 cf b2 f0 07 00 00 vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[rdx\+0x7f0\]
+[ ]*[a-f0-9]+: c4 e2 51 cf b2 00 08 00 00 vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[rdx\+0x800\]
+[ ]*[a-f0-9]+: c4 e2 51 cf b2 00 f8 ff ff vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[rdx-0x800\]
+[ ]*[a-f0-9]+: c4 e2 51 cf b2 f0 f7 ff ff vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[rdx-0x810\]
[ ]*[a-f0-9]+: c4 e2 59 2c 31 vmaskmovps xmm6,xmm4,XMMWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c4 e2 59 2d 31 vmaskmovpd xmm6,xmm4,XMMWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c4 e3 79 df f4 07 vaeskeygenassist xmm6,xmm4,0x7
@@ -801,6 +831,22 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c5 c9 c6 11 07 vshufpd xmm2,xmm6,XMMWORD PTR \[rcx\],0x7
[ ]*[a-f0-9]+: c5 c8 c6 d4 07 vshufps xmm2,xmm6,xmm4,0x7
[ ]*[a-f0-9]+: c5 c8 c6 11 07 vshufps xmm2,xmm6,XMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 d1 ce f4 ab vgf2p8affineqb xmm6,xmm5,xmm4,0xab
+[ ]*[a-f0-9]+: c4 e3 d1 ce f4 7b vgf2p8affineqb xmm6,xmm5,xmm4,0x7b
+[ ]*[a-f0-9]+: c4 e3 d1 ce 31 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[rcx\],0x7b
+[ ]*[a-f0-9]+: c4 a3 d1 ce b4 f0 c0 1d fe ff 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[rax\+r14\*8-0x1e240\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d1 ce b2 f0 07 00 00 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[rdx\+0x7f0\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d1 ce b2 00 08 00 00 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[rdx\+0x800\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d1 ce b2 00 f8 ff ff 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[rdx-0x800\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d1 ce b2 f0 f7 ff ff 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[rdx-0x810\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d1 cf f4 ab vgf2p8affineinvqb xmm6,xmm5,xmm4,0xab
+[ ]*[a-f0-9]+: c4 e3 d1 cf f4 7b vgf2p8affineinvqb xmm6,xmm5,xmm4,0x7b
+[ ]*[a-f0-9]+: c4 e3 d1 cf 31 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[rcx\],0x7b
+[ ]*[a-f0-9]+: c4 a3 d1 cf b4 f0 c0 1d fe ff 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[rax\+r14\*8-0x1e240\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d1 cf b2 f0 07 00 00 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[rdx\+0x7f0\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d1 cf b2 00 08 00 00 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[rdx\+0x800\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d1 cf b2 00 f8 ff ff 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[rdx-0x800\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d1 cf b2 f0 f7 ff ff 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[rdx-0x810\],0x7b
[ ]*[a-f0-9]+: c4 e3 69 4b fe 40 vblendvpd xmm7,xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c4 e3 69 4b 39 40 vblendvpd xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
[ ]*[a-f0-9]+: c4 e3 69 4a fe 40 vblendvps xmm7,xmm2,xmm6,xmm4
@@ -1803,6 +1849,14 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c5 cc c2 d4 1f vcmptrue_usps ymm2,ymm6,ymm4
[ ]*[a-f0-9]+: c5 cc c2 11 1f vcmptrue_usps ymm2,ymm6,YMMWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c5 cc c2 11 1f vcmptrue_usps ymm2,ymm6,YMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 e2 55 cf f4 vgf2p8mulb ymm6,ymm5,ymm4
+[ ]*[a-f0-9]+: c4 e2 55 cf 31 vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 e2 55 cf 31 vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 a2 55 cf b4 f0 c0 1d fe ff vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[rax\+r14\*8-0x1e240\]
+[ ]*[a-f0-9]+: c4 e2 55 cf b2 e0 0f 00 00 vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[rdx\+0xfe0\]
+[ ]*[a-f0-9]+: c4 e2 55 cf b2 00 10 00 00 vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[rdx\+0x1000\]
+[ ]*[a-f0-9]+: c4 e2 55 cf b2 00 f0 ff ff vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[rdx-0x1000\]
+[ ]*[a-f0-9]+: c4 e2 55 cf b2 e0 ef ff ff vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[rdx-0x1020\]
[ ]*[a-f0-9]+: c5 ff e6 e4 vcvtpd2dq xmm4,ymm4
[ ]*[a-f0-9]+: c5 ff e6 21 vcvtpd2dq xmm4,YMMWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c5 fd 5a e4 vcvtpd2ps xmm4,ymm4
@@ -1916,6 +1970,24 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c5 cc c6 d4 07 vshufps ymm2,ymm6,ymm4,0x7
[ ]*[a-f0-9]+: c5 cc c6 11 07 vshufps ymm2,ymm6,YMMWORD PTR \[rcx\],0x7
[ ]*[a-f0-9]+: c5 cc c6 11 07 vshufps ymm2,ymm6,YMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 d5 ce f4 ab vgf2p8affineqb ymm6,ymm5,ymm4,0xab
+[ ]*[a-f0-9]+: c4 e3 d5 ce f4 7b vgf2p8affineqb ymm6,ymm5,ymm4,0x7b
+[ ]*[a-f0-9]+: c4 e3 d5 ce 31 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[rcx\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d5 ce 31 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[rcx\],0x7b
+[ ]*[a-f0-9]+: c4 a3 d5 ce b4 f0 c0 1d fe ff 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[rax\+r14\*8-0x1e240\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d5 ce b2 e0 0f 00 00 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[rdx\+0xfe0\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d5 ce b2 00 10 00 00 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[rdx\+0x1000\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d5 ce b2 00 f0 ff ff 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[rdx-0x1000\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d5 ce b2 e0 ef ff ff 7b vgf2p8affineqb ymm6,ymm5,YMMWORD PTR \[rdx-0x1020\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d5 cf f4 ab vgf2p8affineinvqb ymm6,ymm5,ymm4,0xab
+[ ]*[a-f0-9]+: c4 e3 d5 cf f4 7b vgf2p8affineinvqb ymm6,ymm5,ymm4,0x7b
+[ ]*[a-f0-9]+: c4 e3 d5 cf 31 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[rcx\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d5 cf 31 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[rcx\],0x7b
+[ ]*[a-f0-9]+: c4 a3 d5 cf b4 f0 c0 1d fe ff 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[rax\+r14\*8-0x1e240\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d5 cf b2 e0 0f 00 00 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[rdx\+0xfe0\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d5 cf b2 00 10 00 00 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[rdx\+0x1000\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d5 cf b2 00 f0 ff ff 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[rdx-0x1000\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d5 cf b2 e0 ef ff ff 7b vgf2p8affineinvqb ymm6,ymm5,YMMWORD PTR \[rdx-0x1020\],0x7b
[ ]*[a-f0-9]+: c4 e3 6d 4b fe 40 vblendvpd ymm7,ymm2,ymm6,ymm4
[ ]*[a-f0-9]+: c4 e3 6d 4b 39 40 vblendvpd ymm7,ymm2,YMMWORD PTR \[rcx\],ymm4
[ ]*[a-f0-9]+: c4 e3 6d 4b 39 40 vblendvpd ymm7,ymm2,YMMWORD PTR \[rcx\],ymm4
@@ -2597,6 +2669,14 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c5 c8 c2 d4 1f vcmptrue_usps xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c5 c8 c2 39 1f vcmptrue_usps xmm7,xmm6,XMMWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c5 c8 c2 39 1f vcmptrue_usps xmm7,xmm6,XMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 e2 51 cf f4 vgf2p8mulb xmm6,xmm5,xmm4
+[ ]*[a-f0-9]+: c4 e2 51 cf 31 vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 e2 51 cf 31 vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 a2 51 cf b4 f0 c0 1d fe ff vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[rax\+r14\*8-0x1e240\]
+[ ]*[a-f0-9]+: c4 e2 51 cf b2 f0 07 00 00 vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[rdx\+0x7f0\]
+[ ]*[a-f0-9]+: c4 e2 51 cf b2 00 08 00 00 vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[rdx\+0x800\]
+[ ]*[a-f0-9]+: c4 e2 51 cf b2 00 f8 ff ff vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[rdx-0x800\]
+[ ]*[a-f0-9]+: c4 e2 51 cf b2 f0 f7 ff ff vgf2p8mulb xmm6,xmm5,XMMWORD PTR \[rdx-0x810\]
[ ]*[a-f0-9]+: c4 e2 59 2c 31 vmaskmovps xmm6,xmm4,XMMWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c4 e2 59 2c 31 vmaskmovps xmm6,xmm4,XMMWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c4 e2 59 2d 31 vmaskmovpd xmm6,xmm4,XMMWORD PTR \[rcx\]
@@ -2677,6 +2757,24 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c5 c8 c6 d4 07 vshufps xmm2,xmm6,xmm4,0x7
[ ]*[a-f0-9]+: c5 c8 c6 11 07 vshufps xmm2,xmm6,XMMWORD PTR \[rcx\],0x7
[ ]*[a-f0-9]+: c5 c8 c6 11 07 vshufps xmm2,xmm6,XMMWORD PTR \[rcx\],0x7
+[ ]*[a-f0-9]+: c4 e3 d1 ce f4 ab vgf2p8affineqb xmm6,xmm5,xmm4,0xab
+[ ]*[a-f0-9]+: c4 e3 d1 ce f4 7b vgf2p8affineqb xmm6,xmm5,xmm4,0x7b
+[ ]*[a-f0-9]+: c4 e3 d1 ce 31 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[rcx\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d1 ce 31 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[rcx\],0x7b
+[ ]*[a-f0-9]+: c4 a3 d1 ce b4 f0 c0 1d fe ff 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[rax\+r14\*8-0x1e240\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d1 ce b2 f0 07 00 00 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[rdx\+0x7f0\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d1 ce b2 00 08 00 00 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[rdx\+0x800\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d1 ce b2 00 f8 ff ff 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[rdx-0x800\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d1 ce b2 f0 f7 ff ff 7b vgf2p8affineqb xmm6,xmm5,XMMWORD PTR \[rdx-0x810\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d1 cf f4 ab vgf2p8affineinvqb xmm6,xmm5,xmm4,0xab
+[ ]*[a-f0-9]+: c4 e3 d1 cf f4 7b vgf2p8affineinvqb xmm6,xmm5,xmm4,0x7b
+[ ]*[a-f0-9]+: c4 e3 d1 cf 31 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[rcx\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d1 cf 31 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[rcx\],0x7b
+[ ]*[a-f0-9]+: c4 a3 d1 cf b4 f0 c0 1d fe ff 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[rax\+r14\*8-0x1e240\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d1 cf b2 f0 07 00 00 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[rdx\+0x7f0\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d1 cf b2 00 08 00 00 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[rdx\+0x800\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d1 cf b2 00 f8 ff ff 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[rdx-0x800\],0x7b
+[ ]*[a-f0-9]+: c4 e3 d1 cf b2 f0 f7 ff ff 7b vgf2p8affineinvqb xmm6,xmm5,XMMWORD PTR \[rdx-0x810\],0x7b
[ ]*[a-f0-9]+: c4 e3 69 4b fe 40 vblendvpd xmm7,xmm2,xmm6,xmm4
[ ]*[a-f0-9]+: c4 e3 69 4b 39 40 vblendvpd xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
[ ]*[a-f0-9]+: c4 e3 69 4b 39 40 vblendvpd xmm7,xmm2,XMMWORD PTR \[rcx\],xmm4
diff --git a/gas/testsuite/gas/i386/ilp32/x86-64-avx.d b/gas/testsuite/gas/i386/ilp32/x86-64-avx.d
index 092c1ef..7391734 100644
--- a/gas/testsuite/gas/i386/ilp32/x86-64-avx.d
+++ b/gas/testsuite/gas/i386/ilp32/x86-64-avx.d
@@ -215,6 +215,13 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c5 cc c2 11 1e vcmpgt_oqps \(%rcx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c2 d4 1f vcmptrue_usps %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c2 11 1f vcmptrue_usps \(%rcx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c4 e2 55 cf f4 vgf2p8mulb %ymm4,%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e2 55 cf 31 vgf2p8mulb \(%rcx\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 a2 55 cf b4 f0 c0 1d fe ff vgf2p8mulb -0x1e240\(%rax,%r14,8\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e2 55 cf b2 e0 0f 00 00 vgf2p8mulb 0xfe0\(%rdx\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e2 55 cf b2 00 10 00 00 vgf2p8mulb 0x1000\(%rdx\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e2 55 cf b2 00 f0 ff ff vgf2p8mulb -0x1000\(%rdx\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e2 55 cf b2 e0 ef ff ff vgf2p8mulb -0x1020\(%rdx\),%ymm5,%ymm6
[ ]*[a-f0-9]+: c5 ff e6 e4 vcvtpd2dq %ymm4,%xmm4
[ ]*[a-f0-9]+: c5 ff e6 21 vcvtpd2dqy \(%rcx\),%xmm4
[ ]*[a-f0-9]+: c5 fd 5a e4 vcvtpd2ps %ymm4,%xmm4
@@ -291,6 +298,22 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c5 cd c6 11 07 vshufpd \$0x7,\(%rcx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c6 d4 07 vshufps \$0x7,%ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c6 11 07 vshufps \$0x7,\(%rcx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c4 e3 d5 ce f4 ab vgf2p8affineqb \$0xab,%ymm4,%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e3 d5 ce f4 7b vgf2p8affineqb \$0x7b,%ymm4,%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e3 d5 ce 31 7b vgf2p8affineqb \$0x7b,\(%rcx\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 a3 d5 ce b4 f0 c0 1d fe ff 7b vgf2p8affineqb \$0x7b,-0x1e240\(%rax,%r14,8\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e3 d5 ce b2 e0 0f 00 00 7b vgf2p8affineqb \$0x7b,0xfe0\(%rdx\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e3 d5 ce b2 00 10 00 00 7b vgf2p8affineqb \$0x7b,0x1000\(%rdx\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e3 d5 ce b2 00 f0 ff ff 7b vgf2p8affineqb \$0x7b,-0x1000\(%rdx\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e3 d5 ce b2 e0 ef ff ff 7b vgf2p8affineqb \$0x7b,-0x1020\(%rdx\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e3 d5 cf f4 ab vgf2p8affineinvqb \$0xab,%ymm4,%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e3 d5 cf f4 7b vgf2p8affineinvqb \$0x7b,%ymm4,%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e3 d5 cf 31 7b vgf2p8affineinvqb \$0x7b,\(%rcx\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 a3 d5 cf b4 f0 c0 1d fe ff 7b vgf2p8affineinvqb \$0x7b,-0x1e240\(%rax,%r14,8\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e3 d5 cf b2 e0 0f 00 00 7b vgf2p8affineinvqb \$0x7b,0xfe0\(%rdx\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e3 d5 cf b2 00 10 00 00 7b vgf2p8affineinvqb \$0x7b,0x1000\(%rdx\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e3 d5 cf b2 00 f0 ff ff 7b vgf2p8affineinvqb \$0x7b,-0x1000\(%rdx\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e3 d5 cf b2 e0 ef ff ff 7b vgf2p8affineinvqb \$0x7b,-0x1020\(%rdx\),%ymm5,%ymm6
[ ]*[a-f0-9]+: c4 e3 6d 4b fe 40 vblendvpd %ymm4,%ymm6,%ymm2,%ymm7
[ ]*[a-f0-9]+: c4 e3 6d 4b 39 40 vblendvpd %ymm4,\(%rcx\),%ymm2,%ymm7
[ ]*[a-f0-9]+: c4 e3 6d 4a fe 40 vblendvps %ymm4,%ymm6,%ymm2,%ymm7
@@ -745,6 +768,13 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c5 c8 c2 39 1e vcmpgt_oqps \(%rcx\),%xmm6,%xmm7
[ ]*[a-f0-9]+: c5 c8 c2 d4 1f vcmptrue_usps %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 c8 c2 39 1f vcmptrue_usps \(%rcx\),%xmm6,%xmm7
+[ ]*[a-f0-9]+: c4 e2 51 cf f4 vgf2p8mulb %xmm4,%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e2 51 cf 31 vgf2p8mulb \(%rcx\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 a2 51 cf b4 f0 c0 1d fe ff vgf2p8mulb -0x1e240\(%rax,%r14,8\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e2 51 cf b2 f0 07 00 00 vgf2p8mulb 0x7f0\(%rdx\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e2 51 cf b2 00 08 00 00 vgf2p8mulb 0x800\(%rdx\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e2 51 cf b2 00 f8 ff ff vgf2p8mulb -0x800\(%rdx\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e2 51 cf b2 f0 f7 ff ff vgf2p8mulb -0x810\(%rdx\),%xmm5,%xmm6
[ ]*[a-f0-9]+: c4 e2 59 2c 31 vmaskmovps \(%rcx\),%xmm4,%xmm6
[ ]*[a-f0-9]+: c4 e2 59 2d 31 vmaskmovpd \(%rcx\),%xmm4,%xmm6
[ ]*[a-f0-9]+: c4 e3 79 df f4 07 vaeskeygenassist \$0x7,%xmm4,%xmm6
@@ -801,6 +831,22 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c5 c9 c6 11 07 vshufpd \$0x7,\(%rcx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 c8 c6 d4 07 vshufps \$0x7,%xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 c8 c6 11 07 vshufps \$0x7,\(%rcx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 d1 ce f4 ab vgf2p8affineqb \$0xab,%xmm4,%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e3 d1 ce f4 7b vgf2p8affineqb \$0x7b,%xmm4,%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e3 d1 ce 31 7b vgf2p8affineqb \$0x7b,\(%rcx\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 a3 d1 ce b4 f0 c0 1d fe ff 7b vgf2p8affineqb \$0x7b,-0x1e240\(%rax,%r14,8\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e3 d1 ce b2 f0 07 00 00 7b vgf2p8affineqb \$0x7b,0x7f0\(%rdx\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e3 d1 ce b2 00 08 00 00 7b vgf2p8affineqb \$0x7b,0x800\(%rdx\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e3 d1 ce b2 00 f8 ff ff 7b vgf2p8affineqb \$0x7b,-0x800\(%rdx\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e3 d1 ce b2 f0 f7 ff ff 7b vgf2p8affineqb \$0x7b,-0x810\(%rdx\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e3 d1 cf f4 ab vgf2p8affineinvqb \$0xab,%xmm4,%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e3 d1 cf f4 7b vgf2p8affineinvqb \$0x7b,%xmm4,%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e3 d1 cf 31 7b vgf2p8affineinvqb \$0x7b,\(%rcx\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 a3 d1 cf b4 f0 c0 1d fe ff 7b vgf2p8affineinvqb \$0x7b,-0x1e240\(%rax,%r14,8\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e3 d1 cf b2 f0 07 00 00 7b vgf2p8affineinvqb \$0x7b,0x7f0\(%rdx\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e3 d1 cf b2 00 08 00 00 7b vgf2p8affineinvqb \$0x7b,0x800\(%rdx\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e3 d1 cf b2 00 f8 ff ff 7b vgf2p8affineinvqb \$0x7b,-0x800\(%rdx\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e3 d1 cf b2 f0 f7 ff ff 7b vgf2p8affineinvqb \$0x7b,-0x810\(%rdx\),%xmm5,%xmm6
[ ]*[a-f0-9]+: c4 e3 69 4b fe 40 vblendvpd %xmm4,%xmm6,%xmm2,%xmm7
[ ]*[a-f0-9]+: c4 e3 69 4b 39 40 vblendvpd %xmm4,\(%rcx\),%xmm2,%xmm7
[ ]*[a-f0-9]+: c4 e3 69 4a fe 40 vblendvps %xmm4,%xmm6,%xmm2,%xmm7
@@ -1803,6 +1849,14 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c5 cc c2 d4 1f vcmptrue_usps %ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c2 11 1f vcmptrue_usps \(%rcx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c2 11 1f vcmptrue_usps \(%rcx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c4 e2 55 cf f4 vgf2p8mulb %ymm4,%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e2 55 cf 31 vgf2p8mulb \(%rcx\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e2 55 cf 31 vgf2p8mulb \(%rcx\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 a2 55 cf b4 f0 c0 1d fe ff vgf2p8mulb -0x1e240\(%rax,%r14,8\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e2 55 cf b2 e0 0f 00 00 vgf2p8mulb 0xfe0\(%rdx\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e2 55 cf b2 00 10 00 00 vgf2p8mulb 0x1000\(%rdx\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e2 55 cf b2 00 f0 ff ff vgf2p8mulb -0x1000\(%rdx\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e2 55 cf b2 e0 ef ff ff vgf2p8mulb -0x1020\(%rdx\),%ymm5,%ymm6
[ ]*[a-f0-9]+: c5 ff e6 e4 vcvtpd2dq %ymm4,%xmm4
[ ]*[a-f0-9]+: c5 ff e6 21 vcvtpd2dqy \(%rcx\),%xmm4
[ ]*[a-f0-9]+: c5 fd 5a e4 vcvtpd2ps %ymm4,%xmm4
@@ -1916,6 +1970,24 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c5 cc c6 d4 07 vshufps \$0x7,%ymm4,%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c6 11 07 vshufps \$0x7,\(%rcx\),%ymm6,%ymm2
[ ]*[a-f0-9]+: c5 cc c6 11 07 vshufps \$0x7,\(%rcx\),%ymm6,%ymm2
+[ ]*[a-f0-9]+: c4 e3 d5 ce f4 ab vgf2p8affineqb \$0xab,%ymm4,%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e3 d5 ce f4 7b vgf2p8affineqb \$0x7b,%ymm4,%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e3 d5 ce 31 7b vgf2p8affineqb \$0x7b,\(%rcx\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e3 d5 ce 31 7b vgf2p8affineqb \$0x7b,\(%rcx\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 a3 d5 ce b4 f0 c0 1d fe ff 7b vgf2p8affineqb \$0x7b,-0x1e240\(%rax,%r14,8\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e3 d5 ce b2 e0 0f 00 00 7b vgf2p8affineqb \$0x7b,0xfe0\(%rdx\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e3 d5 ce b2 00 10 00 00 7b vgf2p8affineqb \$0x7b,0x1000\(%rdx\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e3 d5 ce b2 00 f0 ff ff 7b vgf2p8affineqb \$0x7b,-0x1000\(%rdx\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e3 d5 ce b2 e0 ef ff ff 7b vgf2p8affineqb \$0x7b,-0x1020\(%rdx\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e3 d5 cf f4 ab vgf2p8affineinvqb \$0xab,%ymm4,%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e3 d5 cf f4 7b vgf2p8affineinvqb \$0x7b,%ymm4,%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e3 d5 cf 31 7b vgf2p8affineinvqb \$0x7b,\(%rcx\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e3 d5 cf 31 7b vgf2p8affineinvqb \$0x7b,\(%rcx\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 a3 d5 cf b4 f0 c0 1d fe ff 7b vgf2p8affineinvqb \$0x7b,-0x1e240\(%rax,%r14,8\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e3 d5 cf b2 e0 0f 00 00 7b vgf2p8affineinvqb \$0x7b,0xfe0\(%rdx\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e3 d5 cf b2 00 10 00 00 7b vgf2p8affineinvqb \$0x7b,0x1000\(%rdx\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e3 d5 cf b2 00 f0 ff ff 7b vgf2p8affineinvqb \$0x7b,-0x1000\(%rdx\),%ymm5,%ymm6
+[ ]*[a-f0-9]+: c4 e3 d5 cf b2 e0 ef ff ff 7b vgf2p8affineinvqb \$0x7b,-0x1020\(%rdx\),%ymm5,%ymm6
[ ]*[a-f0-9]+: c4 e3 6d 4b fe 40 vblendvpd %ymm4,%ymm6,%ymm2,%ymm7
[ ]*[a-f0-9]+: c4 e3 6d 4b 39 40 vblendvpd %ymm4,\(%rcx\),%ymm2,%ymm7
[ ]*[a-f0-9]+: c4 e3 6d 4b 39 40 vblendvpd %ymm4,\(%rcx\),%ymm2,%ymm7
@@ -2597,6 +2669,14 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c5 c8 c2 d4 1f vcmptrue_usps %xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 c8 c2 39 1f vcmptrue_usps \(%rcx\),%xmm6,%xmm7
[ ]*[a-f0-9]+: c5 c8 c2 39 1f vcmptrue_usps \(%rcx\),%xmm6,%xmm7
+[ ]*[a-f0-9]+: c4 e2 51 cf f4 vgf2p8mulb %xmm4,%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e2 51 cf 31 vgf2p8mulb \(%rcx\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e2 51 cf 31 vgf2p8mulb \(%rcx\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 a2 51 cf b4 f0 c0 1d fe ff vgf2p8mulb -0x1e240\(%rax,%r14,8\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e2 51 cf b2 f0 07 00 00 vgf2p8mulb 0x7f0\(%rdx\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e2 51 cf b2 00 08 00 00 vgf2p8mulb 0x800\(%rdx\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e2 51 cf b2 00 f8 ff ff vgf2p8mulb -0x800\(%rdx\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e2 51 cf b2 f0 f7 ff ff vgf2p8mulb -0x810\(%rdx\),%xmm5,%xmm6
[ ]*[a-f0-9]+: c4 e2 59 2c 31 vmaskmovps \(%rcx\),%xmm4,%xmm6
[ ]*[a-f0-9]+: c4 e2 59 2c 31 vmaskmovps \(%rcx\),%xmm4,%xmm6
[ ]*[a-f0-9]+: c4 e2 59 2d 31 vmaskmovpd \(%rcx\),%xmm4,%xmm6
@@ -2677,6 +2757,24 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c5 c8 c6 d4 07 vshufps \$0x7,%xmm4,%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 c8 c6 11 07 vshufps \$0x7,\(%rcx\),%xmm6,%xmm2
[ ]*[a-f0-9]+: c5 c8 c6 11 07 vshufps \$0x7,\(%rcx\),%xmm6,%xmm2
+[ ]*[a-f0-9]+: c4 e3 d1 ce f4 ab vgf2p8affineqb \$0xab,%xmm4,%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e3 d1 ce f4 7b vgf2p8affineqb \$0x7b,%xmm4,%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e3 d1 ce 31 7b vgf2p8affineqb \$0x7b,\(%rcx\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e3 d1 ce 31 7b vgf2p8affineqb \$0x7b,\(%rcx\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 a3 d1 ce b4 f0 c0 1d fe ff 7b vgf2p8affineqb \$0x7b,-0x1e240\(%rax,%r14,8\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e3 d1 ce b2 f0 07 00 00 7b vgf2p8affineqb \$0x7b,0x7f0\(%rdx\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e3 d1 ce b2 00 08 00 00 7b vgf2p8affineqb \$0x7b,0x800\(%rdx\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e3 d1 ce b2 00 f8 ff ff 7b vgf2p8affineqb \$0x7b,-0x800\(%rdx\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e3 d1 ce b2 f0 f7 ff ff 7b vgf2p8affineqb \$0x7b,-0x810\(%rdx\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e3 d1 cf f4 ab vgf2p8affineinvqb \$0xab,%xmm4,%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e3 d1 cf f4 7b vgf2p8affineinvqb \$0x7b,%xmm4,%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e3 d1 cf 31 7b vgf2p8affineinvqb \$0x7b,\(%rcx\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e3 d1 cf 31 7b vgf2p8affineinvqb \$0x7b,\(%rcx\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 a3 d1 cf b4 f0 c0 1d fe ff 7b vgf2p8affineinvqb \$0x7b,-0x1e240\(%rax,%r14,8\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e3 d1 cf b2 f0 07 00 00 7b vgf2p8affineinvqb \$0x7b,0x7f0\(%rdx\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e3 d1 cf b2 00 08 00 00 7b vgf2p8affineinvqb \$0x7b,0x800\(%rdx\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e3 d1 cf b2 00 f8 ff ff 7b vgf2p8affineinvqb \$0x7b,-0x800\(%rdx\),%xmm5,%xmm6
+[ ]*[a-f0-9]+: c4 e3 d1 cf b2 f0 f7 ff ff 7b vgf2p8affineinvqb \$0x7b,-0x810\(%rdx\),%xmm5,%xmm6
[ ]*[a-f0-9]+: c4 e3 69 4b fe 40 vblendvpd %xmm4,%xmm6,%xmm2,%xmm7
[ ]*[a-f0-9]+: c4 e3 69 4b 39 40 vblendvpd %xmm4,\(%rcx\),%xmm2,%xmm7
[ ]*[a-f0-9]+: c4 e3 69 4b 39 40 vblendvpd %xmm4,\(%rcx\),%xmm2,%xmm7
diff --git a/gas/testsuite/gas/i386/x86-64-avx-intel.d b/gas/testsuite/gas/i386/x86-64-avx-intel.d
index f7a4ef1..a6f1b58 100644
--- a/gas/testsuite/gas/i386/x86-64-avx-intel.d
+++ b/gas/testsuite/gas/i386/x86-64-avx-intel.d
@@ -215,6 +215,13 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: c5 cc c2 11 1e vcmpgt_oqps ymm2,ymm6,YMMWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c5 cc c2 d4 1f vcmptrue_usps ymm2,ymm6,ymm4
[ ]*[a-f0-9]+: c5 cc c2 11 1f vcmptrue_usps ymm2,ymm6,YMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 e2 55 cf f4 vgf2p8mulb ymm6,ymm5,ymm4
+[ ]*[a-f0-9]+: c4 e2 55 cf 31 vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[rcx\]
+[ ]*[a-f0-9]+: c4 a2 55 cf b4 f0 c0 1d fe ff vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[rax\+r14\*8-0x1e240\]
+[ ]*[a-f0-9]+: c4 e2 55 cf b2 e0 0f 00 00 vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[rdx\+0xfe0\]
+[ ]*[a-f0-9]+: c4 e2 55 cf b2 00 10 00 00 vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[rdx\+0x1000\]
+[ ]*[a-f0-9]+: c4 e2 55 cf b2 00 f0 ff ff vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[rdx-0x1000\]
+[ ]*[a-f0-9]+: c4 e2 55 cf b2 e0 ef ff ff vgf2p8mulb ymm6,ymm5,YMMWORD PTR \[rdx-0x1020\]
[ ]*[a-f0-9]+: c5 ff e6 e4 vcvtpd2dq xmm4,ymm4
[ ]*[a-f0-9]+: c5 ff e6 21 vcvtpd2dq xmm4,YMMWORD PTR \[rcx\]
[ ]*[a-f0-9]+: c5 fd 5a e4 vcvtpd2ps xmm4,ymm4
@@ -291,6 +298,22 @@ Disassembly of sectio[...]
[diff truncated at 100000 bytes]
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