[binutils-gdb] MIPS/opcodes: Remove an incorrect MT ASE reference in MFC0/MTC0 decoding

[Maciej W.Rozycki]

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=fdfb475260daf591d05407ea7affa39122a5b7f6

commit fdfb475260daf591d05407ea7affa39122a5b7f6
Author: Maciej W. Rozycki <macro@imgtec.com>
Date:   Mon May 15 13:04:19 2017 +0100

    MIPS/opcodes: Remove an incorrect MT ASE reference in MFC0/MTC0 decoding
    
    The `sel' operand of CP0 move instructions is a part of the base ISA and
    has nothing to do with the MT ASE.
    
    	opcodes/
    	* mips-dis.c (print_insn_args) <default>: Remove an MT ASE
    	reference in CP0 move operand decoding.

Diff:
---
 opcodes/ChangeLog  | 5 +++++
 opcodes/mips-dis.c | 2 +-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 02408b2..4816a4e 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2017-05-15  Maciej W. Rozycki  <macro@imgtec.com>
+
+	* mips-dis.c (print_insn_args) <default>: Remove an MT ASE
+	reference in CP0 move operand decoding.
+
 2017-05-12  Maciej W. Rozycki  <macro@imgtec.com>
 
 	* mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index 289f501..ab92add 100644
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -1641,7 +1641,7 @@ print_insn_args (struct disassemble_info *info,
 	      && s[2] == 'H'
 	      && opcode->name[strlen (opcode->name) - 1] == '0')
 	    {
-	      /* Coprocessor register 0 with sel field (MT ASE).  */
+	      /* Coprocessor register 0 with sel field.  */
 	      const struct mips_cp0sel_name *n;
 	      unsigned int reg, sel;