[binutils-gdb] MIPS: Add microMIPS XPA support
Maciej W.Rozycki
macro@sourceware.org
Fri Jun 30 06:23:00 GMT 2017
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=909b4e3d5fb8579b3721651c9e64a11e7ec27e5f
commit 909b4e3d5fb8579b3721651c9e64a11e7ec27e5f
Author: Maciej W. Rozycki <macro@imgtec.com>
Date: Fri Jun 30 07:21:56 2017 +0100
MIPS: Add microMIPS XPA support
Add support for the base and Virtualization ASE microMIPS instructions
as per the architecture specifications[1][2][3][4].
Most of this change by Andrew Bennett.
[1] "MIPS Architecture for Programmers Volume II-B: The microMIPS32
Instruction Set", MIPS Technologies, Inc., Document Number: MD00582,
Revision 5.04, January 15, 2014, Section 5.5 "Recoded 32-Bit
Instructions", p. 340
[2] "microMIPS32 Architecture for Programmers Volume IV-i:
Virtualization Module of the microMIPS32 Architecture", MIPS
Technologies, Inc., Document Number: MD00848, Revision 1.06,
December 10, 2013, Section 6.1 "Overview", pp. 133, 136
[3] "MIPS Architecture for Programmers Volume II-B: The microMIPS64
Instruction Set", MIPS Technologies, Inc., Document Number: MD00594,
Revision 5.04, January 15, 2014, Section 5.5 "Recoded 32-Bit
Instructions", pp. 415, 444
[4] "microMIPS64 Architecture for Programmers Volume IV-i:
Virtualization Module of the microMIPS64 Architecture", MIPS
Technologies, Inc., Document Number: MD00849, Revision 1.06,
December 10, 2013, Section 6.1 "Overview", pp. 134-135, 139-140
binutils/
* NEWS: Mention microMIPS XPA support.
opcodes/
* micromips-opc.c (XPA, XPAVZ): New macros.
(micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
"mthgc0".
gas/
* config/tc-mips.c (mips_ases): Add microMIPS XPA support.
* testsuite/gas/mips/micromips@xpa.d: New test.
* testsuite/gas/mips/mips.exp: Run the new test. Enable
`xpa-virt-err' test for `micromips'.
Diff:
---
binutils/ChangeLog | 4 ++++
binutils/NEWS | 3 +++
gas/ChangeLog | 8 ++++++++
gas/config/tc-mips.c | 2 +-
gas/testsuite/gas/mips/micromips@xpa.d | 25 +++++++++++++++++++++++++
gas/testsuite/gas/mips/mips.exp | 7 +++----
opcodes/ChangeLog | 7 +++++++
opcodes/micromips-opc.c | 12 ++++++++++++
8 files changed, 63 insertions(+), 5 deletions(-)
diff --git a/binutils/ChangeLog b/binutils/ChangeLog
index bf39942..0496c99 100644
--- a/binutils/ChangeLog
+++ b/binutils/ChangeLog
@@ -1,5 +1,9 @@
2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
+ * NEWS: Mention microMIPS XPA support.
+
+2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
+
* NEWS: Mention microMIPS Release 5 ISA support.
2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
diff --git a/binutils/NEWS b/binutils/NEWS
index f8f33c7..3019320 100644
--- a/binutils/NEWS
+++ b/binutils/NEWS
@@ -1,5 +1,8 @@
-*- text -*-
+* The MIPS port now supports microMIPS eXtended Physical Addressing (XPA)
+ instructions for assembly and disassembly.
+
* The MIPS port now supports the microMIPS Release 5 ISA for assembly and
disassembly.
diff --git a/gas/ChangeLog b/gas/ChangeLog
index c6fb96a..371fca8 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,6 +1,14 @@
2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
Maciej W. Rozycki <macro@imgtec.com>
+ * config/tc-mips.c (mips_ases): Add microMIPS XPA support.
+ * testsuite/gas/mips/micromips@xpa.d: New test.
+ * testsuite/gas/mips/mips.exp: Run the new test. Enable
+ `xpa-virt-err' test for `micromips'.
+
+2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
+ Maciej W. Rozycki <macro@imgtec.com>
+
* testsuite/gas/mips/micromips@r5.d: New test.
* testsuite/gas/mips/mips.exp: Run the new test.
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index 9b42ef8..e1e6b32 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -1762,7 +1762,7 @@ static const struct mips_ase mips_ases[] = {
{ "xpa", ASE_XPA, 0,
OPTION_XPA, OPTION_NO_XPA,
- 2, 2, -1, -1,
+ 2, 2, 2, 2,
-1 },
{ "mips16e2", ASE_MIPS16E2, 0,
diff --git a/gas/testsuite/gas/mips/micromips@xpa.d b/gas/testsuite/gas/mips/micromips@xpa.d
new file mode 100644
index 0000000..a8ab640
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromips@xpa.d
@@ -0,0 +1,25 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -M cp0-names=mips32r2
+#name: XPA instructions
+#source: xpa.s
+#as: -32 -mxpa -mvirt
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 0041 00f4 mfhc0 v0,c0_random
+[0-9a-f]+ <[^>]*> 0050 00f4 mfhc0 v0,c0_config
+[0-9a-f]+ <[^>]*> 0040 10f4 mfhc0 v0,c0_mvpconf0
+[0-9a-f]+ <[^>]*> 0040 38f4 mfhc0 v0,\$0,7
+[0-9a-f]+ <[^>]*> 0041 02f4 mthc0 v0,c0_random
+[0-9a-f]+ <[^>]*> 0050 02f4 mthc0 v0,c0_config
+[0-9a-f]+ <[^>]*> 0040 12f4 mthc0 v0,c0_mvpconf0
+[0-9a-f]+ <[^>]*> 0040 3af4 mthc0 v0,\$0,7
+[0-9a-f]+ <[^>]*> 0041 04f4 mfhgc0 v0,c0_random
+[0-9a-f]+ <[^>]*> 0050 04f4 mfhgc0 v0,c0_config
+[0-9a-f]+ <[^>]*> 0040 14f4 mfhgc0 v0,c0_mvpconf0
+[0-9a-f]+ <[^>]*> 0040 3cf4 mfhgc0 v0,\$0,7
+[0-9a-f]+ <[^>]*> 0041 06f4 mthgc0 v0,c0_random
+[0-9a-f]+ <[^>]*> 0050 06f4 mthgc0 v0,c0_config
+[0-9a-f]+ <[^>]*> 0040 16f4 mthgc0 v0,c0_mvpconf0
+[0-9a-f]+ <[^>]*> 0040 3ef4 mthgc0 v0,\$0,7
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp
index 793505f..81dfd34 100644
--- a/gas/testsuite/gas/mips/mips.exp
+++ b/gas/testsuite/gas/mips/mips.exp
@@ -1561,10 +1561,9 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test_arches "msa-relax" [mips_arch_list_matching mips32r2 !mips32r6]
run_dump_test_arches "msa-branch" [mips_arch_list_matching mips32r2]
- run_dump_test_arches "xpa" [mips_arch_list_matching mips32r2 !micromips]
- run_dump_test_arches "xpa-err" [mips_arch_list_matching mips32r2 !micromips]
- run_dump_test_arches "xpa-virt-err" \
- [mips_arch_list_matching mips32r2 !micromips]
+ run_dump_test_arches "xpa" [mips_arch_list_matching mips32r2]
+ run_dump_test_arches "xpa-err" [mips_arch_list_matching mips32r2]
+ run_dump_test_arches "xpa-virt-err" [mips_arch_list_matching mips32r2]
run_dump_test_arches "r5" "-32" [mips_arch_list_matching mips32r5]
run_dump_test "pcrel-1"
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index d412db9..81c94e4 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,6 +1,13 @@
2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
Maciej W. Rozycki <macro@imgtec.com>
+ * micromips-opc.c (XPA, XPAVZ): New macros.
+ (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
+ "mthgc0".
+
+2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
+ Maciej W. Rozycki <macro@imgtec.com>
+
* micromips-opc.c (I36): New macro.
(micromips_opcodes): Add "eretnc".
diff --git a/opcodes/micromips-opc.c b/opcodes/micromips-opc.c
index d8edd28..d6234af 100644
--- a/opcodes/micromips-opc.c
+++ b/opcodes/micromips-opc.c
@@ -280,6 +280,10 @@ decode_micromips_operand (const char *p)
#define MSA ASE_MSA
#define MSA64 ASE_MSA64
+/* eXtended Physical Address (XPA) support. */
+#define XPA ASE_XPA
+#define XPAVZ ASE_XPA_VIRT
+
const struct mips_opcode micromips_opcodes[] =
{
/* These instructions appear first so that the disassembler will find
@@ -835,6 +839,10 @@ const struct mips_opcode micromips_opcodes[] =
{"mfc2", "t,G", 0x00004d3c, 0xfc00ffff, WR_1|RD_C2, 0, I1, 0, 0 },
{"mfgc0", "t,G", 0x000004fc, 0xfc00ffff, WR_1|RD_C0, 0, 0, IVIRT, 0 },
{"mfgc0", "t,G,H", 0x000004fc, 0xfc00c7ff, WR_1|RD_C0, 0, 0, IVIRT, 0 },
+{"mfhc0", "t,G", 0x000000f4, 0xfc00ffff, WR_1|RD_C0, 0, 0, XPA, 0 },
+{"mfhc0", "t,G,H", 0x000000f4, 0xfc00c7ff, WR_1|RD_C0, 0, 0, XPA, 0 },
+{"mfhgc0", "t,G", 0x000004f4, 0xfc00ffff, WR_1|RD_C0, 0, 0, XPAVZ, 0 },
+{"mfhgc0", "t,G,H", 0x000004f4, 0xfc00c7ff, WR_1|RD_C0, 0, 0, XPAVZ, 0 },
{"mfhc1", "t,S", 0x5400303b, 0xfc00ffff, WR_1|RD_2|FP_D|LC, 0, I1, 0, 0 },
{"mfhc1", "t,G", 0x5400303b, 0xfc00ffff, WR_1|RD_2|FP_D|LC, 0, I1, 0, 0 },
{"mfhc2", "t,G", 0x00008d3c, 0xfc00ffff, WR_1|RD_C2, 0, I1, 0, 0 },
@@ -881,6 +889,10 @@ const struct mips_opcode micromips_opcodes[] =
{"mtc2", "t,G", 0x00005d3c, 0xfc00ffff, RD_1|WR_C2|WR_CC, 0, I1, 0, 0 },
{"mtgc0", "t,G", 0x000006fc, 0xfc00ffff, RD_1|WR_C0|WR_CC, 0, 0, IVIRT, 0 },
{"mtgc0", "t,G,H", 0x000006fc, 0xfc00c7ff, RD_1|WR_C0|WR_CC, 0, 0, IVIRT, 0 },
+{"mthc0", "t,G", 0x000002f4, 0xfc00ffff, RD_1|WR_C0|WR_CC, 0, 0, XPA, 0 },
+{"mthc0", "t,G,H", 0x000002f4, 0xfc00c7ff, RD_1|WR_C0|WR_CC, 0, 0, XPA, 0 },
+{"mthgc0", "t,G", 0x000006f4, 0xfc00ffff, RD_1|WR_C0|WR_CC, 0, 0, XPAVZ, 0 },
+{"mthgc0", "t,G,H", 0x000006f4, 0xfc00c7ff, RD_1|WR_C0|WR_CC, 0, 0, XPAVZ, 0 },
{"mthc1", "t,S", 0x5400383b, 0xfc00ffff, RD_1|WR_2|FP_D|CM, 0, I1, 0, 0 },
{"mthc1", "t,G", 0x5400383b, 0xfc00ffff, RD_1|WR_2|FP_D|CM, 0, I1, 0, 0 },
{"mthc2", "t,G", 0x00009d3c, 0xfc00ffff, RD_1|WR_C2|WR_CC, 0, I1, 0, 0 },
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