[binutils-gdb/binutils-2_28-branch] RISC-V/GAS: Correct branch relaxation for weak symbols.

[Palmer Dabbelt]

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=bf184ddc059f5a0da39aa929255223c2372d295b

commit bf184ddc059f5a0da39aa929255223c2372d295b
Author: Andrew Waterman <andrew@sifive.com>
Date:   Mon Jan 9 09:22:33 2017 +0000

    RISC-V/GAS: Correct branch relaxation for weak symbols.
    
    gas/ChangeLog
    
    2017-01-09  Andrew Waterman <andrew@sifive.com>
    
    	* config/tc-riscv.c (relaxed_branch_length): Use the long
    	sequence when the target is a weak symbol.

Diff:
---
 gas/ChangeLog         | 34 ++++++++++++++++++++++++++++++++++
 gas/config/tc-riscv.c |  1 +
 2 files changed, 35 insertions(+)

diff --git a/gas/ChangeLog b/gas/ChangeLog
index bcd25a2..72c9db2 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -11,6 +11,40 @@
 	* testsuite/gas/i386/x86-64-avx512_vpopcntdqd.d: Ditto.
 	* testsuite/gas/i386/x86-64-avx512_vpopcntdqd.s: Ditto.
 
+2017-01-09  Andrew Waterman <andrew@sifive.com>
+
+	* config/tc-riscv.c (relaxed_branch_length): Use the long
+	sequence when the target is a weak symbol.
+
+2017-01-04  Szabolcs Nagy  <szabolcs.nagy@arm.com>
+
+	* config/tc-aarch64.c (aarch64_features): Add rcpc.
+	* doc/c-aarch64.texi (AArch64 Extensions): Document rcpc.
+	* testsuite/gas/aarch64/ldst-exclusive-armv8_3.d: Rename to ...
+	* testsuite/gas/aarch64/ldst-rcpc.d: This.
+	* testsuite/gas/aarch64/ldst-exclusive-armv8_3.s: Rename to ...
+	* testsuite/gas/aarch64/ldst-rcpc.s: This.
+	* testsuite/gas/aarch64/ldst-rcpc-armv8_2.d: New test.
+
+2017-01-04  Norm Jacobs  <norm.jacobs@oracle.com>
+
+	PR gas/20992
+	* configure.tgt: Treat sparcv9 as sparc64.
+
+2017-01-03  Kito Cheng  <kito.cheng@gmail.com>
+
+	* config/tc-riscv.c (riscv_set_arch): Whitelist the "q" ISA
+	extension.
+	(riscv_after_parse_args): Set FLOAT_ABI_QUAD when the Q ISA is
+	enabled and no other ABI is specified.
+
+2017-01-03  Dimitar Dimitrov  <dimitar@dinux.eu>
+
+	* config/tc-pru.c (md_number_to_chars): Fix parameter to be
+	valueT, as declared in tc.h.
+	(md_apply_fix): Fix to work on 32-bit hosts.
+>>>>>>> 0115611... RISC-V/GAS: Correct branch relaxation for weak symbols.
+
 2017-01-02  Alan Modra  <amodra@gmail.com>
 
 	Update year range in copyright notice of all files.
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 7f3b6cf..3fe9e63 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -354,6 +354,7 @@ relaxed_branch_length (fragS *fragp, asection *sec, int update)
 
   if (fragp->fr_symbol != NULL
       && S_IS_DEFINED (fragp->fr_symbol)
+      && !S_IS_WEAK (fragp->fr_symbol)
       && sec == S_GET_SEGMENT (fragp->fr_symbol))
     {
       offsetT val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;