src cpu/ChangeLog cpu/m32c.cpu opcodes/ChangeL ...

[dj@sourceware.org]

CVSROOT:	/cvs/src
Module name:	src
Changes by:	dj@sourceware.org	2005-12-14 03:30:08

Modified files:
	cpu            : ChangeLog m32c.cpu 
	opcodes        : ChangeLog m32c-desc.c m32c-opc.c m32c-opc.h 

Log message:
	* m32c.cpu (jsri): Fix order so register names aren't treated as
	symbols.
	(indexb, indexbd, indexbs, indexl, indexld, indexls, indexw,
	indexwd, indexws): Fix encodings.
	
	* m32c-desc.c: Regenerate.
	* m32c-opc.c: Regenerate.
	* m32c-opc.h: Regenerate.

Patches:
http://sourceware.org/cgi-bin/cvsweb.cgi/src/cpu/ChangeLog.diff?cvsroot=src&r1=1.60&r2=1.61
http://sourceware.org/cgi-bin/cvsweb.cgi/src/cpu/m32c.cpu.diff?cvsroot=src&r1=1.7&r2=1.8
http://sourceware.org/cgi-bin/cvsweb.cgi/src/opcodes/ChangeLog.diff?cvsroot=src&r1=1.883&r2=1.884
http://sourceware.org/cgi-bin/cvsweb.cgi/src/opcodes/m32c-desc.c.diff?cvsroot=src&r1=1.8&r2=1.9
http://sourceware.org/cgi-bin/cvsweb.cgi/src/opcodes/m32c-opc.c.diff?cvsroot=src&r1=1.7&r2=1.8
http://sourceware.org/cgi-bin/cvsweb.cgi/src/opcodes/m32c-opc.h.diff?cvsroot=src&r1=1.6&r2=1.7