RE:Request fore review of performance counter access proposal

[Carl Love <cel at us dot ibm dot com>]

I read over this proposal.  If I understand it correctly, you are 
talking about using the perfmon2 interface to interface with the 
performance counters.  So a prerequisite to implement this 
functionality in systemtap is that the perfmon2 interface be 
accepted into the kernel.  Additionally, perfmon2 must have the 
power support as well.
 
The prototypes for the functions seem to be very general in terms of
being able to put any event into any counter.  Also, it looked like 
there was the assumption that you could start and stop counters 
individual.  Both of these assumptions are not valid on Power.  Due 
to the architecture of the Power performance counters there are a 
lot of restrictions.  There are three control registers for the 6 
Power 5 or 8 Power 4 performance counters.  Within the control 
registers there are bit fields that specify the specific event.  
There are also bits that define how the MUXs route the performance 
signals to the counters.  It is these MUXs that cause problems.  
Given two events, you may only be able to put one event in counter A
because routing the signal conflicts with routing the signal for the
other event.  Anyway, as a result of this, the hardware team has 
defined a set of groups for use in the counters.  Each group consist
of 6 Power 5 or 8 Power 4 events.  The group is defined by the 
mmcr0, mmcr1 and mmcra control register settings.  These settings 
define which event is in which counter.  All of the counters are 
started and stopped at the same time, i.e. there is a single control
bit to start and stop the counters.  There is an exception on Power 
5 where two of the counters are always counting and do not respond 
to the start/stop bit.  That is a complication that the perfmon2 
interface must deal with.  

So, you will have a very hard time taking the defined groups for 
Power and making them fit into these very general functions.  As I 
recall, there are some Intel processors (Itanium 64 bit processors) 
where some of the events can only be programmed into a subset of the
counters.  Again, these very general calls will be an issue for 
these Intel events. 
 
            Carl Love