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[patch][rfa] SID --trace-semantics output


Hi,

A client of ours, for whom we're developing a SID port, requested that SID's semantic trace show the actual value stored, accounting for read-only fields and other side effects, rather than showing the value which was attempted to be stored. For example, if a 32 bit register has the value 0x12345678 and is readonly in the 16 most significant bits, then storing the value zero actually results in 0x12340000 being stored. SID currently shows that the register has been set to zero.

The most obvious idea I considered was to have the trace code re-read the stored value; This has problems with potential side effects of doing the read (caching statistics, control registers with side effects on read, etc.).

I eventually came up with the notion that the write/set methods of SID's busses, control registers, memory access methods and hardware write handers could return the actual value written. Current code which does not make use of this can remain unchanged and simply ignore the return value. This allows the tracing code generated by CGEN for sid in the sem.cxx file to work with only a slight modification: For example, these extracts from xstormy16-sem.cxx.

-----------------------

Index: sid/component/cgen-cpu/xstormy16/xstormy16-sem.cxx
===================================================================
RCS file: /cvs/src/src/sid/component/cgen-cpu/xstormy16/xstormy16-sem.cxx,v
retrieving revision 1.7
diff -c -p -r1.7 xstormy16-sem.cxx
*** sid/component/cgen-cpu/xstormy16/xstormy16-sem.cxx 5 Jul 2003 17:07:21 -0000 1.7
--- sid/component/cgen-cpu/xstormy16/xstormy16-sem.cxx 17 Mar 2004 20:48:59 -0000


[ ... ]

*************** if (FLD (f_op2m)) {
*** 59,73 ****
tmp_nvalue = FLD (f_imm16);
{
SI opval = ORSI (ANDSI (current_cpu->h_gr_get (((UINT) 14)), 65436), ORBI (ORBI (EQHI (ANDHI (tmp_nvalue, 255), 0), SLLHI (EQHI (tmp_nvalue, 0), 1)), ORHI (SLLHI (current_cpu->parity (tmp_nvalue), 5), SLLHI (LTQI (SRLHI (tmp_nvalue, MULSI (FLD (f_op2m), 8)), 0), 6))));
! current_cpu->h_gr_set (((UINT) 14), opval);
if (UNLIKELY(current_cpu->trace_result_p))
! current_cpu->trace_stream << "gr" << '[' << ((UINT) 14) << ']' << ":=0x" << hex << opval << dec << " ";
}
{
HI opval = tmp_nvalue;
! current_cpu->SETMEMHI (pc, ANDSI (FLD (f_lmem8), 65534), opval);
if (UNLIKELY(current_cpu->trace_result_p))
! current_cpu->trace_stream << "memory" << '[' << "0x" << hex << (UDI) ANDSI (FLD (f_lmem8), 65534) << dec << ']' << ":=0x" << hex << opval << dec << " ";
}
}
} else {
--- 59,73 ----
tmp_nvalue = FLD (f_imm16);
{
SI opval = ORSI (ANDSI (current_cpu->h_gr_get (((UINT) 14)), 65436), ORBI (ORBI (EQHI (ANDHI (tmp_nvalue, 255), 0), SLLHI (EQHI (tmp_nvalue, 0), 1)), ORHI (SLLHI (current_cpu->parity (tmp_nvalue), 5), SLLHI (LTQI (SRLHI (tmp_nvalue, MULSI (FLD (f_op2m), 8)), 0), 6))));
! SI wval = current_cpu->h_gr_set (((UINT) 14), opval);
if (UNLIKELY(current_cpu->trace_result_p))
! current_cpu->trace_stream << "gr" << '[' << ((UINT) 14) << ']' << ":=0x" << hex << wval << dec << " ";
}
{
HI opval = tmp_nvalue;
! HI wval = current_cpu->SETMEMHI (pc, ANDSI (FLD (f_lmem8), 65534), opval);
if (UNLIKELY(current_cpu->trace_result_p))
! current_cpu->trace_stream << "memory" << '[' << "0x" << hex << (UDI) ANDSI (FLD (f_lmem8), 65534) << dec << ']' << ":=0x" << hex << wval << dec << " ";
}
}
} else {


[ ... ]

*************** xstormy16_sem_bccgrgr (xstormy16_cpu* cu
*** 3803,3811 ****
if (tmp_tmp) {
{
USI opval = FLD (f_rel12);
! current_cpu->branch (opval, npc, status);
if (UNLIKELY(current_cpu->trace_result_p))
! current_cpu->trace_stream << "pc" << ":=0x" << hex << opval << dec << " ";
}
}
}
--- 3803,3811 ----
if (tmp_tmp) {
{
USI opval = FLD (f_rel12);
! USI wval = current_cpu->branch (opval, npc, status);
if (UNLIKELY(current_cpu->trace_result_p))
! current_cpu->trace_stream << "pc" << ":=0x" << hex << wval << dec << " ";
}
}
}


-----------------------------------------------------

The only complication I ran into was that the write methods of the various busses already return a status. I decided that for bus writes, an additional pointer argument could be added which defaults to NULL (for existing callers not using the written value). This applies to all bus 'write' methods as well as callback bus write handlers and callback control register 'set' handlers. Control register 'set' methods can simply return the value which was written.

Though simple in concept, these changes have proved quite pervasive. I've attached the complete patch for SID and for CGEN along with the sample generated code (above) and changes needed to the xstormy16_cpu. If this patch is approved, I will update the other SID ports as necessary before committing.

Of course opinions and ideas are welcome. For example, should this be the way --trace-sem works from now on or should it be a CGEN option?

I have tested this against 'make check-sid' for xstormy16 as well as against the entire toolchain testsuite for the port we're developing.

Dave
Index: sid/component/cgen-cpu/xstormy16/xstormy16.h
===================================================================
RCS file: /cvs/src/src/sid/component/cgen-cpu/xstormy16/xstormy16.h,v
retrieving revision 1.2
diff -c -p -r1.2 xstormy16.h
*** sid/component/cgen-cpu/xstormy16/xstormy16.h	11 Jan 2002 07:25:03 -0000	1.2
--- sid/component/cgen-cpu/xstormy16/xstormy16.h	18 Mar 2004 18:58:20 -0000
***************
*** 1,6 ****
  // xstormy16.h - Hand-written code for the Sanyo Xstormy16 CPU. -*- C++ -*-
  
! // Copyright (C) 1999, 2000 Red Hat.
  // This file is part of SID and is licensed under the GPL.
  // See the file COPYING.SID for conditions for redistribution.
  
--- 1,6 ----
  // xstormy16.h - Hand-written code for the Sanyo Xstormy16 CPU. -*- C++ -*-
  
! // Copyright (C) 1999, 2000, 2004 Red Hat.
  // This file is part of SID and is licensed under the GPL.
  // See the file COPYING.SID for conditions for redistribution.
  
*************** namespace xstormy16
*** 64,73 ****
        void do_holdx ();
        
        // Called by semantic code to perform branches.
!       inline void
        branch (PCADDR new_pc, PCADDR& npc, sem_status& status)
  	{
! 	  npc = new_pc;
  	}
  
        // Called by the semantic code at the end of a non-cti insn.
--- 64,73 ----
        void do_holdx ();
        
        // Called by semantic code to perform branches.
!       inline PCADDR
        branch (PCADDR new_pc, PCADDR& npc, sem_status& status)
  	{
! 	  return npc = new_pc;
  	}
  
        // Called by the semantic code at the end of a non-cti insn.
Index: cgen/sid-cpu.scm
===================================================================
RCS file: /cvs/src/src/cgen/sid-cpu.scm,v
retrieving revision 1.11
diff -c -p -r1.11 sid-cpu.scm
*** cgen/sid-cpu.scm	16 Jul 2003 05:35:47 -0000	1.11
--- cgen/sid-cpu.scm	17 Mar 2004 20:48:47 -0000
***************
*** 1,5 ****
  ; CPU family related simulator generator, excluding decoding and model support.
! ; Copyright (C) 2000, 2002 Red Hat, Inc.
  ; This file is part of CGEN.
  
  ; ***********
--- 1,5 ----
  ; CPU family related simulator generator, excluding decoding and model support.
! ; Copyright (C) 2000, 2002, 2004 Red Hat, Inc.
  ; This file is part of CGEN.
  
  ; ***********
*************** namespace @arch@ {
*** 152,163 ****
         ") const"
         " { " get-code " }"
         "\n"
!        "  inline void "
         (gen-reg-set-fun-name hw)
         " ("
         (if scalar? "" "UINT regno, ")
         type " newval)"
!        " { " set-code " }"
         "\n\n")))
  )
  
--- 152,163 ----
         ") const"
         " { " get-code " }"
         "\n"
!        "  inline " type " "
         (gen-reg-set-fun-name hw)
         " ("
         (if scalar? "" "UINT regno, ")
         type " newval)"
!        " { return " set-code " }"
         "\n\n")))
  )
  
Index: cgen/sid.scm
===================================================================
RCS file: /cvs/src/src/cgen/sid.scm,v
retrieving revision 1.11
diff -c -p -r1.11 sid.scm
*** cgen/sid.scm	16 Jul 2003 05:35:47 -0000	1.11
--- cgen/sid.scm	17 Mar 2004 20:48:47 -0000
***************
*** 1,5 ****
  ; Simulator generator support routines.
! ; Copyright (C) 2000, 2002, 2003 Red Hat, Inc.
  ; This file is part of CGEN.
  
  ; One goal of this file is to provide cover functions for all methods.
--- 1,5 ----
  ; Simulator generator support routines.
! ; Copyright (C) 2000-2004 Red Hat, Inc.
  ; This file is part of CGEN.
  
  ; One goal of this file is to provide cover functions for all methods.
***************
*** 1065,1071 ****
     "  {\n"
     "    " (mode:c-type mode) " opval = " (cx:c newval) ";\n"
     ; Dispatch to setter code if appropriate
!    "    "
     (if (op:setter op)
         (let ((args (car (op:setter op)))
  	     (expr (cadr (op:setter op))))
--- 1065,1071 ----
     "  {\n"
     "    " (mode:c-type mode) " opval = " (cx:c newval) ";\n"
     ; Dispatch to setter code if appropriate
!    "    " (mode:c-type mode) " wval = "
     (if (op:setter op)
         (let ((args (car (op:setter op)))
  	     (expr (cadr (op:setter op))))
***************
*** 1118,1124 ****
  	    (if (mode:eq? 'UQI mode)
  		"(USI) "
  		""))
! 	"opval << dec << \"  \";\n"))
     "  }\n")
  )
  
--- 1118,1124 ----
  	    (if (mode:eq? 'UQI mode)
  		"(USI) "
  		""))
! 	"wval << dec << \"  \";\n"))
     "  }\n")
  )
  
Index: cgen/utils.scm
===================================================================
RCS file: /cvs/src/src/cgen/utils.scm,v
retrieving revision 1.11
diff -c -p -r1.11 utils.scm
*** cgen/utils.scm	16 Jul 2003 05:35:48 -0000	1.11
--- cgen/utils.scm	17 Mar 2004 20:48:47 -0000
***************
*** 1,5 ****
  ; Generic Utilities.
! ; Copyright (C) 2000, 2002, 2003 Red Hat, Inc.
  ; This file is part of CGEN.
  ; See file COPYING.CGEN for details.
  
--- 1,5 ----
  ; Generic Utilities.
! ; Copyright (C) 2000-2004 Red Hat, Inc.
  ; This file is part of CGEN.
  ; See file COPYING.CGEN for details.
  
***************
*** 1216,1222 ****
    (cons "\
  THIS FILE IS MACHINE GENERATED WITH CGEN.
  
! Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
  "
  	"\
  This program is free software; you can redistribute it and/or modify
--- 1216,1222 ----
    (cons "\
  THIS FILE IS MACHINE GENERATED WITH CGEN.
  
! Copyright 1996-2004 Free Software Foundation, Inc.
  "
  	"\
  This program is free software; you can redistribute it and/or modify
*************** with this program; if not, write to the 
*** 1241,1247 ****
    (cons "\
  THIS FILE IS MACHINE GENERATED WITH CGEN.
  
! Copyright (C) 2000, 2001, 2002, 2003 Red Hat, Inc.
  "
  	"\
  "))
--- 1241,1247 ----
    (cons "\
  THIS FILE IS MACHINE GENERATED WITH CGEN.
  
! Copyright (C) 2000-2004 Red Hat, Inc.
  "
  	"\
  "))
Index: sid/component/audio/compCodec.cxx
===================================================================
RCS file: /cvs/src/src/sid/component/audio/compCodec.cxx,v
retrieving revision 1.1
diff -c -p -r1.1 compCodec.cxx
*** sid/component/audio/compCodec.cxx	7 Dec 2000 19:30:46 -0000	1.1
--- sid/component/audio/compCodec.cxx	17 Mar 2004 20:48:59 -0000
***************
*** 1,6 ****
  // compCodec.cxx - description.  -*- C++ -*-
  
! // Copyright (C) 1999, 2000 Red Hat.
  // This file is part of SID and is licensed under the GPL.
  // See the file COPYING.SID for conditions for redistribution.
  
--- 1,6 ----
  // compCodec.cxx - description.  -*- C++ -*-
  
! // Copyright (C) 1999, 2000, 2004 Red Hat.
  // This file is part of SID and is licensed under the GPL.
  // See the file COPYING.SID for conditions for redistribution.
  
*************** basic_codec::update_txrx_mode_pins ()
*** 71,77 ****
  
  
  bus::status
! basic_codec::reg_write (host_int_4 idx, big_int_4 mask, big_int_4 data)
  {
    bus::status s = bus::ok;
  
--- 71,77 ----
  
  
  bus::status
! basic_codec::reg_write (host_int_4 idx, big_int_4 mask, big_int_4 data, big_int_4 *written)
  {
    bus::status s = bus::ok;
  
*************** basic_codec::reg_write (host_int_4 idx, 
*** 79,93 ****
--- 79,96 ----
      {
      case 0: // tx-count register
        this->tx_count = (this->tx_count & ~mask) | (data & mask);
+       if (written) *written = this->tx_count;
        break;
  
      case 1: // rx-count register
        this->rx_count = (this->rx_count & ~mask) | (data & mask);
+       if (written) *written = this->rx_count;
        break;
  
      case 2: // audio-config register
        this->config = (this->config & ~mask) | (data & mask);
        this->config_set_pin.drive (this->config);
+       if (written) *written = this->config;
        break;
  
      case 3: // status register
*************** basic_codec::reg_write (host_int_4 idx, 
*** 98,103 ****
--- 101,107 ----
  	{
  	  this->tx_sample_pin.drive (data.read_byte (0));
  	  this->tx_count --;
+ 	  if (written) *written = data.read_byte (0);
  	}
        break;
  
Index: sid/component/audio/components.h
===================================================================
RCS file: /cvs/src/src/sid/component/audio/components.h,v
retrieving revision 1.3
diff -c -p -r1.3 components.h
*** sid/component/audio/components.h	31 Jan 2003 14:55:45 -0000	1.3
--- sid/component/audio/components.h	17 Mar 2004 20:48:59 -0000
***************
*** 1,6 ****
  // components.h - description.  -*- C++ -*-
  
! // Copyright (C) 1999, 2000 Red Hat.
  // This file is part of SID and is licensed under the GPL.
  // See the file COPYING.SID for conditions for redistribution.
  
--- 1,6 ----
  // components.h - description.  -*- C++ -*-
  
! // Copyright (C) 1999, 2000, 2004 Red Hat.
  // This file is part of SID and is licensed under the GPL.
  // See the file COPYING.SID for conditions for redistribution.
  
*************** private:
*** 119,125 ****
    host_int_4 config;
  
  private:
!   bus::status reg_write (host_int_4 idx, big_int_4 mask, big_int_4 data);
    bus::status reg_read (host_int_4 idx, big_int_4 mask, big_int_4& data);
    void rx_sample_pin_handler (host_int_4);
    
--- 119,125 ----
    host_int_4 config;
  
  private:
!   bus::status reg_write (host_int_4 idx, big_int_4 mask, big_int_4 data, big_int_4 *written);
    bus::status reg_read (host_int_4 idx, big_int_4 mask, big_int_4& data);
    void rx_sample_pin_handler (host_int_4);
    
Index: sid/component/cache/cache.cxx
===================================================================
RCS file: /cvs/src/src/sid/component/cache/cache.cxx,v
retrieving revision 1.16
diff -c -p -r1.16 cache.cxx
*** sid/component/cache/cache.cxx	8 Jan 2003 02:51:57 -0000	1.16
--- sid/component/cache/cache.cxx	17 Mar 2004 20:48:59 -0000
***************
*** 1,6 ****
  // cache.cxx -- A universal memory cache. -*- C++ -*-
  
! // Copyright (C) 2001, 2002 Red Hat.
  // This file is part of SID and is licensed under the GPL.
  // See the file COPYING.SID for conditions for redistribution.
  
--- 1,6 ----
  // cache.cxx -- A universal memory cache. -*- C++ -*-
  
! // Copyright (C) 2001, 2002, 2004 Red Hat.
  // This file is part of SID and is licensed under the GPL.
  // See the file COPYING.SID for conditions for redistribution.
  
*************** cache_component::line_offset (const cach
*** 166,172 ****
  
  template <typename DataType>
  bus::status
! cache_component::write_any (host_int_4 addr, DataType data)
  {
    bool hit;
    bus::status st, read_status;
--- 166,172 ----
  
  template <typename DataType>
  bus::status
! cache_component::write_any (host_int_4 addr, DataType data, DataType *written)
  {
    bool hit;
    bus::status st, read_status;
*************** cache_component::write_any (host_int_4 a
*** 250,255 ****
--- 250,258 ----
  	    return st;
  	}
      }
+ 
+   if (written)
+     *written = data;
  
    st = bus::ok;
    if (hit)
Index: sid/component/cache/cache.h
===================================================================
RCS file: /cvs/src/src/sid/component/cache/cache.h,v
retrieving revision 1.9
diff -c -p -r1.9 cache.h
*** sid/component/cache/cache.h	8 Jan 2003 02:51:57 -0000	1.9
--- sid/component/cache/cache.h	17 Mar 2004 20:48:59 -0000
***************
*** 1,6 ****
  // cache.h -- A universal memory cache. -*- C++ -*-
  
! // Copyright (C) 2001, 2002 Red Hat.
  // This file is part of SID and is licensed under the GPL.
  // See the file COPYING.SID for conditions for redistribution.
  
--- 1,6 ----
  // cache.h -- A universal memory cache. -*- C++ -*-
  
! // Copyright (C) 2001, 2002, 2004 Red Hat.
  // This file is part of SID and is licensed under the GPL.
  // See the file COPYING.SID for conditions for redistribution.
  
*************** private:
*** 37,49 ****
    cache_component& cache;
  
    template <typename DataType>
!   bus::status write_any (host_int_4 addr, DataType data);
    
    template <typename DataType>
    bus::status read_any (host_int_4 addr, DataType& data);
  
  #define DEFN_METHOD(DataType) \
!   bus::status write(host_int_4 addr, DataType data) throw (); \
    bus::status read(host_int_4 addr, DataType& data) throw ();
    
    DEFN_METHOD (sid::big_int_1)
--- 37,49 ----
    cache_component& cache;
  
    template <typename DataType>
!   bus::status write_any (host_int_4 addr, DataType data, DataType *written);
    
    template <typename DataType>
    bus::status read_any (host_int_4 addr, DataType& data);
  
  #define DEFN_METHOD(DataType) \
!   bus::status write(host_int_4 addr, DataType data, DataType *written = 0) throw (); \
    bus::status read(host_int_4 addr, DataType& data) throw ();
    
    DEFN_METHOD (sid::big_int_1)
*************** public:
*** 111,117 ****
    ~cache_component () throw();
  
    template <typename DataType> bus::status 
!   write_any (host_int_4 addr, DataType data);
    
    template <typename DataType> bus::status
    read_any (host_int_4 addr, DataType& data);
--- 111,117 ----
    ~cache_component () throw();
  
    template <typename DataType> bus::status 
!   write_any (host_int_4 addr, DataType data, DataType *written);
    
    template <typename DataType> bus::status
    read_any (host_int_4 addr, DataType& data);
*************** private:
*** 205,213 ****
  
  template <typename DataType>
  bus::status
! cache_bus::write_any (host_int_4 addr, DataType data)
  {
!   return cache.write_any (addr, data);
  }
    
  template <typename DataType>
--- 205,213 ----
  
  template <typename DataType>
  bus::status
! cache_bus::write_any (host_int_4 addr, DataType data, DataType *written)
  {
!   return cache.write_any (addr, data, written);
  }
    
  template <typename DataType>
*************** cache_bus::read_any (host_int_4 addr, Da
*** 218,224 ****
  }
  
  #define DEFN_METHOD(DataType) \
!   inline bus::status cache_bus::write(host_int_4 addr, DataType data) throw () { return this->write_any(addr, data); } \
    inline bus::status cache_bus::read(host_int_4 addr, DataType& data) throw () { return this->read_any(addr, data); }
    
  DEFN_METHOD (sid::big_int_1)
--- 218,224 ----
  }
  
  #define DEFN_METHOD(DataType) \
!   inline bus::status cache_bus::write(host_int_4 addr, DataType data, DataType *written) throw () { return this->write_any(addr, data, written); } \
    inline bus::status cache_bus::read(host_int_4 addr, DataType& data) throw () { return this->read_any(addr, data); }
    
  DEFN_METHOD (sid::big_int_1)
Index: sid/component/cgen-cpu/cgen-cpu.h
===================================================================
RCS file: /cvs/src/src/sid/component/cgen-cpu/cgen-cpu.h,v
retrieving revision 1.9
diff -c -p -r1.9 cgen-cpu.h
*** sid/component/cgen-cpu/cgen-cpu.h	15 Jan 2003 20:04:57 -0000	1.9
--- sid/component/cgen-cpu/cgen-cpu.h	17 Mar 2004 20:48:59 -0000
***************
*** 1,6 ****
  // cgen-cpu.h  -*- C++ -*-
  
! // Copyright (C) 2000, 2001, 2002, 2003 Red Hat.
  // This file is part of SID and is licensed under the GPL.
  // See the file COPYING.SID for conditions for redistribution.
  
--- 1,6 ----
  // cgen-cpu.h  -*- C++ -*-
  
! // Copyright (C) 2000-2004 Red Hat.
  // This file is part of SID and is licensed under the GPL.
  // See the file COPYING.SID for conditions for redistribution.
  
*************** public:
*** 97,113 ****
      {
        return this->read_data_memory_1 (pc, addr);
      }
!   inline void
    SETMEMBI(PCADDR pc, ADDR addr, BI value) const
      {
        return this->write_insn_memory_1 (pc, addr, value);
      }
!   inline void
    SETMEMQI(PCADDR pc, ADDR addr, QI value) const
      {
        return this->write_data_memory_1 (pc, addr, value);
      }
!   inline void
    SETMEMUQI(PCADDR pc, ADDR addr, UQI value) const
      {
        return this->write_data_memory_1 (pc, addr, value);
--- 97,113 ----
      {
        return this->read_data_memory_1 (pc, addr);
      }
!   inline BI
    SETMEMBI(PCADDR pc, ADDR addr, BI value) const
      {
        return this->write_insn_memory_1 (pc, addr, value);
      }
!   inline QI
    SETMEMQI(PCADDR pc, ADDR addr, QI value) const
      {
        return this->write_data_memory_1 (pc, addr, value);
      }
!   inline UQI
    SETMEMUQI(PCADDR pc, ADDR addr, UQI value) const
      {
        return this->write_data_memory_1 (pc, addr, value);
*************** public:
*** 122,133 ****
      {
        return this->read_data_memory_2 (pc, addr);
      }
!   inline void
    SETMEMHI(PCADDR pc, ADDR addr, HI value) const
      {
        return this->write_data_memory_2 (pc, addr, value);
      }
!   inline void
    SETMEMUHI(PCADDR pc, ADDR addr, UHI value) const
      {
        return this->write_data_memory_2 (pc, addr, value);
--- 122,133 ----
      {
        return this->read_data_memory_2 (pc, addr);
      }
!   inline HI
    SETMEMHI(PCADDR pc, ADDR addr, HI value) const
      {
        return this->write_data_memory_2 (pc, addr, value);
      }
!   inline UHI
    SETMEMUHI(PCADDR pc, ADDR addr, UHI value) const
      {
        return this->write_data_memory_2 (pc, addr, value);
*************** public:
*** 137,143 ****
      {
        return this->read_data_memory_4 (pc, addr);
      }
!   inline void
    SETMEMSI(PCADDR pc, ADDR addr, SI value) const
      {
        return this->write_data_memory_4 (pc, addr, value);
--- 137,143 ----
      {
        return this->read_data_memory_4 (pc, addr);
      }
!   inline SI
    SETMEMSI(PCADDR pc, ADDR addr, SI value) const
      {
        return this->write_data_memory_4 (pc, addr, value);
*************** public:
*** 147,153 ****
      {
        return this->read_data_memory_4 (pc, addr);
      }
!   inline void
    SETMEMUSI(PCADDR pc, ADDR addr, USI value) const
      {
        return this->write_data_memory_4 (pc, addr, value);
--- 147,153 ----
      {
        return this->read_data_memory_4 (pc, addr);
      }
!   inline USI
    SETMEMUSI(PCADDR pc, ADDR addr, USI value) const
      {
        return this->write_data_memory_4 (pc, addr, value);
*************** public:
*** 157,168 ****
      {
        return this->read_data_memory_8 (pc, addr);
      }
!   inline void
    SETMEMDI(PCADDR pc, ADDR addr, DI value) const
      {
        return this->write_data_memory_8 (pc, addr, value);
      }
!   inline void
    SETMEMUDI(PCADDR pc, ADDR addr, UDI value) const
      {
        return this->write_data_memory_8 (pc, addr, value);
--- 157,168 ----
      {
        return this->read_data_memory_8 (pc, addr);
      }
!   inline DI
    SETMEMDI(PCADDR pc, ADDR addr, DI value) const
      {
        return this->write_data_memory_8 (pc, addr, value);
      }
!   inline UDI
    SETMEMUDI(PCADDR pc, ADDR addr, UDI value) const
      {
        return this->write_data_memory_8 (pc, addr, value);
*************** public:
*** 174,180 ****
      {
        return reinterpret_cast<SF>(this->read_insn_memory_4 (pc, addr));
      }
!   inline void
    SETMEMSF(PCADDR pc, ADDR addr, SF value) const
      {
        return this->write_insn_memory_4 (pc, addr, reinterpret_cast<USI>(value));
--- 174,180 ----
      {
        return reinterpret_cast<SF>(this->read_insn_memory_4 (pc, addr));
      }
!   inline SF
    SETMEMSF(PCADDR pc, ADDR addr, SF value) const
      {
        return this->write_insn_memory_4 (pc, addr, reinterpret_cast<USI>(value));
*************** public:
*** 185,191 ****
      {
        return reinterpret_cast<DF>(this->read_insn_memory_8 (pc, addr));
      }
!   inline void
    SETMEMDF(PCADDR pc, ADDR addr, DF value) const
      {
        return this->write_insn_memory_8 (pc, addr, reinterpret_cast<UDI>(value));
--- 185,191 ----
      {
        return reinterpret_cast<DF>(this->read_insn_memory_8 (pc, addr));
      }
!   inline DF
    SETMEMDF(PCADDR pc, ADDR addr, DF value) const
      {
        return this->write_insn_memory_8 (pc, addr, reinterpret_cast<UDI>(value));
*************** public:
*** 198,204 ****
      {
        return this->read_insn_memory_1 (pc, addr);
      }
!   inline void
    SETIMEMQI(PCADDR pc, ADDR addr, QI value) const
      {
        return this->write_insn_memory_1 (pc, addr, value);
--- 198,204 ----
      {
        return this->read_insn_memory_1 (pc, addr);
      }
!   inline QI
    SETIMEMQI(PCADDR pc, ADDR addr, QI value) const
      {
        return this->write_insn_memory_1 (pc, addr, value);
*************** public:
*** 208,214 ****
      {
        return this->read_insn_memory_1 (pc, addr);
      }
!   inline void
    SETIMEMUQI(PCADDR pc, ADDR addr, UQI value) const
      {
        return this->write_insn_memory_1 (pc, addr, value);
--- 208,214 ----
      {
        return this->read_insn_memory_1 (pc, addr);
      }
!   inline UQI
    SETIMEMUQI(PCADDR pc, ADDR addr, UQI value) const
      {
        return this->write_insn_memory_1 (pc, addr, value);
*************** public:
*** 218,224 ****
      {
        return this->read_insn_memory_2 (pc, addr);
      }
!   inline void
    SETIMEMHI(PCADDR pc, ADDR addr, HI value) const
      {
        return this->write_insn_memory_2 (pc, addr, value);
--- 218,224 ----
      {
        return this->read_insn_memory_2 (pc, addr);
      }
!   inline HI
    SETIMEMHI(PCADDR pc, ADDR addr, HI value) const
      {
        return this->write_insn_memory_2 (pc, addr, value);
*************** public:
*** 228,234 ****
      {
        return this->read_insn_memory_2 (pc, addr);
      }
!   inline void
    SETIMEMUHI(PCADDR pc, ADDR addr, UHI value) const
      {
        return this->write_insn_memory_2 (pc, addr, value);
--- 228,234 ----
      {
        return this->read_insn_memory_2 (pc, addr);
      }
!   inline UHI
    SETIMEMUHI(PCADDR pc, ADDR addr, UHI value) const
      {
        return this->write_insn_memory_2 (pc, addr, value);
*************** public:
*** 238,244 ****
      {
        return this->read_insn_memory_4 (pc, addr);
      }
!   inline void
    SETIMEMSI(PCADDR pc, ADDR addr, SI value) const
      {
        return this->write_insn_memory_4 (pc, addr, value);
--- 238,244 ----
      {
        return this->read_insn_memory_4 (pc, addr);
      }
!   inline SI
    SETIMEMSI(PCADDR pc, ADDR addr, SI value) const
      {
        return this->write_insn_memory_4 (pc, addr, value);
*************** public:
*** 248,254 ****
      {
        return this->read_insn_memory_4 (pc, addr);
      }
!   inline void
    SETIMEMUSI(PCADDR pc, ADDR addr, USI value) const
      {
        return this->write_insn_memory_4 (pc, addr, value);
--- 248,254 ----
      {
        return this->read_insn_memory_4 (pc, addr);
      }
!   inline USI
    SETIMEMUSI(PCADDR pc, ADDR addr, USI value) const
      {
        return this->write_insn_memory_4 (pc, addr, value);
*************** public:
*** 258,264 ****
      {
        return this->read_insn_memory_8 (pc, addr);
      }
!   inline void
    SETIMEMDI(PCADDR pc, ADDR addr, DI value) const
      {
        return this->write_insn_memory_8 (pc, addr, value);
--- 258,264 ----
      {
        return this->read_insn_memory_8 (pc, addr);
      }
!   inline DI
    SETIMEMDI(PCADDR pc, ADDR addr, DI value) const
      {
        return this->write_insn_memory_8 (pc, addr, value);
*************** public:
*** 268,274 ****
      {
        return this->read_insn_memory_8 (pc, addr);
      }
!   inline void
    SETIMEMUDI(PCADDR pc, ADDR addr, UDI value) const
      {
        return this->write_insn_memory_8 (pc, addr, value);
--- 268,274 ----
      {
        return this->read_insn_memory_8 (pc, addr);
      }
!   inline UDI
    SETIMEMUDI(PCADDR pc, ADDR addr, UDI value) const
      {
        return this->write_insn_memory_8 (pc, addr, value);
Index: sid/component/glue/glue.cxx
===================================================================
RCS file: /cvs/src/src/sid/component/glue/glue.cxx,v
retrieving revision 1.9
diff -c -p -r1.9 glue.cxx
*** sid/component/glue/glue.cxx	22 Nov 2002 17:15:42 -0000	1.9
--- sid/component/glue/glue.cxx	17 Mar 2004 20:48:59 -0000
***************
*** 1,6 ****
  // glue.cxx - miscellaneous glue components.  -*- C++ -*-
  
! // Copyright (C) 1999-2001 Red Hat.
  // This file is part of SID and is licensed under the GPL.
  // See the file COPYING.SID for conditions for redistribution.
  
--- 1,6 ----
  // glue.cxx - miscellaneous glue components.  -*- C++ -*-
  
! // Copyright (C) 1999-2001, 2004 Red Hat.
  // This file is part of SID and is licensed under the GPL.
  // See the file COPYING.SID for conditions for redistribution.
  
*************** class probing_bus: public bus
*** 325,331 ****
    bool verbose_p;
  
    template <typename DataType>
!   bus::status writeAny(host_int_4 addr, DataType data, host_int_4 code) throw ();
    template <typename DataType>
    bus::status readAny(host_int_4 addr, DataType& data, host_int_4 code) throw ();
  
--- 325,331 ----
    bool verbose_p;
  
    template <typename DataType>
!   bus::status writeAny(host_int_4 addr, DataType data, DataType *written, host_int_4 code) throw ();
    template <typename DataType>
    bus::status readAny(host_int_4 addr, DataType& data, host_int_4 code) throw ();
  
*************** class probing_bus: public bus
*** 333,341 ****
    void traceAccess(host_int_4 addr, DataType data, host_int_4 code, bus::status s) throw ();
  
  #define PROBE(DataType,Code) \
!   status write(host_int_4 addr, DataType data) throw () \
      { \
!       return this->writeAny(addr, data, Code); \
      } \
    status read(host_int_4 addr, DataType& data) throw () \
      { \
--- 333,341 ----
    void traceAccess(host_int_4 addr, DataType data, host_int_4 code, bus::status s) throw ();
  
  #define PROBE(DataType,Code) \
!   status write(host_int_4 addr, DataType data, DataType *written) throw () \
      { \
!       return this->writeAny(addr, data, written, Code); \
      } \
    status read(host_int_4 addr, DataType& data) throw () \
      { \
*************** probing_bus::traceAccess(host_int_4 addr
*** 452,464 ****
  
  template <typename DataType>
  bus::status
! probing_bus::writeAny(host_int_4 addr, DataType data, host_int_4 code) throw ()
  {
    assert (this->prober);
  
    bus::status s = bus::unmapped;
    if (this->prober->downstream != 0)
!     s = this->prober->downstream->write (addr, data);
  
    if (this->prober->sample_interval > 0)
      {
--- 452,464 ----
  
  template <typename DataType>
  bus::status
! probing_bus::writeAny(host_int_4 addr, DataType data, DataType *written, host_int_4 code) throw ()
  {
    assert (this->prober);
  
    bus::status s = bus::unmapped;
    if (this->prober->downstream != 0)
!     s = this->prober->downstream->write (addr, data, written);
  
    if (this->prober->sample_interval > 0)
      {
Index: sid/component/ide/compIDE.cxx
===================================================================
RCS file: /cvs/src/src/sid/component/ide/compIDE.cxx,v
retrieving revision 1.3
diff -c -p -r1.3 compIDE.cxx
*** sid/component/ide/compIDE.cxx	4 Mar 2002 23:54:55 -0000	1.3
--- sid/component/ide/compIDE.cxx	17 Mar 2004 20:49:00 -0000
***************
*** 1,6 ****
  // compIDE.cxx - An IDE disk drive component.  -*- C++ -*-
  
! // Copyright (C) 1999, 2000 Red Hat.
  // This file is part of SID and is licensed under the GPL.
  // See the file COPYING.SID for conditions for redistribution.
  
--- 1,6 ----
  // compIDE.cxx - An IDE disk drive component.  -*- C++ -*-
  
! // Copyright (C) 1999, 2000, 2004 Red Hat.
  // This file is part of SID and is licensed under the GPL.
  // See the file COPYING.SID for conditions for redistribution.
  
*************** protected:
*** 387,397 ****
    enum controller_state { idle, reading, reading_nowb, writing, writing_nowb } state;
    	 
    // register access callbacks
!   void device_control_srst(little_int_1 value, little_int_1 mask);
!   void data_port_set(little_int_1 value, little_int_1 mask);
    little_int_1 data_port_get();
    little_int_1 status_get();
!   void command_set(little_int_1 value, little_int_1 mask);
  
    // work functions
    void interrupt(host_int_4 v)
--- 387,397 ----
    enum controller_state { idle, reading, reading_nowb, writing, writing_nowb } state;
    	 
    // register access callbacks
!   little_int_1 device_control_srst(little_int_1 value, little_int_1 mask);
!   little_int_1 data_port_set(little_int_1 value, little_int_1 mask);
    little_int_1 data_port_get();
    little_int_1 status_get();
!   little_int_1 command_set(little_int_1 value, little_int_1 mask);
  
    // work functions
    void interrupt(host_int_4 v)
*************** ide_controller::reset()
*** 558,571 ****
  }
  
  
! void 
  ide_controller::device_control_srst(little_int_1 value, little_int_1 mask)
  {
    if (value & mask)
      reset();
  }
  
! void
  ide_controller::data_port_set(little_int_1 value, little_int_1 mask)
  {
    switch (this->state)
--- 558,572 ----
  }
  
  
! little_int_1 
  ide_controller::device_control_srst(little_int_1 value, little_int_1 mask)
  {
    if (value & mask)
      reset();
+   return value & mask;
  }
  
! little_int_1
  ide_controller::data_port_set(little_int_1 value, little_int_1 mask)
  {
    switch (this->state)
*************** ide_controller::data_port_set(little_int
*** 616,621 ****
--- 617,624 ----
        // Undefined behavior
        cerr << "Warning: inappropriate time to write to IDE data port." << endl;
      }
+ 
+   return value & mask;
  }
  
  little_int_1
*************** ide_controller::status_get()
*** 669,675 ****
  }
  
  
! void
  ide_controller::command_set(little_int_1 value, little_int_1 mask)
  {
    if ((this->state != idle)
--- 672,678 ----
  }
  
  
! little_int_1
  ide_controller::command_set(little_int_1 value, little_int_1 mask)
  {
    if ((this->state != idle)
*************** ide_controller::command_set(little_int_1
*** 679,685 ****
        cerr << "Inappropriate time to issue IDE command." << endl;
        this->altstatus_reg_error = 1;
        this->interrupt (1);
!       return;
      }
  
    // XXX: Clear meaningless powerup state
--- 682,688 ----
        cerr << "Inappropriate time to issue IDE command." << endl;
        this->altstatus_reg_error = 1;
        this->interrupt (1);
!       return value & mask;
      }
  
    // XXX: Clear meaningless powerup state
*************** ide_controller::command_set(little_int_1
*** 787,792 ****
--- 790,797 ----
  	this->interrupt(1); // command aborted
        }
      }
+ 
+   return value & mask;
  }
  
  
Index: sid/component/lcd/HD44780U.cxx
===================================================================
RCS file: /cvs/src/src/sid/component/lcd/HD44780U.cxx,v
retrieving revision 1.2
diff -c -p -r1.2 HD44780U.cxx
*** sid/component/lcd/HD44780U.cxx	3 Aug 2001 06:02:44 -0000	1.2
--- sid/component/lcd/HD44780U.cxx	17 Mar 2004 20:49:00 -0000
***************
*** 1,6 ****
  // HD44780U.cxx - description.  -*- C++ -*-
  
! // Copyright (C) 1999, 2000 Red Hat.
  // This file is part of SID and is licensed under the GPL.
  // See the file COPYING.SID for conditions for redistribution.
  
--- 1,6 ----
  // HD44780U.cxx - description.  -*- C++ -*-
  
! // Copyright (C) 1999, 2000, 2004 Red Hat.
  // This file is part of SID and is licensed under the GPL.
  // See the file COPYING.SID for conditions for redistribution.
  
*************** HD44780U :: busRead( host_int_4 laddr, h
*** 146,152 ****
  }
  
  sid::bus::status
! HD44780U :: busWrite( host_int_4 laddr, host_int_1 data ) {
    if( laddr == 0 ) {
      // write the IR (busy is not used, so don't need to worry about it)
      ir = data;
--- 146,152 ----
  }
  
  sid::bus::status
! HD44780U :: busWrite( host_int_4 laddr, host_int_1 data, host_int_1 *written ) {
    if( laddr == 0 ) {
      // write the IR (busy is not used, so don't need to worry about it)
      ir = data;
*************** HD44780U :: busWrite( host_int_4 laddr, 
*** 214,219 ****
--- 214,222 ----
  
    if( verbose )
      cerr << "HD44780U::write - schedule " << current_schedule << endl;
+ 
+   if (written)
+     *written = data;
  
    return sid::bus::ok;
  }
Index: sid/component/lcd/HD44780U.h
===================================================================
RCS file: /cvs/src/src/sid/component/lcd/HD44780U.h,v
retrieving revision 1.2
diff -c -p -r1.2 HD44780U.h
*** sid/component/lcd/HD44780U.h	3 Aug 2001 06:02:44 -0000	1.2
--- sid/component/lcd/HD44780U.h	17 Mar 2004 20:49:00 -0000
***************
*** 1,6 ****
  // HD44780U.h - description.  -*- C++ -*-
  
! // Copyright (C) 1999, 2000 Red Hat.
  // This file is part of SID and is licensed under the GPL.
  // See the file COPYING.SID for conditions for redistribution.
  
--- 1,6 ----
  // HD44780U.h - description.  -*- C++ -*-
  
! // Copyright (C) 1999, 2000, 2004 Red Hat.
  // This file is part of SID and is licensed under the GPL.
  // See the file COPYING.SID for conditions for redistribution.
  
*************** private:
*** 87,93 ****
    callback_byte_bus<HD44780U> busif;
  
    sid::bus::status busRead( host_int_4 laddr, host_int_1& data );
!   sid::bus::status busWrite( host_int_4 laddr, host_int_1 data );
  
    void execute( unsigned char );
  
--- 87,93 ----
    callback_byte_bus<HD44780U> busif;
  
    sid::bus::status busRead( host_int_4 laddr, host_int_1& data );
!   sid::bus::status busWrite( host_int_4 laddr, host_int_1 data, host_int_1 *written );
  
    void execute( unsigned char );
  
Index: sid/component/lcd/T6963C.cxx
===================================================================
RCS file: /cvs/src/src/sid/component/lcd/T6963C.cxx,v
retrieving revision 1.2
diff -c -p -r1.2 T6963C.cxx
*** sid/component/lcd/T6963C.cxx	3 Aug 2001 06:02:44 -0000	1.2
--- sid/component/lcd/T6963C.cxx	17 Mar 2004 20:49:00 -0000
***************
*** 1,6 ****
  // T6963.cxx - description.  -*- C++ -*-
  
! // Copyright (C) 1999, 2000 Red Hat.
  // This file is part of SID and is licensed under the GPL.
  // See the file COPYING.SID for conditions for redistribution.
  
--- 1,6 ----
  // T6963.cxx - description.  -*- C++ -*-
  
! // Copyright (C) 1999, 2000, 2004 Red Hat.
  // This file is part of SID and is licensed under the GPL.
  // See the file COPYING.SID for conditions for redistribution.
  
*************** T6963C :: busRead( host_int_4 laddr, hos
*** 172,182 ****
  }
  
  sid::bus::status
! T6963C :: busWrite( host_int_4 laddr, host_int_1 data ) {
    if( laddr == 0 ) {
      if( status & STA3 ) {	// auto write mode
        if( !ex_ram ) {		// no external ram?
  	status &= ~(STA3 | STA1);
  	return sid::bus::ok;	// its the ex-ram, not the lcd, thats unmapped
        }
  
--- 172,183 ----
  }
  
  sid::bus::status
! T6963C :: busWrite( host_int_4 laddr, host_int_1 data, host_int_1 *written ) {
    if( laddr == 0 ) {
      if( status & STA3 ) {	// auto write mode
        if( !ex_ram ) {		// no external ram?
  	status &= ~(STA3 | STA1);
+ 	if (written) *written = data;
  	return sid::bus::ok;	// its the ex-ram, not the lcd, thats unmapped
        }
  
*************** T6963C :: busWrite( host_int_4 laddr, ho
*** 235,240 ****
--- 236,243 ----
  
    // check for triggerpoints
    trigger_mgr.check_and_dispatch();
+ 
+   if (written) *written = data;
  
    return sid::bus::ok;
  }
Index: sid/component/lcd/T6963C.h
===================================================================
RCS file: /cvs/src/src/sid/component/lcd/T6963C.h,v
retrieving revision 1.2
diff -c -p -r1.2 T6963C.h
*** sid/component/lcd/T6963C.h	3 Aug 2001 06:02:44 -0000	1.2
--- sid/component/lcd/T6963C.h	17 Mar 2004 20:49:00 -0000
***************
*** 1,6 ****
  // T6963C.h - description.  -*- C++ -*-
  
! // Copyright (C) 1999, 2000 Red Hat.
  // This file is part of SID and is licensed under the GPL.
  // See the file COPYING.SID for conditions for redistribution.
  
--- 1,6 ----
  // T6963C.h - description.  -*- C++ -*-
  
! // Copyright (C) 1999, 2000, 2004 Red Hat.
  // This file is part of SID and is licensed under the GPL.
  // See the file COPYING.SID for conditions for redistribution.
  
*************** private:
*** 103,109 ****
    * Logical Address 1: Command/Status register
    */
    sid::bus::status busRead( host_int_4 laddr, host_int_1& data );
!   sid::bus::status busWrite( host_int_4 laddr, host_int_1 data );
  
    host_int_1 rom[ROM_SIZE][8];
  
--- 103,109 ----
    * Logical Address 1: Command/Status register
    */
    sid::bus::status busRead( host_int_4 laddr, host_int_1& data );
!   sid::bus::status busWrite( host_int_4 laddr, host_int_1 data, host_int_1 *written );
  
    host_int_1 rom[ROM_SIZE][8];
  
Index: sid/component/loader/compLoader.cxx
===================================================================
RCS file: /cvs/src/src/sid/component/loader/compLoader.cxx,v
retrieving revision 1.7
diff -c -p -r1.7 compLoader.cxx
*** sid/component/loader/compLoader.cxx	12 Feb 2004 20:30:08 -0000	1.7
--- sid/component/loader/compLoader.cxx	17 Mar 2004 20:49:00 -0000
*************** class loader_probe_bus: public sidutil::
*** 79,90 ****
      // Some macros to make manufacturing of the cartesian-product
      // calls simpler.
  #define SID_GB_WRITE(dtype) \
!       sid::bus::status write(sid::host_int_4 addr, dtype data) throw ()\
  	  { if (LIKELY(*target)) \
                { \
                  if (write_to_code_address_pin && textSectionAddress (addr, section_table)) \
                    write_to_code_address_pin->drive (addr); \
!                 return (*target)->write(addr, data); \
                } \
              else return sid::bus::unpermitted; \
            }
--- 79,90 ----
      // Some macros to make manufacturing of the cartesian-product
      // calls simpler.
  #define SID_GB_WRITE(dtype) \
!       sid::bus::status write(sid::host_int_4 addr, dtype data, dtype *written) throw ()\
  	  { if (LIKELY(*target)) \
                { \
                  if (write_to_code_address_pin && textSectionAddress (addr, section_table)) \
                    write_to_code_address_pin->drive (addr); \
!                 return (*target)->write(addr, data, written); \
                } \
              else return sid::bus::unpermitted; \
            }
Index: sid/component/mapper/compMapper.cxx
===================================================================
RCS file: /cvs/src/src/sid/component/mapper/compMapper.cxx,v
retrieving revision 1.13
diff -c -p -r1.13 compMapper.cxx
*** sid/component/mapper/compMapper.cxx	14 Feb 2003 19:06:21 -0000	1.13
--- sid/component/mapper/compMapper.cxx	17 Mar 2004 20:49:00 -0000
***************
*** 1,6 ****
  // compMapper.cxx - a bus mapper component.  -*- C++ -*-
  
! // Copyright (C) 1999-2003 Red Hat.
  // This file is part of SID and is licensed under the GPL.
  // See the file COPYING.SID for conditions for redistribution.
  
--- 1,6 ----
  // compMapper.cxx - a bus mapper component.  -*- C++ -*-
  
! // Copyright (C) 1999-2004 Red Hat.
  // This file is part of SID and is licensed under the GPL.
  // See the file COPYING.SID for conditions for redistribution.
  
*************** public:
*** 180,186 ****
    template <class DataMaster, class DataSlave>
    inline bus::status
    write_strideoffset_any (host_int_4 address, const mapping_record* r,
! 			  DataMaster data, DataSlave) throw ()
      {
        const host_int_4 master_offset = address & r->stride_mask;
        const host_int_4 master_size = sizeof (typename DataMaster::value_type);
--- 180,186 ----
    template <class DataMaster, class DataSlave>
    inline bus::status
    write_strideoffset_any (host_int_4 address, const mapping_record* r,
! 			  DataMaster data, DataMaster *written, DataSlave) throw ()
      {
        const host_int_4 master_offset = address & r->stride_mask;
        const host_int_4 master_size = sizeof (typename DataMaster::value_type);
*************** public:
*** 202,209 ****
  	ds.write_byte (i, data.read_byte (i + slave_offset - master_offset));
  
        host_int_4 mapped_address = (address - (r->low - r->mapped_base)) >> (r->stride_shift - r->width_shift);
!       
!       bus::status st = r->accessor->write (mapped_address, ds);
        st.latency += target->latency;
        return st;
      }
--- 202,215 ----
  	ds.write_byte (i, data.read_byte (i + slave_offset - master_offset));
  
        host_int_4 mapped_address = (address - (r->low - r->mapped_base)) >> (r->stride_shift - r->width_shift);
! 
!       DataSlave ws;
!       bus::status st = r->accessor->write (mapped_address, ds, &ws);
! 
!       if (written)
! 	for (unsigned i=0; i<slave_size; i++)
! 	  written->write_byte (i + slave_offset - master_offset, ws.read_byte(i));
! 
        st.latency += target->latency;
        return st;
      }
*************** public:
*** 246,252 ****
    // Generic write() & read()
    template <class Data>
    inline bus::status
!   write_any (host_int_4 address, Data data) throw ();
    template <class Data>
    inline bus::status
    read_any (host_int_4 address, Data& data) throw ();
--- 252,258 ----
    // Generic write() & read()
    template <class Data>
    inline bus::status
!   write_any (host_int_4 address, Data data, Data *written) throw ();
    template <class Data>
    inline bus::status
    read_any (host_int_4 address, Data& data) throw ();
*************** public:
*** 254,260 ****
  
    // some macros to make manufacturing of the cartesian-product calls simpler
  #define SID_GB_WRITE(Type) \
!   bus::status write (host_int_4 address, Type data) throw () { return write_any (address,data); }
  #define SID_GB_READ(Type) \
    bus::status read (host_int_4 address, Type& data) throw () { return read_any (address,data); }
    
--- 260,266 ----
  
    // some macros to make manufacturing of the cartesian-product calls simpler
  #define SID_GB_WRITE(Type) \
!   bus::status write (host_int_4 address, Type data, Type *written) throw () { return write_any (address,data,written); }
  #define SID_GB_READ(Type) \
    bus::status read (host_int_4 address, Type& data) throw () { return read_any (address,data); }
    
*************** generic_mapper::connected_bus (const str
*** 495,501 ****
  
  template <class Data>
  inline bus::status
! generic_mapper_bus::write_any (host_int_4 address, Data data) throw ()
    {
      const mapping_record* r = this->locate (address);
      if (LIKELY (r))
--- 501,507 ----
  
  template <class Data>
  inline bus::status
! generic_mapper_bus::write_any (host_int_4 address, Data data, Data *written) throw ()
    {
      const mapping_record* r = this->locate (address);
      if (LIKELY (r))
*************** generic_mapper_bus::write_any (host_int_
*** 504,510 ****
  	if (LIKELY(! r->use_strideoffset_p))
  	  {
  	    host_int_4 mapped_address = address - (r->low - r->mapped_base);
! 	    bus::status st = r->accessor->write (mapped_address, data);
  	    st.latency += target->latency;
  	    return st;
  	  }
--- 510,516 ----
  	if (LIKELY(! r->use_strideoffset_p))
  	  {
  	    host_int_4 mapped_address = address - (r->low - r->mapped_base);
! 	    bus::status st = r->accessor->write (mapped_address, data, written);
  	    st.latency += target->latency;
  	    return st;
  	  }
*************** generic_mapper_bus::write_any (host_int_
*** 513,534 ****
  	if (r->width == 1)
  	  {
  	    typename Data::size_1_type s1data;
! 	    return write_strideoffset_any (address, r, data, s1data);
  	  }
  	else if (r->width == 4)
  	  {
  	    typename Data::size_4_type s4data;
! 	    return write_strideoffset_any (address, r, data, s4data);
  	  }
  	else if (r->width == 2)
  	  {
  	    typename Data::size_2_type s2data;
! 	    return write_strideoffset_any (address, r, data, s2data);
  	  }
  	else if (r->width == 8)
  	  {
  	    typename Data::size_8_type s8data;
! 	    return write_strideoffset_any (address, r, data, s8data);
  	  }
  	else
  	  assert (0);
--- 519,540 ----
  	if (r->width == 1)
  	  {
  	    typename Data::size_1_type s1data;
! 	    return write_strideoffset_any (address, r, data, written, s1data);
  	  }
  	else if (r->width == 4)
  	  {
  	    typename Data::size_4_type s4data;
! 	    return write_strideoffset_any (address, r, data, written, s4data);
  	  }
  	else if (r->width == 2)
  	  {
  	    typename Data::size_2_type s2data;
! 	    return write_strideoffset_any (address, r, data, written, s2data);
  	  }
  	else if (r->width == 8)
  	  {
  	    typename Data::size_8_type s8data;
! 	    return write_strideoffset_any (address, r, data, written, s8data);
  	  }
  	else
  	  assert (0);
Index: sid/component/mapper/testsuite/busif.cxx
===================================================================
RCS file: /cvs/src/src/sid/component/mapper/testsuite/busif.cxx,v
retrieving revision 1.2
diff -c -p -r1.2 busif.cxx
*** sid/component/mapper/testsuite/busif.cxx	3 Aug 2001 06:02:46 -0000	1.2
--- sid/component/mapper/testsuite/busif.cxx	17 Mar 2004 20:49:00 -0000
***************
*** 1,6 ****
  // busif.cxx - a component for testing word_bus<>.  -*- C++ -*-
  
! // Copyright (C) 1999, 2000 Red Hat.
  // This file is part of SID and is licensed under the GPL.
  // See the file COPYING.SID for conditions for redistribution.
  
--- 1,6 ----
  // busif.cxx - a component for testing word_bus<>.  -*- C++ -*-
  
! // Copyright (C) 1999, 2000, 2004 Red Hat.
  // This file is part of SID and is licensed under the GPL.
  // See the file COPYING.SID for conditions for redistribution.
  
*************** private:
*** 42,48 ****
      
      sid::bus::status word_write( host_int_4 addr, 
  				 DataType mask,
! 				 DataType data ) {
        host_int_4 a = addr * sizeof( internal_type );
        internal_type m = mask;
        internal_type d = data;
--- 42,49 ----
      
      sid::bus::status word_write( host_int_4 addr, 
  				 DataType mask,
! 				 DataType data,
! 				 DataType *written ) {
        host_int_4 a = addr * sizeof( internal_type );
        internal_type m = mask;
        internal_type d = data;
*************** private:
*** 60,65 ****
--- 61,68 ----
  	  }
  	}
        }
+ 
+       if (written) *written = data & mask;
  
        return sid::bus::ok;
      }
Index: sid/component/memory/am29.cxx
===================================================================
RCS file: /cvs/src/src/sid/component/memory/am29.cxx,v
retrieving revision 1.2
diff -c -p -r1.2 am29.cxx
*** sid/component/memory/am29.cxx	22 Jun 2001 07:22:52 -0000	1.2
--- sid/component/memory/am29.cxx	17 Mar 2004 20:49:00 -0000
***************
*** 1,6 ****
  // am29.cxx - Implementation of AMD's 29xxx flash memory.  -*- C++ -*-
  
! // Copyright (C) 1999, 2000 Red Hat.
  // This file is part of SID and is licensed under the GPL.
  // See the file COPYING.SID for conditions for redistribution.
  
--- 1,6 ----
  // am29.cxx - Implementation of AMD's 29xxx flash memory.  -*- C++ -*-
  
! // Copyright (C) 1999, 2000, 2004 Red Hat.
  // This file is part of SID and is licensed under the GPL.
  // See the file COPYING.SID for conditions for redistribution.
  
*************** am29_flash_memory::am29_bus::read(host_i
*** 180,186 ****
  
  bus::status
  am29_flash_memory::am29_bus::write(host_int_4 address, 
! 				   little_int_1 le_data) throw()
  {
    host_int_1 data = le_data;
        
--- 180,186 ----
  
  bus::status
  am29_flash_memory::am29_bus::write(host_int_4 address, 
! 				   little_int_1 le_data, little_int_1 *le_written) throw()
  {
    host_int_1 data = le_data;
        
*************** am29_flash_memory::am29_bus::write(host_
*** 190,201 ****
--- 190,203 ----
        if (address == UNLOCK && data == UNLOCK1_CMD)
  	{
  	  target->mode = STATE_UNLOCK1;
+ 	  if (le_written) *le_written = data;
  	  return bus::ok;
  	}
        return bus::unpermitted;
  
      case STATE_AUTOSELECT:
        // Don't care about the address bits for the reset command.
+       if (le_written) *le_written = data;
        if (data == 0xF0)
  	{
  	  target->mode = STATE_READ;
*************** am29_flash_memory::am29_bus::write(host_
*** 211,222 ****
--- 213,226 ----
  	target->mode = STATE_BYPASS_RESET;
        else
  	target->mode = STATE_READ;
+       if (le_written) *le_written = data;
        return bus::ok;
  
      case STATE_BYPASS_RESET:
        // Go back to read mode unconditionally -- this is the
        // expected behaviour even if the magic codes are wrong.
        target->mode = STATE_READ;
+       if (le_written) *le_written = data;
        return bus::ok;
  
      case STATE_ERASE0:
*************** am29_flash_memory::am29_bus::write(host_
*** 224,229 ****
--- 228,234 ----
  	target->mode = STATE_ERASE1;
        else
  	target->mode = STATE_READ;
+       if (le_written) *le_written = data;
        return bus::ok;
  
      case STATE_ERASE1:
*************** am29_flash_memory::am29_bus::write(host_
*** 231,236 ****
--- 236,242 ----
  	target->mode = STATE_ERASE2;
        else
  	target->mode = STATE_READ;
+       if (le_written) *le_written = data;
        return bus::ok;
  
      case STATE_ERASE2:
*************** am29_flash_memory::am29_bus::write(host_
*** 243,248 ****
--- 249,255 ----
  	  target->erase((address >> 16));
  	}
        target->mode = STATE_READ;
+       if (le_written) *le_written = data;
        return bus::ok;
  	  
      case STATE_UNLOCK1:
*************** am29_flash_memory::am29_bus::write(host_
*** 250,255 ****
--- 257,263 ----
  	target->mode = STATE_UNLOCK2;
        else
  	target->mode = STATE_READ;
+       if (le_written) *le_written = data;
        return bus::ok;
  	  
      case STATE_UNLOCK2:
*************** am29_flash_memory::am29_bus::write(host_
*** 263,268 ****
--- 271,277 ----
  	target->mode = STATE_BYPASS;
        else
  	target->mode = STATE_READ;
+       if (le_written) *le_written = data;
        return bus::ok;
      }
  
*************** am29_flash_memory::am29_bus::write(host_
*** 286,291 ****
--- 295,301 ----
  		  
        target->buffer[address] = data;
        target->mode = STATE_READ;
+       if (le_written) *le_written = data;
        return bus::ok;
      }
   // XXX: error
*************** am29_flash_memory::am29_bus::write(host_
*** 294,302 ****
  
  bus::status
  am29_flash_memory::am29_bus::write(host_int_4 address,
! 				   big_int_1 data) throw ()
  {
!   return write(address, little_int_1(data));
  }
  
  // static const description table for flash family
--- 304,316 ----
  
  bus::status
  am29_flash_memory::am29_bus::write(host_int_4 address,
! 				   big_int_1 data, big_int_1 *written) throw ()
  {
!   little_int_1 w;
!   bus::status s = write(address, little_int_1(data), & w);
!   if (s == bus::ok)
!     if (written) *written = w;
!   return s;
  }
  
  // static const description table for flash family
Index: sid/component/memory/am29.h
===================================================================
RCS file: /cvs/src/src/sid/component/memory/am29.h,v
retrieving revision 1.1
diff -c -p -r1.1 am29.h
*** sid/component/memory/am29.h	7 Dec 2000 19:30:55 -0000	1.1
--- sid/component/memory/am29.h	17 Mar 2004 20:49:00 -0000
***************
*** 1,7 ****
  // am29.h - A specialisation of the generic uniform sector flash memory
  // class which models the AMD 29xxx series of flash memory.  -*- C++ -*-
  
! // Copyright (C) 1999, 2000 Red Hat.
  // This file is part of SID and is licensed under the GPL.
  // See the file COPYING.SID for conditions for redistribution.
  
--- 1,7 ----
  // am29.h - A specialisation of the generic uniform sector flash memory
  // class which models the AMD 29xxx series of flash memory.  -*- C++ -*-
  
! // Copyright (C) 1999, 2000, 2004 Red Hat.
  // This file is part of SID and is licensed under the GPL.
  // See the file COPYING.SID for conditions for redistribution.
  
*************** private:
*** 59,75 ****
      am29_bus(am29_flash_memory* target):
        target(target) {}
  
!     bus::status write(host_int_4 address, big_int_1 data) 
  								    throw ( );
  
!     bus::status write(host_int_4 address, little_int_1 data)
  								    throw ( );
  
      bus::status read(host_int_4 address, big_int_1& data) throw ( );
      bus::status read(host_int_4 address, little_int_1& data) throw ( );
  
  #define NOPERM_WRITE(type) \
!     bus::status write(host_int_4 address, type data) throw () \
                { return bus::unpermitted; }
    
  #define NOPERM_READ(type) \
--- 59,75 ----
      am29_bus(am29_flash_memory* target):
        target(target) {}
  
!     bus::status write(host_int_4 address, big_int_1 data, big_int_1 *written = 0) 
  								    throw ( );
  
!     bus::status write(host_int_4 address, little_int_1 data, little_int_1 *written = 0)
  								    throw ( );
  
      bus::status read(host_int_4 address, big_int_1& data) throw ( );
      bus::status read(host_int_4 address, little_int_1& data) throw ( );
  
  #define NOPERM_WRITE(type) \
!     bus::status write(host_int_4 address, type data, type *written) throw () \
                { return bus::unpermitted; }
    
  #define NOPERM_READ(type) \
Index: sid/component/memory/at29.cxx
===================================================================
RCS file: /cvs/src/src/sid/component/memory/at29.cxx,v
retrieving revision 1.1
diff -c -p -r1.1 at29.cxx
*** sid/component/memory/at29.cxx	7 Dec 2000 19:30:55 -0000	1.1
--- sid/component/memory/at29.cxx	17 Mar 2004 20:49:00 -0000
***************
*** 1,6 ****
  // at29.cxx - Implementation of ATMEL's 29xxx flash memory.  -*- C++ -*-
  
! // Copyright (C) 1999, 2000 Red Hat.
  // This file is part of SID and is licensed under the GPL.
  // See the file COPYING.SID for conditions for redistribution.
  
--- 1,6 ----
  // at29.cxx - Implementation of ATMEL's 29xxx flash memory.  -*- C++ -*-
  
! // Copyright (C) 1999, 2000, 2004 Red Hat.
  // This file is part of SID and is licensed under the GPL.
  // See the file COPYING.SID for conditions for redistribution.
  
*************** at29_bus::read(host_int_4 address,
*** 134,140 ****
  
  bus::status
  at29_bus::write(host_int_4 address, 
! 		little_int_1 le_data) throw()
  {
    host_int_1 data = le_data;
  
--- 134,140 ----
  
  bus::status
  at29_bus::write(host_int_4 address, 
! 		little_int_1 le_data, little_int_1 *le_written) throw()
  {
    host_int_1 data = le_data;
  
*************** at29_bus::write(host_int_4 address, 
*** 148,153 ****
--- 148,154 ----
        address == SEQ_ADDR1 && data == START_CMD1)
      {
        target->state = at29_flash_memory::START1;
+       if (le_written) *le_written = data;
        return bus::ok;
      }
    
*************** at29_bus::write(host_int_4 address, 
*** 155,160 ****
--- 156,162 ----
        address == SEQ_ADDR1 && data == START_CMD1)
      {
        target->state = at29_flash_memory::START1;
+       if (le_written) *le_written = data;
        return bus::ok;
      }
    
*************** at29_bus::write(host_int_4 address, 
*** 162,167 ****
--- 164,170 ----
        address == SEQ_ADDR2 && data == START_CMD2)
      {
        target->state = at29_flash_memory::START2;
+       if (le_written) *le_written = data;
        return bus::ok;
      }
    
*************** at29_bus::write(host_int_4 address, 
*** 169,174 ****
--- 172,178 ----
        address == SEQ_ADDR1 && data == ID_CMD)
      {
        target->state = at29_flash_memory::IDENT;
+       if (le_written) *le_written = data;
        return bus::ok;
      }
    
*************** at29_bus::write(host_int_4 address, 
*** 176,181 ****
--- 180,186 ----
        address == SEQ_ADDR1 && data == STOP_CMD)
      {
        target->state = at29_flash_memory::LOCKED;
+       if (le_written) *le_written = data;
        return bus::ok;
      }
    
*************** at29_bus::write(host_int_4 address, 
*** 184,189 ****
--- 189,195 ----
      {
        target->state = at29_flash_memory::PROG;
        target->sectorNum = target->noSectorNum;
+       if (le_written) *le_written = data;
        return bus::ok;
      }
    
*************** at29_bus::write(host_int_4 address, 
*** 196,201 ****
--- 202,208 ----
    if (target->write_ok(address))
      {
        target->buffer[address] = data;
+       if (le_written) *le_written = data;
      }
  
    return bus::ok;
*************** at29_bus::write(host_int_4 address, 
*** 204,212 ****
  
  bus::status
  at29_bus::write(host_int_4 address,
! 		big_int_1 data) throw ()
  {
!   return write(address, little_int_1(data));
  }
  
  
--- 211,223 ----
  
  bus::status
  at29_bus::write(host_int_4 address,
! 		big_int_1 data, big_int_1 *written) throw ()
  {
!   little_int_1 w;
!   bus::status s = write(address, little_int_1(data), & w);
!   if (s)
!     if (written) *written = w;
!   return s;
  }
  
  
Index: sid/component/memory/at29.h
===================================================================
RCS file: /cvs/src/src/sid/component/memory/at29.h,v
retrieving revision 1.1
diff -c -p -r1.1 at29.h
*** sid/component/memory/at29.h	7 Dec 2000 19:30:55 -0000	1.1
--- sid/component/memory/at29.h	17 Mar 2004 20:49:00 -0000
***************
*** 1,7 ****
  // at29.h - A specialisation of the generic flash memory class to
  // model the ATMEL 29xxx series of flash memory.  -*- C++ -*-
  
! // Copyright (C) 1999, 2000 Red Hat.
  // This file is part of SID and is licensed under the GPL.
  // See the file COPYING.SID for conditions for redistribution.
  
--- 1,7 ----
  // at29.h - A specialisation of the generic flash memory class to
  // model the ATMEL 29xxx series of flash memory.  -*- C++ -*-
  
! // Copyright (C) 1999, 2000, 2004 Red Hat.
  // This file is part of SID and is licensed under the GPL.
  // See the file COPYING.SID for conditions for redistribution.
  
*************** class at29_bus: public bus
*** 64,76 ****
  public:
    at29_bus(at29_flash_memory* target): target(target) {}
    
!   bus::status write(host_int_4 address, big_int_1 data) throw ();
!   bus::status write(host_int_4 address, little_int_1 data) throw ();
    bus::status read(host_int_4 address, big_int_1& data) throw ();
    bus::status read(host_int_4 address, little_int_1& data) throw ();
    
  #define NOPERM_WRITE(type) \
!     bus::status write(host_int_4 address, type data) throw () \
                { return bus::unpermitted; }
    
  #define NOPERM_READ(type) \
--- 64,76 ----
  public:
    at29_bus(at29_flash_memory* target): target(target) {}
    
!   bus::status write(host_int_4 address, big_int_1 data, big_int_1 *written = 0) throw ();
!   bus::status write(host_int_4 address, little_int_1 data, little_int_1 *written = 0) throw ();
    bus::status read(host_int_4 address, big_int_1& data) throw ();
    bus::status read(host_int_4 address, little_int_1& data) throw ();
    
  #define NOPERM_WRITE(type) \
!     bus::status write(host_int_4 address, type data, type *written) throw () \
                { return bus::unpermitted; }
    
  #define NOPERM_READ(type) \
Index: sid/component/memory/generic.h
===================================================================
RCS file: /cvs/src/src/sid/component/memory/generic.h,v
retrieving revision 1.5
diff -c -p -r1.5 generic.h
*** sid/component/memory/generic.h	3 Aug 2001 06:02:46 -0000	1.5
--- sid/component/memory/generic.h	17 Mar 2004 20:49:00 -0000
***************
*** 1,6 ****
  // generic.h - Header for the generic_memory class.  -*- C++ -*-
  
! // Copyright (C) 1999-2001 Red Hat.
  // This file is part of SID and is licensed under the GPL.
  // See the file COPYING.SID for conditions for redistribution.
  
--- 1,6 ----
  // generic.h - Header for the generic_memory class.  -*- C++ -*-
  
! // Copyright (C) 1999-2001, 2004 Red Hat.
  // This file is part of SID and is licensed under the GPL.
  // See the file COPYING.SID for conditions for redistribution.
  
*************** public:
*** 124,130 ****
  
    // some macros to make manufacturing of the cartesian-product calls simpler
  #define SID_GB_WRITE(type2) \
!       bus::status write(host_int_4 address, type2 data) throw () \
  	  { return bus::unpermitted; } 
   
  #define SID_GB_READ(type2) \
--- 124,130 ----
  
    // some macros to make manufacturing of the cartesian-product calls simpler
  #define SID_GB_WRITE(type2) \
!       bus::status write(host_int_4 address, type2 data, type2 *written) throw () \
  	  { return bus::unpermitted; } 
   
  #define SID_GB_READ(type2) \
*************** public:
*** 174,181 ****
  
    // some macros to make manufacturing of the cartesian-product calls simpler
  #define SID_GB_WRITE(type2) \
!       bus::status write(host_int_4 address, type2 data) throw () \
! 	      { return this->write_any(address,data); } \
    
    // ----------------------------------------------------------------
    
--- 174,181 ----
  
    // some macros to make manufacturing of the cartesian-product calls simpler
  #define SID_GB_WRITE(type2) \
!       bus::status write(host_int_4 address, type2 data, type2 *written) throw () \
! 	      { return this->write_any(address,data,written); } \
    
    // ----------------------------------------------------------------
    
*************** public:
*** 194,200 ****
  protected:
    template <typename DataType>
    inline bus::status
!   write_any(host_int_4 address, DataType data);
  };
  
  
--- 194,200 ----
  protected:
    template <typename DataType>
    inline bus::status
!   write_any(host_int_4 address, DataType data, DataType *written);
  };
  
  
*************** protected:
*** 203,209 ****
  
  template <typename DataType>
  inline bus::status
! generic_read_write_bus::write_any(host_int_4 address, DataType data)
  {
    const unsigned width = sizeof(typename DataType::value_type); 
  
--- 203,209 ----
  
  template <typename DataType>
  inline bus::status
! generic_read_write_bus::write_any(host_int_4 address, DataType data, DataType *written)
  {
    const unsigned width = sizeof(typename DataType::value_type); 
  
*************** generic_read_write_bus::write_any(host_i
*** 214,219 ****
--- 214,220 ----
        memcpy (& target->buffer[address], & mem_image, width);
        bus::status st (bus::ok);
        st.latency = target->write_latency;
+       if (written) *written = data;
        return st;
      }
  
Index: sid/component/mmu/armRemap.cxx
===================================================================
RCS file: /cvs/src/src/sid/component/mmu/armRemap.cxx,v
retrieving revision 1.2
diff -c -p -r1.2 armRemap.cxx
*** sid/component/mmu/armRemap.cxx	11 Nov 2002 22:28:28 -0000	1.2
--- sid/component/mmu/armRemap.cxx	17 Mar 2004 20:49:00 -0000
***************
*** 1,7 ****
  // armRemap.cxx - An implementation of the "remap and pause"
  // controller from the ARM PID7T development board.  -*- C++ -*-
  
! // Copyright (C) 1999, 2000, 2002 Red Hat.
  // This file is part of SID and is licensed under the GPL.
  // See the file COPYING.SID for conditions for redistribution.
  
--- 1,7 ----
  // armRemap.cxx - An implementation of the "remap and pause"
  // controller from the ARM PID7T development board.  -*- C++ -*-
  
! // Copyright (C) 1999, 2000, 2002, 2004 Red Hat.
  // This file is part of SID and is licensed under the GPL.
  // See the file COPYING.SID for conditions for redistribution.
  
*************** private:
*** 83,89 ****
      map_bus(armRemapPause* target) :target(target) {}
  
  #define BUS_WRITE(type1, type2) \
!     virtual bus::status write(type1 address, type2 data) throw () = 0;
  #define BUS_READ(type1, type2) \
      virtual bus::status read(type1 address, type2& data) throw () = 0;
      
--- 83,89 ----
      map_bus(armRemapPause* target) :target(target) {}
  
  #define BUS_WRITE(type1, type2) \
!     virtual bus::status write(type1 address, type2 data, type2 *written = 0) throw () = 0;
  #define BUS_READ(type1, type2) \
      virtual bus::status read(type1 address, type2& data) throw () = 0;
      
*************** private:
*** 118,127 ****
      reset_map_bus(armRemapPause* target): map_bus(target) {}
  
  #define BUS_WRITE(type1, type2) \
!     bus::status write(type1 address, type2 data) throw () { \
          if (! target->downstream_bus) return bus::unmapped; \
          type1 newAddress = translate(address); \
! 	return target->downstream_bus->write(newAddress, data);\
      }
  
  #define BUS_READ(type1, type2) \
--- 118,127 ----
      reset_map_bus(armRemapPause* target): map_bus(target) {}
  
  #define BUS_WRITE(type1, type2) \
!     bus::status write(type1 address, type2 data, type2 *written) throw () { \
          if (! target->downstream_bus) return bus::unmapped; \
          type1 newAddress = translate(address); \
! 	return target->downstream_bus->write(newAddress, data, written);\
      }
  
  #define BUS_READ(type1, type2) \
*************** private:
*** 176,184 ****
      normal_map_bus(armRemapPause* target): map_bus(target) {}
  
  #define BUS_WRITE(type1,type2) \
!     bus::status write(type1 address, type2 data) throw ( ) { \
          if (! target->downstream_bus) return bus::unmapped; \
! 	  return target->downstream_bus->write(address, data); }
    
  #define BUS_READ(type1,type2) \
      bus::status read(type1 address, type2& data) throw ( ) { \
--- 176,184 ----
      normal_map_bus(armRemapPause* target): map_bus(target) {}
  
  #define BUS_WRITE(type1,type2) \
!     bus::status write(type1 address, type2 data, type2 *written) throw ( ) { \
          if (! target->downstream_bus) return bus::unmapped; \
! 	  return target->downstream_bus->write(address, data, written); }
    
  #define BUS_READ(type1,type2) \
      bus::status read(type1 address, type2& data) throw ( ) { \
*************** private:
*** 223,230 ****
      void use_normal_map();
  
  #define BUS_WRITE(type1, type2) \
!     bus::status write(type1 address, type2 data) throw () \
!       { return bus->write(address, data); }
      
  #define BUS_READ(type1, type2) \
      bus::status read(type1 address, type2& data) throw () \
--- 223,230 ----
      void use_normal_map();
  
  #define BUS_WRITE(type1, type2) \
!     bus::status write(type1 address, type2 data, type2 *written) throw () \
!       { return bus->write(address, data, written); }
      
  #define BUS_READ(type1, type2) \
      bus::status read(type1 address, type2& data) throw () \
*************** private:
*** 268,274 ****
  
      bus::status word_write(host_int_4 addr,
  			   little_int_4 mask,
! 			   little_int_4 data);
  
      bus::status word_read(host_int_4 addr,
  			  little_int_4 mask,
--- 268,275 ----
  
      bus::status word_write(host_int_4 addr,
  			   little_int_4 mask,
! 			   little_int_4 data,
! 			   little_int_4 *written);
  
      bus::status word_read(host_int_4 addr,
  			  little_int_4 mask,
*************** armRemapPause::remap_bus::use_normal_map
*** 652,658 ****
  bus::status
  armRemapPause::bus_interface::word_write(host_int_4 addr,
  					 little_int_4 mask,
! 					 little_int_4 le_data) 
  {
    host_int_4 data = le_data;
    switch (addr)
--- 653,660 ----
  bus::status
  armRemapPause::bus_interface::word_write(host_int_4 addr,
  					 little_int_4 mask,
! 					 little_int_4 le_data,
! 					 little_int_4 *le_written)
  {
    host_int_4 data = le_data;
    switch (addr)
*************** armRemapPause::bus_interface::word_write
*** 677,682 ****
--- 679,686 ----
        target->resetStatus &= ~data;
        break;
      }
+   if (le_written)
+     *le_written = le_data;
    return bus::ok;
  }
  
Index: sid/component/parport/ps2.cxx
===================================================================
RCS file: /cvs/src/src/sid/component/parport/ps2.cxx,v
retrieving revision 1.3
diff -c -p -r1.3 ps2.cxx
*** sid/component/parport/ps2.cxx	22 Nov 2002 20:34:59 -0000	1.3
--- sid/component/parport/ps2.cxx	17 Mar 2004 20:49:00 -0000
***************
*** 1,6 ****
  // ps2.cxx - Simulation of the PS/2 parallel controller.  -*- C++ -*-
  
! // Copyright (C) 1999, 2000 Red Hat.
  // This file is part of SID and is licensed under the GPL.
  // See the file COPYING.SID for conditions for redistribution.
  
--- 1,6 ----
  // ps2.cxx - Simulation of the PS/2 parallel controller.  -*- C++ -*-
  
! // Copyright (C) 1999, 2000, 2004 Red Hat.
  // This file is part of SID and is licensed under the GPL.
  // See the file COPYING.SID for conditions for redistribution.
  
*************** register won't have any affect on the re
*** 451,457 ****
  */
  sid::bus::status
  ParPort::write_parport(host_int_4 reg_index,
! 		      host_int_1 reg_val)
  {
    host_int_1 store_val = reg_val;
  
--- 451,457 ----
  */
  sid::bus::status
  ParPort::write_parport(host_int_4 reg_index,
! 		      host_int_1 reg_val, host_int_1 *written)
  {
    host_int_1 store_val = reg_val;
  
*************** ParPort::write_parport(host_int_4 reg_in
*** 481,486 ****
--- 481,488 ----
    // check for triggerpoints
    triggerpoint_manager.check_and_dispatch ();
  
+   if (written) *written = store_val;
+ 
    return sid::bus::ok;
  }
  
*************** operator >> (istream& ip, ParPort& ovwri
*** 1250,1256 ****
    ovwrite_obj.regs[IOSEL] = reg_val;
  
    ip >> reg_val; // CON val
!   ovwrite_obj.write_parport(2, reg_val); // Pins will be updated
  
    ip >> reg_val; //PR reg
    if ( ! ovwrite_obj.output_mode() )
--- 1252,1258 ----
    ovwrite_obj.regs[IOSEL] = reg_val;
  
    ip >> reg_val; // CON val
!   ovwrite_obj.write_parport(2, reg_val, 0); // Pins will be updated
  
    ip >> reg_val; //PR reg
    if ( ! ovwrite_obj.output_mode() )
Index: sid/component/parport/ps2.h
===================================================================
RCS file: /cvs/src/src/sid/component/parport/ps2.h,v
retrieving revision 1.2
diff -c -p -r1.2 ps2.h
*** sid/component/parport/ps2.h	3 Aug 2001 06:02:46 -0000	1.2
--- sid/component/parport/ps2.h	17 Mar 2004 20:49:00 -0000
***************
*** 1,6 ****
  // ps2.h - Simulation of PS/2 parallel controller.  -*- C++ -*-
  
! // Copyright (C) 1999, 2000 Red Hat.
  // This file is part of SID and is licensed under the GPL.
  // See the file COPYING.SID for conditions for redistribution.
  
--- 1,6 ----
  // ps2.h - Simulation of PS/2 parallel controller.  -*- C++ -*-
  
! // Copyright (C) 1999, 2000, 2004 Red Hat.
  // This file is part of SID and is licensed under the GPL.
  // See the file COPYING.SID for conditions for redistribution.
  
*************** private:
*** 200,206 ****
    
    // Write to Registers.
    sid::bus::status write_parport (host_int_4 reg_index, 
! 				  host_int_1 reg_val);  
    
    void add_bus_pins();
    void store_registerAttr();
--- 200,206 ----
    
    // Write to Registers.
    sid::bus::status write_parport (host_int_4 reg_index, 
! 				  host_int_1 reg_val, host_int_1 *written);  
    
    void add_bus_pins();
    void store_registerAttr();
Index: sid/component/rtc/components.h
===================================================================
RCS file: /cvs/src/src/sid/component/rtc/components.h,v
retrieving revision 1.3
diff -c -p -r1.3 components.h
*** sid/component/rtc/components.h	3 Aug 2001 06:02:46 -0000	1.3
--- sid/component/rtc/components.h	17 Mar 2004 20:49:00 -0000
***************
*** 1,7 ****
  // components.h - A simulation of the Dallas 1x42 time-keeping NVRAMs.
  // -*- C++ -*-
  
! // Copyright (C) 1999-2001 Red Hat.
  // This file is part of SID and is licensed under the GPL.
  // See the file COPYING.SID for conditions for redistribution.
  
--- 1,7 ----
  // components.h - A simulation of the Dallas 1x42 time-keeping NVRAMs.
  // -*- C++ -*-
  
! // Copyright (C) 1999-2001, 2004 Red Hat.
  // This file is part of SID and is licensed under the GPL.
  // See the file COPYING.SID for conditions for redistribution.
  
*************** protected:
*** 79,85 ****
        :target(target) {}
              
    protected:
!     status write_data(host_int_4 addr, host_int_1 data) throw();
      status read_data(host_int_4 addr, host_int_1& data) throw();
      ds1642* target;
    };
--- 79,85 ----
        :target(target) {}
              
    protected:
!     status write_data(host_int_4 addr, host_int_1 data, host_int_1 *written) throw();
      status read_data(host_int_4 addr, host_int_1& data) throw();
      ds1642* target;
    };
*************** class sidrtc: public virtual component,
*** 237,243 ****
  {
    class mybus: public word_bus<big_int_4>
    {
!     bus::status word_write (host_int_4 addr, big_int_4 mask, big_int_4 data);
      bus::status word_read (host_int_4 addr, big_int_4 mask, big_int_4& data);
  
    public:
--- 237,243 ----
  {
    class mybus: public word_bus<big_int_4>
    {
!     bus::status word_write (host_int_4 addr, big_int_4 mask, big_int_4 data, big_int_4 *written);
      bus::status word_read (host_int_4 addr, big_int_4 mask, big_int_4& data);
  
    public:
Index: sid/component/rtc/ds1x42.cxx
===================================================================
RCS file: /cvs/src/src/sid/component/rtc/ds1x42.cxx,v
retrieving revision 1.1
diff -c -p -r1.1 ds1x42.cxx
*** sid/component/rtc/ds1x42.cxx	7 Dec 2000 19:30:56 -0000	1.1
--- sid/component/rtc/ds1x42.cxx	17 Mar 2004 20:49:00 -0000
***************
*** 1,7 ****
  // ds1x42.cxx - A simulation of the Dallas DS1x42 time-keeping NVRAMs.
  // -*- C++ -*-
  
! // Copyright (C) 1999, 2000 Red Hat.
  // This file is part of SID and is licensed under the GPL.
  // See the file COPYING.SID for conditions for redistribution.
  
--- 1,7 ----
  // ds1x42.cxx - A simulation of the Dallas DS1x42 time-keeping NVRAMs.
  // -*- C++ -*-
  
! // Copyright (C) 1999, 2000, 2004 Red Hat.
  // This file is part of SID and is licensed under the GPL.
  // See the file COPYING.SID for conditions for redistribution.
  
*************** static host_int_1 bin_to_bcd(unsigned sh
*** 22,28 ****
  
  bus::status
  ds1642::ds1642_bus::write_data(host_int_4 address,
! 			       host_int_1 data) throw()
  {
    bus::status st;
  
--- 22,28 ----
  
  bus::status
  ds1642::ds1642_bus::write_data(host_int_4 address,
! 			       host_int_1 data, host_int_1 *written) throw()
  {
    bus::status st;
  
*************** ds1642::ds1642_bus::write_data(host_int_
*** 38,43 ****
--- 38,44 ----
  	  target->set_year_attribute(make_attribute(value));
  	}
        target->triggerpoint_manager.check_and_dispatch();
+       if (written) *written = data;
        return ok;
  
      case 0x7FE:
*************** ds1642::ds1642_bus::write_data(host_int_
*** 54,59 ****
--- 55,61 ----
  	}
  
        target->triggerpoint_manager.check_and_dispatch();
+       if (written) *written = data;
        return ok;
  
      case 0x7FD:
*************** ds1642::ds1642_bus::write_data(host_int_
*** 70,75 ****
--- 72,78 ----
  	}
  
        target->triggerpoint_manager.check_and_dispatch();
+       if (written) *written = data;
        return ok;
  
      case 0x7FC:
*************** ds1642::ds1642_bus::write_data(host_int_
*** 95,100 ****
--- 98,104 ----
  	}
  
        target->triggerpoint_manager.check_and_dispatch();
+       if (written) *written = data;
        return ok;
  
      case 0x7FB:
*************** ds1642::ds1642_bus::write_data(host_int_
*** 111,116 ****
--- 115,121 ----
  	}
  
        target->triggerpoint_manager.check_and_dispatch();
+       if (written) *written = data;
        return ok;
  
      case 0x7FA:
*************** ds1642::ds1642_bus::write_data(host_int_
*** 127,135 ****
--- 132,142 ----
  	}
  
        target->triggerpoint_manager.check_and_dispatch();
+       if (written) *written = data;
        return ok;
  
      case 0x7F9:
+       if (written) *written = data;
        if (target->disconnected_p && !(data & 0x80))
  	{
  	  target->connect_oscillator();
*************** ds1642::ds1642_bus::write_data(host_int_
*** 151,160 ****
--- 158,169 ----
        return ok;
  
      case 0x7F8:
+       if (written) *written = data;
        return target->write_7f8(data);
        
      default:
        // Any of the remaining 2K NVRAM can be written to.
+       if (written) *written = data;
        temp = data;
        return target->membus->write(address, temp);
      }
Index: sid/component/rtc/sidrtc.cxx
===================================================================
RCS file: /cvs/src/src/sid/component/rtc/sidrtc.cxx,v
retrieving revision 1.2
diff -c -p -r1.2 sidrtc.cxx
*** sid/component/rtc/sidrtc.cxx	4 Apr 2001 23:54:05 -0000	1.2
--- sid/component/rtc/sidrtc.cxx	17 Mar 2004 20:49:00 -0000
***************
*** 1,6 ****
  // sidrtc.cxx - A simple real-time clock component.  -*- C++ -*-
  
! // Copyright (C) 1999-2001 Red Hat.
  // This file is part of SID and is licensed under the GPL.
  // See the file COPYING.SID for conditions for redistribution.
  
--- 1,6 ----
  // sidrtc.cxx - A simple real-time clock component.  -*- C++ -*-
  
! // Copyright (C) 1999-2001, 2004 Red Hat.
  // This file is part of SID and is licensed under the GPL.
  // See the file COPYING.SID for conditions for redistribution.
  
*************** sidrtc::get_seconds_attribute ()
*** 58,64 ****
  
  
  bus::status
! sidrtc::mybus::word_write (host_int_4 addr, big_int_4 mask, big_int_4 data)
  { 
    return bus::unpermitted; 
  }
--- 58,64 ----
  
  
  bus::status
! sidrtc::mybus::word_write (host_int_4 addr, big_int_4 mask, big_int_4 data, big_int_4 *written)
  { 
    return bus::unpermitted; 
  }
Index: sid/component/tcl/compTcl.cxx
===================================================================
RCS file: /cvs/src/src/sid/component/tcl/compTcl.cxx,v
retrieving revision 1.6
diff -c -p -r1.6 compTcl.cxx
*** sid/component/tcl/compTcl.cxx	12 Jul 2001 11:37:32 -0000	1.6
--- sid/component/tcl/compTcl.cxx	17 Mar 2004 20:49:01 -0000
***************
*** 1,6 ****
  // compTcl.cxx - Tcl bridge component.  -*- C++ -*-
  
! // Copyright (C) 1999, 2000, 2001 Red Hat.
  // This file is part of SID and is licensed under the GPL.
  // See the file COPYING.SID for conditions for redistribution.
  
--- 1,6 ----
  // compTcl.cxx - Tcl bridge component.  -*- C++ -*-
  
! // Copyright (C) 1999-2001, 2004 Red Hat.
  // This file is part of SID and is licensed under the GPL.
  // See the file COPYING.SID for conditions for redistribution.
  
*************** public:
*** 1443,1450 ****
  // write_h4_[lb]Y BUS ADDRESS DATA, for host_int_4/{little,big}_int_Y.
  // The tcl procedure should return "status".
  
! status write (host_int_4 address, big_int_1 data) throw ()
  {
    return this->write_any ("write_h4_b1", 
  			 make_attribute (address)
  			 + " " + 
--- 1443,1452 ----
  // write_h4_[lb]Y BUS ADDRESS DATA, for host_int_4/{little,big}_int_Y.
  // The tcl procedure should return "status".
  
! status write (host_int_4 address, big_int_1 data, big_int_1 *written = 0) throw ()
  {
+   if (written)
+     *written = data;
    return this->write_any ("write_h4_b1", 
  			 make_attribute (address)
  			 + " " + 
*************** status read (host_int_4 address, big_int
*** 1464,1471 ****
  }
  
  
! status write (host_int_4 address, big_int_2 data) throw ()
  {
    return this->write_any ("write_h4_b2", 
  			 make_attribute (address)
  			 + " " + 
--- 1466,1475 ----
  }
  
  
! status write (host_int_4 address, big_int_2 data, big_int_2 *written) throw ()
  {
+   if (written)
+     *written = data;
    return this->write_any ("write_h4_b2", 
  			 make_attribute (address)
  			 + " " + 
*************** status read (host_int_4 address, big_int
*** 1485,1492 ****
  }
  
  
! status write (host_int_4 address, big_int_4 data) throw ()
  {
    return this->write_any ("write_h4_b4", 
  			 make_attribute (address)
  			 + " " + 
--- 1489,1498 ----
  }
  
  
! status write (host_int_4 address, big_int_4 data, big_int_4 *written) throw ()
  {
+   if (written)
+     *written = data;
    return this->write_any ("write_h4_b4", 
  			 make_attribute (address)
  			 + " " + 
*************** status read (host_int_4 address, big_int
*** 1505,1512 ****
    return res.first;
  }
  
! status write (host_int_4 address, big_int_8 data) throw ()
  {
    return this->write_any ("write_h4_b8", 
  			 make_attribute (address)
  			 + " " + 
--- 1511,1520 ----
    return res.first;
  }
  
! status write (host_int_4 address, big_int_8 data, big_int_8 *written) throw ()
  {
+   if (written)
+     *written = data;
    return this->write_any ("write_h4_b8", 
  			 make_attribute (address)
  			 + " " + 
*************** status read (host_int_4 address, big_int
*** 1526,1533 ****
  }
  
  
! status write (host_int_4 address, little_int_1 data) throw ()
  {
    return this->write_any ("write_h4_l1", 
  			 make_attribute (address)
  			 + " " + 
--- 1534,1543 ----
  }
  
  
! status write (host_int_4 address, little_int_1 data, little_int_1 *written) throw ()
  {
+   if (written)
+     *written = data;
    return this->write_any ("write_h4_l1", 
  			 make_attribute (address)
  			 + " " + 
*************** status read (host_int_4 address, little_
*** 1548,1555 ****
  
  
  
! status write (host_int_4 address, little_int_2 data) throw ()
  {
    return this->write_any ("write_h4_l2", 
  			 make_attribute (address)
  			 + " " + 
--- 1558,1567 ----
  
  
  
! status write (host_int_4 address, little_int_2 data, little_int_2 *written) throw ()
  {
+   if (written)
+     *written = data;
    return this->write_any ("write_h4_l2", 
  			 make_attribute (address)
  			 + " " + 
*************** status read (host_int_4 address, little_
*** 1569,1576 ****
  }
  
  
! status write (host_int_4 address, little_int_4 data) throw ()
  {
    return this->write_any ("write_h4_l4", 
  			 make_attribute (address)
  			 + " " + 
--- 1581,1590 ----
  }
  
  
! status write (host_int_4 address, little_int_4 data, little_int_4 *written) throw ()
  {
+   if (written)
+     *written = data;
    return this->write_any ("write_h4_l4", 
  			 make_attribute (address)
  			 + " " + 
*************** status read (host_int_4 address, little_
*** 1590,1597 ****
  }
  
  
! status write (host_int_4 address, little_int_8 data) throw ()
  {
    return this->write_any ("write_h4_l8", 
  			 make_attribute (address)
  			 + " " + 
--- 1604,1613 ----
  }
  
  
! status write (host_int_4 address, little_int_8 data, little_int_8 *written) throw ()
  {
+   if (written)
+     *written = data;
    return this->write_any ("write_h4_l8", 
  			 make_attribute (address)
  			 + " " + 
Index: sid/component/uart/Uart.cxx
===================================================================
RCS file: /cvs/src/src/sid/component/uart/Uart.cxx,v
retrieving revision 1.2
diff -c -p -r1.2 Uart.cxx
*** sid/component/uart/Uart.cxx	3 Aug 2001 06:02:48 -0000	1.2
--- sid/component/uart/Uart.cxx	17 Mar 2004 20:49:01 -0000
***************
*** 1,6 ****
  // Uart.cxx - NS16550 UART component.  -*- C++ -*-
  
! // Copyright (C) 1999, 2000 Red Hat.
  // This file is part of SID and is licensed under the GPL.
  // See the file COPYING.SID for conditions for redistribution.
  
--- 1,6 ----
  // Uart.cxx - NS16550 UART component.  -*- C++ -*-
  
! // Copyright (C) 1999, 2000, 2004 Red Hat.
  // This file is part of SID and is licensed under the GPL.
  // See the file COPYING.SID for conditions for redistribution.
  
*************** Uart::busReadHandler( host_int_4 index, 
*** 537,556 ****
  }
  
  sid::bus::status
! Uart :: busWriteHandler( host_int_4 index, host_int_1 val ) {
    switch( index ) {
    case 0:
      if( bit_test( regs[LCR], LCR_DLAB ) )
        regs[DLL] = val;
      else
        xmit( val );
      break;
  
    case 1:
      if( bit_test( regs[LCR], LCR_DLAB ) )
!       regs[DLM] = val;
      else {
        regs[IER] = val & 0x0f;
  
        if( setInterruptId() ) {	// did we enable something that was pending?
  	if( bit_test( regs[IIR], IIR_NPEND) ) {
--- 537,561 ----
  }
  
  sid::bus::status
! Uart :: busWriteHandler( host_int_4 index, host_int_1 val, host_int_1 *written ) {
    switch( index ) {
    case 0:
      if( bit_test( regs[LCR], LCR_DLAB ) )
        regs[DLL] = val;
      else
        xmit( val );
+     if (written) *written = val;
      break;
  
    case 1:
      if( bit_test( regs[LCR], LCR_DLAB ) )
!       {
! 	regs[DLM] = val;
! 	if (written) *written = val;
!       }
      else {
        regs[IER] = val & 0x0f;
+       if (written) *written = val & 0x0f;
  
        if( setInterruptId() ) {	// did we enable something that was pending?
  	if( bit_test( regs[IIR], IIR_NPEND) ) {
*************** Uart :: busWriteHandler( host_int_4 inde
*** 573,587 ****
--- 578,595 ----
  
    case 2: // FCR (write-only)
      setFunctionReg( val );
+     if (written) *written = regs[FCR];
      break;
  
    case LCR:
    case SCR:
      regs[index] = val;
+     if (written) *written = val;
      break;
  
    case MCR:
      setModemControlReg( val );
+     if (written) *written = regs[MCR];
      break;
  
    case MSR:
*************** operator >> (istream& ip, Uart& ovwrite_
*** 1262,1268 ****
  	if (reg_num != MCR)
  	   ovwrite_obj.regs[reg_num] = reg_value;
          else
! 	  ovwrite_obj.busWriteHandler(MCR, (host_int_1)reg_value); // Will drive o/p pins too
        }
  
      if ( bit_test(ovwrite_obj.regs[IIR], IIR_NPEND) )
--- 1270,1276 ----
  	if (reg_num != MCR)
  	   ovwrite_obj.regs[reg_num] = reg_value;
          else
! 	  ovwrite_obj.busWriteHandler(MCR, (host_int_1)reg_value, 0); // Will drive o/p pins too
        }
  
      if ( bit_test(ovwrite_obj.regs[IIR], IIR_NPEND) )
Index: sid/component/uart/Uart.h
===================================================================
RCS file: /cvs/src/src/sid/component/uart/Uart.h,v
retrieving revision 1.2
diff -c -p -r1.2 Uart.h
*** sid/component/uart/Uart.h	3 Aug 2001 06:02:48 -0000	1.2
--- sid/component/uart/Uart.h	17 Mar 2004 20:49:01 -0000
***************
*** 1,6 ****
  // Uart.h - Declarations for the 16550 UART component.  -*- C++ -*-
  
! // Copyright (C) 1999, 2000 Red Hat.
  // This file is part of SID and is licensed under the GPL.
  // See the file COPYING.SID for conditions for redistribution.
  
--- 1,6 ----
  // Uart.h - Declarations for the 16550 UART component.  -*- C++ -*-
  
! // Copyright (C) 1999, 2000, 2004 Red Hat.
  // This file is part of SID and is licensed under the GPL.
  // See the file COPYING.SID for conditions for redistribution.
  
*************** private:
*** 93,99 ****
    callback_byte_bus<Uart> busif;
  
    bus::status busReadHandler( host_int_4 index, host_int_1& val );
!   bus::status busWriteHandler( host_int_4 index, host_int_1 val);
  
    // Output pins
  
--- 93,99 ----
    callback_byte_bus<Uart> busif;
  
    bus::status busReadHandler( host_int_4 index, host_int_1& val );
!   bus::status busWriteHandler( host_int_4 index, host_int_1 val, host_int_1 *written);
  
    // Output pins
  
Index: sid/include/sidbusutil.h
===================================================================
RCS file: /cvs/src/src/sid/include/sidbusutil.h,v
retrieving revision 1.14
diff -c -p -r1.14 sidbusutil.h
*** sid/include/sidbusutil.h	21 Oct 2003 21:38:24 -0000	1.14
--- sid/include/sidbusutil.h	17 Mar 2004 20:49:01 -0000
***************
*** 1,6 ****
  // sidbusutil.h -*- C++ -*- Different types and sizes of buses.
  
! // Copyright (C) 1999, 2000, 2001, 2002 Red Hat.
  // This file is part of SID and is licensed under the GPL.
  // See the file COPYING.SID for conditions for redistribution.
  
--- 1,6 ----
  // sidbusutil.h -*- C++ -*- Different types and sizes of buses.
  
! // Copyright (C) 1999-2002, 2004 Red Hat.
  // This file is part of SID and is licensed under the GPL.
  // See the file COPYING.SID for conditions for redistribution.
  
*************** namespace sidutil
*** 30,36 ****
  
      virtual sid::bus::status word_write(sid::host_int_4 addr,
  					DataType mask,
! 					DataType data) = 0;
  
      virtual sid::bus::status word_read(sid::host_int_4 addr,
  				       DataType mask,
--- 30,37 ----
  
      virtual sid::bus::status word_write(sid::host_int_4 addr,
  					DataType mask,
! 					DataType data,
! 					DataType *written) = 0;
  
      virtual sid::bus::status word_read(sid::host_int_4 addr,
  				       DataType mask,
*************** namespace sidutil
*** 43,49 ****
      // in its required data size.
      template <typename AccDataType>
      bus::status
!     writeAny(sid::host_int_4 address, AccDataType data)
        {
  	unsigned busWidth = sizeof(typename DataType::value_type);
  	unsigned accWidth = sizeof(typename AccDataType::value_type);
--- 44,50 ----
      // in its required data size.
      template <typename AccDataType>
      bus::status
!     writeAny(sid::host_int_4 address, AccDataType data, AccDataType *written)
        {
  	unsigned busWidth = sizeof(typename DataType::value_type);
  	unsigned accWidth = sizeof(typename AccDataType::value_type);
*************** namespace sidutil
*** 60,84 ****
  	    d.write_byte((bytesWritten + a) % busWidth, byte);
  	    mask.write_byte((bytesWritten + a) % busWidth, 0xff);
  
! 	    if(((bytesWritten + a) % busWidth == (busWidth - 1)) || // last byte in target
! 	       (bytesWritten == (accWidth - 1))) // last byte in source
  	      {
  		sid::bus::status s;
  
! 		s = this->word_write(sid::host_int_4(a / busWidth), mask, d);
  		if (s != sid::bus::ok)
  		  {
  		    this->post_access_hook();
  		    return s;
  		  }
  
  		a = a + busWidth; // advance address
  		// Clear data.
  		d = 0;
  		// Clear mask.
  		mask = 0;
  	      }
- 	    bytesWritten ++;
  	  }
  
  	this->post_access_hook();
--- 61,99 ----
  	    d.write_byte((bytesWritten + a) % busWidth, byte);
  	    mask.write_byte((bytesWritten + a) % busWidth, 0xff);
  
! 	    bytesWritten ++;
! 	    if (written)
! 	      *written = *written << 8;
! 
! 	    if(((bytesWritten + a) % busWidth == 0) || // last byte in target
! 	       (bytesWritten == accWidth)) // last byte in source
  	      {
  		sid::bus::status s;
+ 		DataType w;
  
! 		s = this->word_write(sid::host_int_4(a / busWidth), mask, d, & w);
  		if (s != sid::bus::ok)
  		  {
  		    this->post_access_hook();
  		    return s;
  		  }
  
+ 		// update data actually written
+ 
+ 		if (written)
+ 		  {
+ 		    // May have to shift data for the final word written.
+ 		    if (bytesWritten == accWidth)
+ 		      w = w >> ((a % busWidth) * 8);
+ 		    *written = *written | w;
+ 		  }
+ 
  		a = a + busWidth; // advance address
  		// Clear data.
  		d = 0;
  		// Clear mask.
  		mask = 0;
  	      }
  	  }
  
  	this->post_access_hook();
*************** namespace sidutil
*** 145,152 ****
      // Some macros to make manufacturing of the cartesian-product
      // calls simpler.
  #define SID_GB_WRITE(type1,type2) \
!       sid::bus::status write(type1 addr, type2 data) throw () \
! 	  { return writeAny(addr, data); }
      
  #define SID_GB_READ(type1,type2) \
        sid::bus::status read(type1 addr, type2& data) throw () \
--- 160,167 ----
      // Some macros to make manufacturing of the cartesian-product
      // calls simpler.
  #define SID_GB_WRITE(type1,type2) \
!       sid::bus::status write(type1 addr, type2 data, type2 *written = 0) throw () \
! 	  { return writeAny(addr, data, written); }
      
  #define SID_GB_READ(type1,type2) \
        sid::bus::status read(type1 addr, type2& data) throw () \
*************** namespace sidutil
*** 181,187 ****
    {
    public:
      typedef sid::bus::status (Master::*ReadFunction) (sid::host_int_4, DataType, DataType&);
!     typedef sid::bus::status (Master::*WriteFunction) (sid::host_int_4, DataType, DataType);
  
    private:
      Master* receiver;
--- 196,202 ----
    {
    public:
      typedef sid::bus::status (Master::*ReadFunction) (sid::host_int_4, DataType, DataType&);
!     typedef sid::bus::status (Master::*WriteFunction) (sid::host_int_4, DataType, DataType, DataType *);
  
    private:
      Master* receiver;
*************** namespace sidutil
*** 190,198 ****
  
      sid::bus::status word_write(sid::host_int_4 addr,
  				DataType mask,
! 				DataType data)
        {
! 	return (receiver->*write_callback) (addr, mask, data);
        }
  
      sid::bus::status word_read(sid::host_int_4 addr,
--- 205,214 ----
  
      sid::bus::status word_write(sid::host_int_4 addr,
  				DataType mask,
! 				DataType data,
! 				DataType *written)
        {
! 	return (receiver->*write_callback) (addr, mask, data, written);
        }
  
      sid::bus::status word_read(sid::host_int_4 addr,
*************** namespace sidutil
*** 223,230 ****
      // Some macros to make manufacturing of the cartesian-product
      // calls simpler.
  #define SID_GB_WRITE(dtype) \
!       sid::bus::status write(sid::host_int_4 addr, dtype data) throw ()\
! 	  { if (LIKELY(*target)) return (*target)->write(addr, data); else return sid::bus::unpermitted; }
  
  #define SID_GB_READ(dtype) \
        sid::bus::status read(sid::host_int_4 addr, dtype& data) throw ()\
--- 239,246 ----
      // Some macros to make manufacturing of the cartesian-product
      // calls simpler.
  #define SID_GB_WRITE(dtype) \
!       sid::bus::status write(sid::host_int_4 addr, dtype data, dtype *written = 0) throw ()\
! 	  { if (LIKELY(*target)) return (*target)->write(addr, data, written); else return sid::bus::unpermitted; }
  
  #define SID_GB_READ(dtype) \
        sid::bus::status read(sid::host_int_4 addr, dtype& data) throw ()\
*************** namespace sidutil
*** 307,314 ****
      // Some macros to make manufacturing of the cartesian-product
      // calls simpler.
  #define SID_GB_WRITE(dtype) \
!       sid::bus::status write(sid::host_int_4 addr, dtype data) throw ()\
! 	  { if (LIKELY(*target)) return (*target)->write(addr, data); else return sid::bus::unmapped; }
  
  #define SID_GB_READ(dtype) \
        sid::bus::status read(sid::host_int_4 addr, dtype& data) throw ()\
--- 323,330 ----
      // Some macros to make manufacturing of the cartesian-product
      // calls simpler.
  #define SID_GB_WRITE(dtype) \
!       sid::bus::status write(sid::host_int_4 addr, dtype data, dtype *written = 0) throw ()\
! 	  { if (LIKELY(*target)) return (*target)->write(addr, data, written); else return sid::bus::unmapped; }
  
  #define SID_GB_READ(dtype) \
        sid::bus::status read(sid::host_int_4 addr, dtype& data) throw ()\
*************** namespace sidutil
*** 363,369 ****
  
      virtual sid::bus::status word_write(sid::host_int_4 addr,
  					DataType mask,
! 					DataType data) = 0;
  
      virtual sid::bus::status word_read(sid::host_int_4 addr,
  				       DataType mask,
--- 379,386 ----
  
      virtual sid::bus::status word_write(sid::host_int_4 addr,
  					DataType mask,
! 					DataType data,
! 					DataType *written) = 0;
  
      virtual sid::bus::status word_read(sid::host_int_4 addr,
  				       DataType mask,
*************** namespace sidutil
*** 374,383 ****
      // Some macros to make manufacturing of the cartesian-product
      // calls simpler.
  #define SID_GB_WRITE(type1,type2) \
!       sid::bus::status write(type1 addr, type2 data) throw () \
  	  { if (do_direct_passthrough (addr)) \
!                return (*target)->write(addr, data); \
!                return word_bus<DataType>::write(addr, data); }
      
  #define SID_GB_READ(type1,type2) \
        sid::bus::status read(type1 addr, type2& data) throw () \
--- 391,400 ----
      // Some macros to make manufacturing of the cartesian-product
      // calls simpler.
  #define SID_GB_WRITE(type1,type2) \
!       sid::bus::status write(type1 addr, type2 data, type2 *written = 0) throw () \
  	  { if (do_direct_passthrough (addr)) \
!                return (*target)->write(addr, data, written); \
!                return word_bus<DataType>::write(addr, data, written); }
      
  #define SID_GB_READ(type1,type2) \
        sid::bus::status read(type1 addr, type2& data) throw () \
*************** namespace sidutil
*** 460,471 ****
      // Some macros to make manufacturing of the cartesian-product
      // calls simpler.
  #define SID_GB_WRITE(type1) \
!       sid::bus::status write(sid::host_int_4 addr, type1 data) throw () \
  	  { sid::bus *bus = this->map_addr_to_bus (&addr); \
              if (UNLIKELY(bus == NULL)) \
                return sid::bus::unmapped; \
              else \
!               return bus->write(addr, data); }
      
  #define SID_GB_READ(type1) \
        sid::bus::status read(sid::host_int_4 addr, type1& data) throw () \
--- 477,488 ----
      // Some macros to make manufacturing of the cartesian-product
      // calls simpler.
  #define SID_GB_WRITE(type1) \
!       sid::bus::status write(sid::host_int_4 addr, type1 data, type1 *written = 0) throw () \
  	  { sid::bus *bus = this->map_addr_to_bus (&addr); \
              if (UNLIKELY(bus == NULL)) \
                return sid::bus::unmapped; \
              else \
!               return bus->write(addr, data, written); }
      
  #define SID_GB_READ(type1) \
        sid::bus::status read(sid::host_int_4 addr, type1& data) throw () \
*************** namespace sidutil
*** 509,530 ****
      ~byte_bus() throw() {}
      
      virtual sid::bus::status 
!     write_data(sid::host_int_4 addr, sid::host_int_1 data) throw () = 0;
      
      virtual sid::bus::status 
      read_data(sid::host_int_4 addr, sid::host_int_1& data) throw () = 0;
      
      // Byte accesses to a byte-wide component are easy.
      sid::bus::status 
!     write(sid::host_int_4 addr, sid::little_int_1 data) throw () 
        {
! 	return write_data(addr, data.integer_value() );
        }
  
      sid::bus::status 
!     write(sid::host_int_4 addr, sid::big_int_1 data) throw () 
        {
! 	return write_data( addr, data.integer_value() );
        }
      
      sid::bus::status 
--- 526,555 ----
      ~byte_bus() throw() {}
      
      virtual sid::bus::status 
!     write_data(sid::host_int_4 addr, sid::host_int_1 data, sid::host_int_1 *written) throw () = 0;
      
      virtual sid::bus::status 
      read_data(sid::host_int_4 addr, sid::host_int_1& data) throw () = 0;
      
      // Byte accesses to a byte-wide component are easy.
      sid::bus::status 
!     write(sid::host_int_4 addr, sid::little_int_1 data, sid::little_int_1 *written = 0) throw () 
        {
! 	sid::host_int_1 w;
! 	sid::bus::status s = write_data( addr, data.integer_value(), & w );
! 	if (written)
! 	  *written = w;
! 	return s;
        }
  
      sid::bus::status 
!     write(sid::host_int_4 addr, sid::big_int_1 data, sid::big_int_1 *written = 0) throw () 
        {
! 	sid::host_int_1 w;
! 	sid::bus::status s = write_data( addr, data.integer_value(), & w );
! 	if (written)
! 	  *written = w;
! 	return s;
        }
      
      sid::bus::status 
*************** namespace sidutil
*** 548,554 ****
      // Some macros to make manufacturing of the cartesian-product
      // calls simpler.
  #define BYTE_BUS_WRITE_A4(dtype) \
!     sid::bus::status write(sid::host_int_4 addr, dtype data ) throw () {\
            return sid::bus::unmapped; }
  
  #define BYTE_BUS_READ_A4(dtype)\
--- 573,579 ----
      // Some macros to make manufacturing of the cartesian-product
      // calls simpler.
  #define BYTE_BUS_WRITE_A4(dtype) \
!     sid::bus::status write(sid::host_int_4 addr, dtype data, dtype *written = 0 ) throw () {\
            return sid::bus::unmapped; }
  
  #define BYTE_BUS_READ_A4(dtype)\
*************** namespace sidutil
*** 586,592 ****
  		       sid::bus::status (Receiver::*r) ( 
  			 sid::host_int_4, sid::host_int_1& ),
  		       sid::bus::status (Receiver::*w) ( 
! 			 sid::host_int_4, sid::host_int_1 )
  		      ) : receiver(h), reader(r), writer(w) {}
  
      ~callback_byte_bus() throw() {}
--- 611,617 ----
  		       sid::bus::status (Receiver::*r) ( 
  			 sid::host_int_4, sid::host_int_1& ),
  		       sid::bus::status (Receiver::*w) ( 
! 			 sid::host_int_4, sid::host_int_1, sid::host_int_1 *)
  		      ) : receiver(h), reader(r), writer(w) {}
  
      ~callback_byte_bus() throw() {}
*************** namespace sidutil
*** 596,611 ****
      sid::bus::status (Receiver::*reader) ( sid::host_int_4 addr, 
  					   sid::host_int_1& data );
      sid::bus::status (Receiver::*writer) ( sid::host_int_4 addr, 
! 					   sid::host_int_1 data );
! 
      virtual sid::bus::status 
      read_data( sid::host_int_4 addr, sid::host_int_1& data ) throw() {
        return (receiver->*reader) ( addr, data );
      }
  
      virtual sid::bus::status 
!     write_data( sid::host_int_4 addr, sid::host_int_1 data ) throw() {
!       return (receiver->*writer) ( addr, data );
      }
      
    };
--- 621,636 ----
      sid::bus::status (Receiver::*reader) ( sid::host_int_4 addr, 
  					   sid::host_int_1& data );
      sid::bus::status (Receiver::*writer) ( sid::host_int_4 addr, 
! 					   sid::host_int_1 data,
! 					   sid::host_int_1 *written );
      virtual sid::bus::status 
      read_data( sid::host_int_4 addr, sid::host_int_1& data ) throw() {
        return (receiver->*reader) ( addr, data );
      }
  
      virtual sid::bus::status 
!     write_data( sid::host_int_4 addr, sid::host_int_1 data, sid::host_int_1 *written ) throw() {
!       return (receiver->*writer) ( addr, data, written );
      }
      
    };
*************** namespace sidutil
*** 671,677 ****
    class control_register
    {
    public:
!     virtual void set (DataType set_value, DataType set_mask) = 0;
      virtual DataType get () = 0;
      DataType get_mask() const { return this->field_mask; }
      
--- 696,702 ----
    class control_register
    {
    public:
!     virtual DataType set (DataType set_value, DataType set_mask) = 0;
      virtual DataType get () = 0;
      DataType get_mask() const { return this->field_mask; }
      
*************** namespace sidutil
*** 723,731 ****
      typedef typename DataType::value_type ValueType;
  
    public:
!     void set (DataType set_value, DataType set_mask)
        {
! 	this->field_value = (this->field_value & ~set_mask) | (set_value & set_mask);
        }
  
  
--- 748,756 ----
      typedef typename DataType::value_type ValueType;
  
    public:
!     DataType set (DataType set_value, DataType set_mask)
        {
! 	return this->field_value = (this->field_value & ~set_mask) | (set_value & set_mask);
        }
  
  
*************** namespace sidutil
*** 833,841 ****
        }
  
    protected:
!     void set (DataType set_value, DataType set_mask)
      {
!       // do nothing
      }
    };
  
--- 858,866 ----
        }
  
    protected:
!     DataType set (DataType set_value, DataType set_mask)
      {
!       return get (); // do nothing
      }
    };
  
*************** namespace sidutil
*** 862,870 ****
      {}
  
    protected:
!     void set (DataType set_value, DataType set_mask)
        {
  	// do nothing
  	// XXX: check for match with field_value?
        }
    };
--- 887,896 ----
      {}
  
    protected:
!     DataType set (DataType set_value, DataType set_mask)
        {
  	// do nothing
+ 	return get ();
  	// XXX: check for match with field_value?
        }
    };
*************** namespace sidutil
*** 882,888 ****
  			      bool r,
  			      bool w,
  			      Class* rec, 
! 			      void (Class::*s)(DataType, DataType), 
  			      DataType (Class::*g)()): 
        control_register<DataType>(b,o,m,r,w),
        receiver(rec),
--- 908,914 ----
  			      bool r,
  			      bool w,
  			      Class* rec, 
! 			      DataType (Class::*s)(DataType, DataType), 
  			      DataType (Class::*g)()): 
        control_register<DataType>(b,o,m,r,w),
        receiver(rec),
*************** namespace sidutil
*** 911,917 ****
  			      bool r,
  			      bool w,
  			      Class* rec, 
! 			      void (Class::*s)(DataType, DataType)):
        control_register<DataType>(b,o,m,r,w),
        receiver(rec),
        set_callback(s),
--- 937,943 ----
  			      bool r,
  			      bool w,
  			      Class* rec, 
! 			      DataType (Class::*s)(DataType, DataType)):
        control_register<DataType>(b,o,m,r,w),
        receiver(rec),
        set_callback(s),
*************** namespace sidutil
*** 920,932 ****
  
    private:
      Class* receiver;
!     void (Class::*set_callback) (DataType, DataType);
      DataType (Class::*get_callback) ();
  
!     void set (DataType set_value, DataType set_mask)
        {
  	assert(this->set_callback);
! 	(receiver->*set_callback)(set_value, set_mask); 
        }
  
      DataType get ()
--- 946,958 ----
  
    private:
      Class* receiver;
!     DataType (Class::*set_callback) (DataType, DataType);
      DataType (Class::*get_callback) ();
  
!     DataType set (DataType set_value, DataType set_mask)
        {
  	assert(this->set_callback);
! 	return (receiver->*set_callback)(set_value, set_mask); 
        }
  
      DataType get ()
*************** namespace sidutil
*** 948,954 ****
    protected:
      sid::bus::status word_write(sid::host_int_4 addr,
  				DataType mask,
! 				DataType data)
        {
  	typename control_register_bus<DataType>::reg_map::iterator i = 
  		 this->write_map.find(addr);
--- 974,981 ----
    protected:
      sid::bus::status word_write(sid::host_int_4 addr,
  				DataType mask,
! 				DataType data,
! 				DataType *written)
        {
  	typename control_register_bus<DataType>::reg_map::iterator i = 
  		 this->write_map.find(addr);
*************** namespace sidutil
*** 974,979 ****
--- 1001,1013 ----
  		// Hand over the masked data value.  Use both the
  		// incoming write mask and the control register mask
  		reg->set (data & mask & reg_mask, reg_mask & mask);
+ 		// Update the actual data written.
+ 		if (written)
+ 		  {
+ 		    *written = *written & ~(reg_mask & mask);
+ 		    DataType d = reg->get ();
+ 		    *written = *written | (d & reg_mask & mask);
+ 		  }
  	      }
  	  }
  
Index: sid/include/sidcomp.h
===================================================================
RCS file: /cvs/src/src/sid/include/sidcomp.h,v
retrieving revision 1.5
diff -c -p -r1.5 sidcomp.h
*** sid/include/sidcomp.h	25 Jun 2001 01:45:28 -0000	1.5
--- sid/include/sidcomp.h	17 Mar 2004 20:49:04 -0000
***************
*** 1,7 ****
  // sidcomp.h - Define the external interface of a SID component, that
  // is, the SID component API expressed in -*- C++ -*-.
  
! // Copyright (C) 1999, 2000, 2001 Red Hat.
  // This file is part of SID and is licensed under the GPL.
  // See the file COPYING.SID for conditions for redistribution.
  
--- 1,7 ----
  // sidcomp.h - Define the external interface of a SID component, that
  // is, the SID component API expressed in -*- C++ -*-.
  
! // Copyright (C) 1999-2001, 2004 Red Hat.
  // This file is part of SID and is licensed under the GPL.
  // See the file COPYING.SID for conditions for redistribution.
  
*************** namespace sid
*** 23,29 ****
    // interopration attempts with obsolete component objects.
  
    const unsigned API_MAJOR_VERSION = 3;
!   const unsigned API_MINOR_VERSION = 2;
  
    // PART 1: Buses
    //
--- 23,29 ----
    // interopration attempts with obsolete component objects.
  
    const unsigned API_MAJOR_VERSION = 3;
!   const unsigned API_MINOR_VERSION = 3;
  
    // PART 1: Buses
    //
*************** namespace sid
*** 69,99 ****
  
      // Write data at given address.
  
!     virtual status write(host_int_4 addr, big_int_1 data) 
        throw () = 0;
  
!     virtual status write(host_int_4 addr, little_int_1 data) 
        throw () = 0;
  
!     virtual status write(host_int_4 addr, big_int_2 data) 
        throw () = 0;
  
!     virtual status write(host_int_4 addr, little_int_2 data) 
        throw () = 0;
  
!     virtual status write(host_int_4 addr, big_int_4 data)
        throw () = 0;
  
!     virtual status write(host_int_4 addr, little_int_4 data)
        throw () = 0;
  
!     virtual status write(host_int_4 addr, big_int_8 data) 
        throw () = 0;
  
!     virtual status write(host_int_4 addr, little_int_8 data)
        throw () = 0;
  
!     // Write data from given address.
      virtual status
      read(host_int_4 addr, big_int_1& data)
        throw () = 0;
--- 69,99 ----
  
      // Write data at given address.
  
!     virtual status write(host_int_4 addr, big_int_1 data, big_int_1 *written = 0) 
        throw () = 0;
  
!     virtual status write(host_int_4 addr, little_int_1 data, little_int_1 *written = 0) 
        throw () = 0;
  
!     virtual status write(host_int_4 addr, big_int_2 data, big_int_2 *written = 0) 
        throw () = 0;
  
!     virtual status write(host_int_4 addr, little_int_2 data, little_int_2 *written = 0) 
        throw () = 0;
  
!     virtual status write(host_int_4 addr, big_int_4 data, big_int_4 *written = 0)
        throw () = 0;
  
!     virtual status write(host_int_4 addr, little_int_4 data, little_int_4 *written = 0)
        throw () = 0;
  
!     virtual status write(host_int_4 addr, big_int_8 data, big_int_8 *written = 0) 
        throw () = 0;
  
!     virtual status write(host_int_4 addr, little_int_8 data, little_int_8 *written = 0)
        throw () = 0;
  
!     // Read data from given address.
      virtual status
      read(host_int_4 addr, big_int_1& data)
        throw () = 0;
Index: sid/include/sidcpuutil.h
===================================================================
RCS file: /cvs/src/src/sid/include/sidcpuutil.h,v
retrieving revision 1.27
diff -c -p -r1.27 sidcpuutil.h
*** sid/include/sidcpuutil.h	21 Oct 2003 21:38:24 -0000	1.27
--- sid/include/sidcpuutil.h	17 Mar 2004 20:49:04 -0000
***************
*** 1,6 ****
  // sidcpuutil.h - Elements common to CPU models.  -*- C++ -*-
  
! // Copyright (C) 1999, 2000, 2001, 2002, 2003 Red Hat.
  // This file is part of SID and is licensed under the GPL.
  // See the file COPYING.SID for conditions for redistribution.
  
--- 1,6 ----
  // sidcpuutil.h - Elements common to CPU models.  -*- C++ -*-
  
! // Copyright (C) 1999-2004 Red Hat.
  // This file is part of SID and is licensed under the GPL.
  // See the file COPYING.SID for conditions for redistribution.
  
*************** public:
*** 647,660 ****
      template <typename BigOrLittleInt>
      BigOrLittleInt basic_cpu::write_insn_memory (sid::host_int_4 pc, sid::host_int_4 address, BigOrLittleInt value) const
        {
  	sid::bus::status s;
  	if (LIKELY(this->insn_bus))
! 	  s = this->insn_bus->write (address, value);
  	else
  	  s = sid::bus::unmapped;
  	total_latency += s.latency;
  	if (LIKELY(s == sid::bus::ok))
! 	  return value;
  
  	throw cpu_memory_fault (pc, address, s, "insn write");
        }
--- 647,661 ----
      template <typename BigOrLittleInt>
      BigOrLittleInt basic_cpu::write_insn_memory (sid::host_int_4 pc, sid::host_int_4 address, BigOrLittleInt value) const
        {
+ 	BigOrLittleInt written;
  	sid::bus::status s;
  	if (LIKELY(this->insn_bus))
! 	  s = this->insn_bus->write (address, value, & written);
  	else
  	  s = sid::bus::unmapped;
  	total_latency += s.latency;
  	if (LIKELY(s == sid::bus::ok))
! 	  return written;
  
  	throw cpu_memory_fault (pc, address, s, "insn write");
        }
*************** public:
*** 678,691 ****
      template <typename BigOrLittleInt>
      BigOrLittleInt basic_cpu::write_data_memory (sid::host_int_4 pc, sid::host_int_4 address, BigOrLittleInt value) const
        {
  	sid::bus::status s;
  	if (LIKELY(this->data_bus))
! 	  s = this->data_bus->write (address, value);
  	else
  	  s = sid::bus::unmapped;
  	total_latency += s.latency;
  	if (LIKELY(s == sid::bus::ok))
! 	  return value;
  
  	throw cpu_memory_fault (pc, address, s, "data write");
        }
--- 679,693 ----
      template <typename BigOrLittleInt>
      BigOrLittleInt basic_cpu::write_data_memory (sid::host_int_4 pc, sid::host_int_4 address, BigOrLittleInt value) const
        {
+ 	BigOrLittleInt written;
  	sid::bus::status s;
  	if (LIKELY(this->data_bus))
! 	  s = this->data_bus->write (address, value, & written);
  	else
  	  s = sid::bus::unmapped;
  	total_latency += s.latency;
  	if (LIKELY(s == sid::bus::ok))
! 	  return written;
  
  	throw cpu_memory_fault (pc, address, s, "data write");
        }
*************** public:
*** 727,750 ****
  	return this->read_insn_memory (pc, address, sid::big_int_8());
        }
  
!     void write_insn_memory_1 (sid::host_int_4 pc, sid::host_int_4 address, sid::host_int_1 value) const
        {
! 	this->write_insn_memory (pc, address, sid::big_int_1(value));
        }
  
!     void write_insn_memory_2 (sid::host_int_4 pc, sid::host_int_4 address, sid::host_int_2 value) const
        {
! 	this->write_insn_memory (pc, address, sid::big_int_2(value));
        }
  
!     void write_insn_memory_4 (sid::host_int_4 pc, sid::host_int_4 address, sid::host_int_4 value) const
        {
! 	this->write_insn_memory (pc, address, sid::big_int_4(value));
        }
  
!     void write_insn_memory_8 (sid::host_int_4 pc, sid::host_int_4 address, sid::host_int_8 value) const
        {
! 	this->write_insn_memory (pc, address, sid::big_int_8(value));
        }
  
      sid::host_int_1 read_data_memory_1 (sid::host_int_4 pc, sid::host_int_4 address) const
--- 729,752 ----
  	return this->read_insn_memory (pc, address, sid::big_int_8());
        }
  
!     sid::host_int_1 write_insn_memory_1 (sid::host_int_4 pc, sid::host_int_4 address, sid::host_int_1 value) const
        {
! 	return this->write_insn_memory (pc, address, sid::big_int_1(value));
        }
  
!     sid::host_int_2 write_insn_memory_2 (sid::host_int_4 pc, sid::host_int_4 address, sid::host_int_2 value) const
        {
! 	return this->write_insn_memory (pc, address, sid::big_int_2(value));
        }
  
!     sid::host_int_4 write_insn_memory_4 (sid::host_int_4 pc, sid::host_int_4 address, sid::host_int_4 value) const
        {
! 	return this->write_insn_memory (pc, address, sid::big_int_4(value));
        }
  
!     sid::host_int_8 write_insn_memory_8 (sid::host_int_4 pc, sid::host_int_4 address, sid::host_int_8 value) const
        {
! 	return this->write_insn_memory (pc, address, sid::big_int_8(value));
        }
  
      sid::host_int_1 read_data_memory_1 (sid::host_int_4 pc, sid::host_int_4 address) const
*************** public:
*** 767,790 ****
  	return this->read_data_memory (pc, address, sid::big_int_8());
        }
  
!     void write_data_memory_1 (sid::host_int_4 pc, sid::host_int_4 address, sid::host_int_1 value) const
        {
! 	this->write_data_memory (pc, address, sid::big_int_1(value));
        }
  
!     void write_data_memory_2 (sid::host_int_4 pc, sid::host_int_4 address, sid::host_int_2 value) const
        {
! 	this->write_data_memory (pc, address, sid::big_int_2(value));
        }
  
!     void write_data_memory_4 (sid::host_int_4 pc, sid::host_int_4 address, sid::host_int_4 value) const
        {
! 	this->write_data_memory (pc, address, sid::big_int_4(value));
        }
  
!     void write_data_memory_8 (sid::host_int_4 pc, sid::host_int_4 address, sid::host_int_8 value) const
        {
! 	this->write_data_memory (pc, address, sid::big_int_8(value));
        }
    };
  
--- 769,792 ----
  	return this->read_data_memory (pc, address, sid::big_int_8());
        }
  
!     sid::host_int_1 write_data_memory_1 (sid::host_int_4 pc, sid::host_int_4 address, sid::host_int_1 value) const
        {
! 	return this->write_data_memory (pc, address, sid::big_int_1(value));
        }
  
!     sid::host_int_2 write_data_memory_2 (sid::host_int_4 pc, sid::host_int_4 address, sid::host_int_2 value) const
        {
! 	return this->write_data_memory (pc, address, sid::big_int_2(value));
        }
  
!     sid::host_int_4 write_data_memory_4 (sid::host_int_4 pc, sid::host_int_4 address, sid::host_int_4 value) const
        {
! 	return this->write_data_memory (pc, address, sid::big_int_4(value));
        }
  
!     sid::host_int_8 write_data_memory_8 (sid::host_int_4 pc, sid::host_int_4 address, sid::host_int_8 value) const
        {
! 	return this->write_data_memory (pc, address, sid::big_int_8(value));
        }
    };
  
*************** public:
*** 822,845 ****
  	return this->read_insn_memory (pc, address, sid::little_int_8());
        }
  
!     void write_insn_memory_1 (sid::host_int_4 pc, sid::host_int_4 address, sid::host_int_1 value) const
        {
! 	this->write_insn_memory (pc, address, sid::little_int_1(value));
        }
  
!     void write_insn_memory_2 (sid::host_int_4 pc, sid::host_int_4 address, sid::host_int_2 value) const
        {
! 	this->write_insn_memory (pc, address, sid::little_int_2(value));
        }
  
!     void write_insn_memory_4 (sid::host_int_4 pc, sid::host_int_4 address, sid::host_int_4 value) const
        {
! 	this->write_insn_memory (pc, address, sid::little_int_4(value));
        }
  
!     void write_insn_memory_8 (sid::host_int_4 pc, sid::host_int_4 address, sid::host_int_8 value) const
        {
! 	this->write_insn_memory (pc, address, sid::little_int_8(value));
        }
  
      sid::host_int_1 read_data_memory_1 (sid::host_int_4 pc, sid::host_int_4 address) const
--- 824,847 ----
  	return this->read_insn_memory (pc, address, sid::little_int_8());
        }
  
!     sid::host_int_1 write_insn_memory_1 (sid::host_int_4 pc, sid::host_int_4 address, sid::host_int_1 value) const
        {
! 	return this->write_insn_memory (pc, address, sid::little_int_1(value));
        }
  
!     sid::host_int_2 write_insn_memory_2 (sid::host_int_4 pc, sid::host_int_4 address, sid::host_int_2 value) const
        {
! 	return this->write_insn_memory (pc, address, sid::little_int_2(value));
        }
  
!     sid::host_int_4 write_insn_memory_4 (sid::host_int_4 pc, sid::host_int_4 address, sid::host_int_4 value) const
        {
! 	return this->write_insn_memory (pc, address, sid::little_int_4(value));
        }
  
!     sid::host_int_8 write_insn_memory_8 (sid::host_int_4 pc, sid::host_int_4 address, sid::host_int_8 value) const
        {
! 	return this->write_insn_memory (pc, address, sid::little_int_8(value));
        }
  
      sid::host_int_1 read_data_memory_1 (sid::host_int_4 pc, sid::host_int_4 address) const
*************** public:
*** 862,885 ****
  	return this->read_data_memory (pc, address, sid::little_int_8());
        }
  
!     void write_data_memory_1 (sid::host_int_4 pc, sid::host_int_4 address, sid::host_int_1 value) const
        {
! 	this->write_data_memory (pc, address, sid::little_int_1(value));
        }
  
!     void write_data_memory_2 (sid::host_int_4 pc, sid::host_int_4 address, sid::host_int_2 value) const
        {
! 	this->write_data_memory (pc, address, sid::little_int_2(value));
        }
  
!     void write_data_memory_4 (sid::host_int_4 pc, sid::host_int_4 address, sid::host_int_4 value) const
        {
! 	this->write_data_memory (pc, address, sid::little_int_4(value));
        }
  
!     void write_data_memory_8 (sid::host_int_4 pc, sid::host_int_4 address, sid::host_int_8 value) const
        {
! 	this->write_data_memory (pc, address, sid::little_int_8(value));
        }
    };
  
--- 864,887 ----
  	return this->read_data_memory (pc, address, sid::little_int_8());
        }
  
!     sid::host_int_1 write_data_memory_1 (sid::host_int_4 pc, sid::host_int_4 address, sid::host_int_1 value) const
        {
! 	return this->write_data_memory (pc, address, sid::little_int_1(value));
        }
  
!     sid::host_int_2 write_data_memory_2 (sid::host_int_4 pc, sid::host_int_4 address, sid::host_int_2 value) const
        {
! 	return this->write_data_memory (pc, address, sid::little_int_2(value));
        }
  
!     sid::host_int_4 write_data_memory_4 (sid::host_int_4 pc, sid::host_int_4 address, sid::host_int_4 value) const
        {
! 	return this->write_data_memory (pc, address, sid::little_int_4(value));
        }
  
!     sid::host_int_8 write_data_memory_8 (sid::host_int_4 pc, sid::host_int_4 address, sid::host_int_8 value) const
        {
! 	return this->write_data_memory (pc, address, sid::little_int_8(value));
        }
    };
  
*************** public:
*** 962,997 ****
  	  return this->read_insn_memory (pc, address, sid::big_int_8());
        }
  
!     void write_insn_memory_1 (sid::host_int_4 pc, sid::host_int_4 address, sid::host_int_1 value) const
        {
  	if (this->_current_endianness == endian_little)
! 	  this->write_insn_memory (pc, address, sid::little_int_1(value));
  	else // endian_big or endian_unknown
! 	  this->write_insn_memory (pc, address, sid::big_int_1(value));
        }
  
!     void write_insn_memory_2 (sid::host_int_4 pc, sid::host_int_4 address, sid::host_int_2 value) const
        {
  	if (this->_current_endianness == endian_little)
! 	  this->write_insn_memory (pc, address, sid::little_int_2(value));
  	else // endian_big or endian_unknown
! 	  this->write_insn_memory (pc, address, sid::big_int_2(value));
        }
  
!     void write_insn_memory_4 (sid::host_int_4 pc, sid::host_int_4 address, sid::host_int_4 value) const
        {
  	if (this->_current_endianness == endian_little)
! 	  this->write_insn_memory (pc, address, sid::little_int_4(value));
  	else // endian_big or endian_unknown
! 	  this->write_insn_memory (pc, address, sid::big_int_4(value));
        }
  
!     void write_insn_memory_8 (sid::host_int_4 pc, sid::host_int_4 address, sid::host_int_8 value) const
        {
  	if (this->_current_endianness == endian_little)
! 	  this->write_insn_memory (pc, address, sid::little_int_8(value));
  	else // endian_big or endian_unknown
! 	  this->write_insn_memory (pc, address, sid::big_int_8(value));
        }
  
      sid::host_int_1 read_data_memory_1 (sid::host_int_4 pc, sid::host_int_4 address) const
--- 964,999 ----
  	  return this->read_insn_memory (pc, address, sid::big_int_8());
        }
  
!     sid::host_int_1 write_insn_memory_1 (sid::host_int_4 pc, sid::host_int_4 address, sid::host_int_1 value) const
        {
  	if (this->_current_endianness == endian_little)
! 	  return this->write_insn_memory (pc, address, sid::little_int_1(value));
  	else // endian_big or endian_unknown
! 	  return this->write_insn_memory (pc, address, sid::big_int_1(value));
        }
  
!     sid::host_int_2 write_insn_memory_2 (sid::host_int_4 pc, sid::host_int_4 address, sid::host_int_2 value) const
        {
  	if (this->_current_endianness == endian_little)
! 	  return this->write_insn_memory (pc, address, sid::little_int_2(value));
  	else // endian_big or endian_unknown
! 	  return this->write_insn_memory (pc, address, sid::big_int_2(value));
        }
  
!     sid::host_int_4 write_insn_memory_4 (sid::host_int_4 pc, sid::host_int_4 address, sid::host_int_4 value) const
        {
  	if (this->_current_endianness == endian_little)
! 	  return this->write_insn_memory (pc, address, sid::little_int_4(value));
  	else // endian_big or endian_unknown
! 	  return this->write_insn_memory (pc, address, sid::big_int_4(value));
        }
  
!     sid::host_int_8 write_insn_memory_8 (sid::host_int_4 pc, sid::host_int_4 address, sid::host_int_8 value) const
        {
  	if (this->_current_endianness == endian_little)
! 	  return this->write_insn_memory (pc, address, sid::little_int_8(value));
  	else // endian_big or endian_unknown
! 	  return this->write_insn_memory (pc, address, sid::big_int_8(value));
        }
  
      sid::host_int_1 read_data_memory_1 (sid::host_int_4 pc, sid::host_int_4 address) const
*************** public:
*** 1026,1061 ****
  	  return this->read_data_memory (pc, address, sid::big_int_8());
        }
  
!     void write_data_memory_1 (sid::host_int_4 pc, sid::host_int_4 address, sid::host_int_1 value) const
        {
  	if (this->_current_endianness == endian_little)
! 	  this->write_data_memory (pc, address, sid::little_int_1(value));
  	else // endian_big or endian_unknown
! 	  this->write_data_memory (pc, address, sid::big_int_1(value));
        }
  
!     void write_data_memory_2 (sid::host_int_4 pc, sid::host_int_4 address, sid::host_int_2 value) const
        {
  	if (this->_current_endianness == endian_little)
! 	  this->write_data_memory (pc, address, sid::little_int_2(value));
  	else // endian_big or endian_unknown
! 	  this->write_data_memory (pc, address, sid::big_int_2(value));
        }
  
!     void write_data_memory_4 (sid::host_int_4 pc, sid::host_int_4 address, sid::host_int_4 value) const
        {
  	if (this->_current_endianness == endian_little)
! 	  this->write_data_memory (pc, address, sid::little_int_4(value));
  	else // endian_big or endian_unknown
! 	  this->write_data_memory (pc, address, sid::big_int_4(value));
        }
  
!     void write_data_memory_8 (sid::host_int_4 pc, sid::host_int_4 address, sid::host_int_8 value) const
        {
  	if (this->_current_endianness == endian_little)
! 	  this->write_data_memory (pc, address, sid::little_int_8(value));
  	else // endian_big or endian_unknown
! 	  this->write_data_memory (pc, address, sid::big_int_8(value));
        }
    };
  
--- 1028,1063 ----
  	  return this->read_data_memory (pc, address, sid::big_int_8());
        }
  
!     sid::host_int_1 write_data_memory_1 (sid::host_int_4 pc, sid::host_int_4 address, sid::host_int_1 value) const
        {
  	if (this->_current_endianness == endian_little)
! 	  return this->write_data_memory (pc, address, sid::little_int_1(value));
  	else // endian_big or endian_unknown
! 	  return this->write_data_memory (pc, address, sid::big_int_1(value));
        }
  
!     sid::host_int_2 write_data_memory_2 (sid::host_int_4 pc, sid::host_int_4 address, sid::host_int_2 value) const
        {
  	if (this->_current_endianness == endian_little)
! 	  return this->write_data_memory (pc, address, sid::little_int_2(value));
  	else // endian_big or endian_unknown
! 	  return this->write_data_memory (pc, address, sid::big_int_2(value));
        }
  
!     sid::host_int_4 write_data_memory_4 (sid::host_int_4 pc, sid::host_int_4 address, sid::host_int_4 value) const
        {
  	if (this->_current_endianness == endian_little)
! 	  return this->write_data_memory (pc, address, sid::little_int_4(value));
  	else // endian_big or endian_unknown
! 	  return this->write_data_memory (pc, address, sid::big_int_4(value));
        }
  
!     sid::host_int_8 write_data_memory_8 (sid::host_int_4 pc, sid::host_int_4 address, sid::host_int_8 value) const
        {
  	if (this->_current_endianness == endian_little)
! 	  return this->write_data_memory (pc, address, sid::little_int_8(value));
  	else // endian_big or endian_unknown
! 	  return this->write_data_memory (pc, address, sid::big_int_8(value));
        }
    };
  
Index: sid/samples/timer.cxx
===================================================================
RCS file: /cvs/src/src/sid/samples/timer.cxx,v
retrieving revision 1.2
diff -c -p -r1.2 timer.cxx
*** sid/samples/timer.cxx	3 Aug 2001 06:02:48 -0000	1.2
--- sid/samples/timer.cxx	17 Mar 2004 20:49:04 -0000
***************
*** 1,6 ****
  // timer.cxx - an example of a SID component implementation.  -*- C++ -*-
  
! // Copyright (C) 1999, 2000 Red Hat.
  // This file is part of SID and is licensed under the GPL.
  // See the file COPYING.SID for conditions for redistribution.
  
--- 1,6 ----
  // timer.cxx - an example of a SID component implementation.  -*- C++ -*-
  
! // Copyright (C) 1999, 2000, 2004 Red Hat.
  // This file is part of SID and is licensed under the GPL.
  // See the file COPYING.SID for conditions for redistribution.
  
*************** private:
*** 126,139 ****
      sid::bus::status read(sid::host_int_4 addr,sid::little_int_8& data) throw();
      sid::bus::status read(sid::host_int_4 addr,sid::big_int_8& data) throw();
  
!     sid::bus::status write(sid::host_int_4 addr,sid::little_int_1 data) throw();
!     sid::bus::status write(sid::host_int_4 addr,sid::big_int_1 data) throw();
!     sid::bus::status write(sid::host_int_4 addr,sid::little_int_2 data) throw();
!     sid::bus::status write(sid::host_int_4 addr,sid::big_int_2 data) throw();
!     sid::bus::status write(sid::host_int_4 addr,sid::little_int_4 data) throw();
!     sid::bus::status write(sid::host_int_4 addr,sid::big_int_4 data) throw();
!     sid::bus::status write(sid::host_int_4 addr,sid::little_int_8 data) throw();
!     sid::bus::status write(sid::host_int_4 addr,sid::big_int_8 data) throw();
  
    private:
      Timer* timer;
--- 126,139 ----
      sid::bus::status read(sid::host_int_4 addr,sid::little_int_8& data) throw();
      sid::bus::status read(sid::host_int_4 addr,sid::big_int_8& data) throw();
  
!     sid::bus::status write(sid::host_int_4 addr,sid::little_int_1 data, sid::little_int_1 *written = 0) throw();
!     sid::bus::status write(sid::host_int_4 addr,sid::big_int_1 data, sid::big_int_1 *written = 0) throw();
!     sid::bus::status write(sid::host_int_4 addr,sid::little_int_2 data, sid::little_int_2 *written = 0) throw();
!     sid::bus::status write(sid::host_int_4 addr,sid::big_int_2 data, sid::big_int_2 *written = 0) throw();
!     sid::bus::status write(sid::host_int_4 addr,sid::little_int_4 data, sid::little_int_4 *written = 0) throw();
!     sid::bus::status write(sid::host_int_4 addr,sid::big_int_4 data, sid::big_int_4 *written = 0) throw();
!     sid::bus::status write(sid::host_int_4 addr,sid::little_int_8 data, sid::little_int_8 *written = 0) throw();
!     sid::bus::status write(sid::host_int_4 addr,sid::big_int_8 data, sid::big_int_8 *written = 0) throw();
  
    private:
      Timer* timer;
*************** Timer::register_bus::read(sid::host_int_
*** 476,486 ****
  // address, return an error.
  
  sid::bus::status
! Timer::register_bus::write(sid::host_int_4 addr, sid::little_int_4 data) throw()
  {
    if (addr % 4 != 0)
      return sid::bus::misaligned;
    
    switch (addr)
      {
      case 0x0:
--- 476,488 ----
  // address, return an error.
  
  sid::bus::status
! Timer::register_bus::write(sid::host_int_4 addr, sid::little_int_4 data, sid::little_int_4 *written) throw()
  {
    if (addr % 4 != 0)
      return sid::bus::misaligned;
    
+   if (written) *written = data;
+ 
    switch (addr)
      {
      case 0x0:
*************** Timer::register_bus::write(sid::host_int
*** 518,528 ****
  // Just rearrange the data and do a little endian write.
  
  sid::bus::status
! Timer::register_bus::write(sid::host_int_4 addr, sid::big_int_4 data) throw()
  {
    sid::little_int_4 le_data;
    le_data.set_target_memory_value (data.target_memory_value ());
!   return write(addr, le_data);
  }
  
  // For simplicity, bus accesses that are not 32-bits wide are not
--- 520,533 ----
  // Just rearrange the data and do a little endian write.
  
  sid::bus::status
! Timer::register_bus::write(sid::host_int_4 addr, sid::big_int_4 data, sid::big_int_4 *written) throw()
  {
    sid::little_int_4 le_data;
+   sid::little_int_4 le_written;
    le_data.set_target_memory_value (data.target_memory_value ());
!   sid::bus::status s = write(addr, le_data, & le_written);
!   if (written) *written = le_written;
!   return s;
  }
  
  // For simplicity, bus accesses that are not 32-bits wide are not
*************** Timer::register_bus::read(sid::host_int_
*** 567,603 ****
  }
  
  sid::bus::status
! Timer::register_bus::write(sid::host_int_4 addr, sid::little_int_1 data) throw()
  {
    return sid::bus::unpermitted;
  }
  
  sid::bus::status
! Timer::register_bus::write(sid::host_int_4 addr, sid::big_int_1 data) throw()
  {
    return sid::bus::unpermitted;
  }
  
  sid::bus::status
! Timer::register_bus::write(sid::host_int_4 addr, sid::little_int_2 data) throw()
  {
    return sid::bus::unpermitted;
  }
  
  sid::bus::status
! Timer::register_bus::write(sid::host_int_4 addr, sid::big_int_2 data) throw()
  {
    return sid::bus::unpermitted;
  }
  
  sid::bus::status
! Timer::register_bus::write(sid::host_int_4 addr, sid::little_int_8 data) throw()
  {
    return sid::bus::unpermitted;
  }
  
  sid::bus::status
! Timer::register_bus::write(sid::host_int_4 addr, sid::big_int_8 data) throw()
  {
    return sid::bus::unpermitted;
  }
--- 572,608 ----
  }
  
  sid::bus::status
! Timer::register_bus::write(sid::host_int_4 addr, sid::little_int_1 data, sid::little_int_1 *written) throw()
  {
    return sid::bus::unpermitted;
  }
  
  sid::bus::status
! Timer::register_bus::write(sid::host_int_4 addr, sid::big_int_1 data, sid::big_int_1 *written) throw()
  {
    return sid::bus::unpermitted;
  }
  
  sid::bus::status
! Timer::register_bus::write(sid::host_int_4 addr, sid::little_int_2 data, sid::little_int_2 *written) throw()
  {
    return sid::bus::unpermitted;
  }
  
  sid::bus::status
! Timer::register_bus::write(sid::host_int_4 addr, sid::big_int_2 data, sid::big_int_2 *written) throw()
  {
    return sid::bus::unpermitted;
  }
  
  sid::bus::status
! Timer::register_bus::write(sid::host_int_4 addr, sid::little_int_8 data, sid::little_int_8 *written) throw()
  {
    return sid::bus::unpermitted;
  }
  
  sid::bus::status
! Timer::register_bus::write(sid::host_int_4 addr, sid::big_int_8 data, sid::big_int_8 *written) throw()
  {
    return sid::bus::unpermitted;
  }

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